Attention is currently required from: Angel Pons.
4 comments:
File src/mainboard/fujitsu/d3410-b1/bootblock.c:
We had a private discussion on this already, so just for the record:
1. IMO all pads should be configured, even if they match the "reset" values, because the GPIO file also serves as sort-of documentation how the pads are configured.
2. Reset values:
There is a possibility to change these "reset" values using the FIT tool. On ME-platforms only a few pads can be configured, while on server platforms (SPS) many more pads' reset values/functions can be edited via dropdowns.
That means, the values in the datasheet is the hardware reset value but software (probably ME) can override them and we can't always rely on these values and should instead always configure all pads, so we have a defined, sane state.
Patch Set #12, Line 11: UP_20K
uhm, that is 0b1100, which is only valid in eSPI mode. LPC *must* have `NATIVE` (0b1111) here, according to the pch ds vol2. does that board use eSPI?
inteltooldump says 0b11 (reserved), just like the GPP_I* below
PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I1, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I2, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I3, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I5, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I6, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I7, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I8, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I9, NONE, PWROK, NF1),
PAD_CFG_NF(GPP_I10, NONE, PWROK, NF1),
your inteltool dump says PADRSTCFG=0b11, which is "Reserved"... eds also says reserved... hmm. default for these pads is DEEP, which should be ok
To view, visit change 48383. To unsubscribe, or for help writing mail filters, visit settings.