Name of user not set #1002789 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from sandybridge with vendor IDs updated to the correct haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-29 kernel. Without patches dmesg reports noveau is unable to read the ROM of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With patches drm appears to be initalized and dmesg only reports an error I assume is related to the Optimus setup of "DRM: Pointer to TMDS table invalid".
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan macromorgan@hotmail.com --- M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl A src/northbridge/intel/haswell/acpi/peg.asl A src/northbridge/intel/haswell/pcie.c 5 files changed, 156 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38743/1
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b986336..73a20f2 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -19,6 +19,7 @@
ramstage-y += memmap.c ramstage-y += northbridge.c +ramstage-y += pcie.c ramstage-y += gma.c
ramstage-y += acpi.c diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 45ebff2..2db72d7 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -16,6 +16,7 @@
#include "../haswell.h" #include "hostbridge.asl" +#include "peg.asl" #include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 19d788c..d567701 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -36,7 +36,8 @@ MHEN, 1, // Enable , 13, // MHBR, 22, // MCHBAR - + Offset (0x54), + DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl new file mode 100644 index 0000000..07f7cdf --- /dev/null +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph siro@das-labor.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + Method (_STA) + { + ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) + Return (And (Local0, 1)) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG1) +{ + Name (_ADR, 0x00010001) + + Method (_STA) + { + ShiftRight (_SB.PCI0.MCHC.DVEN, 2, Local0) + Return (And (Local0, 1)) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG2) +{ + Name (_ADR, 0x00010002) + + Method (_STA) + { + ShiftRight (_SB.PCI0.MCHC.DVEN, 1, Local0) + Return (And (Local0, 1)) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c new file mode 100644 index 0000000..ea9fa54 --- /dev/null +++ b/src/northbridge/intel/haswell/pcie.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph siro@das-labor.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <assert.h> + +static void pcie_disable(struct device *dev) +{ + printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev)); + dev->enabled = 0; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static const char *pcie_acpi_name(const struct device *dev) +{ + assert(dev); + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + assert(dev->bus); + if (dev->bus->secondary == 0) + switch (dev->path.pci.devfn) { + case PCI_DEVFN(1, 0): + return "PEGP"; + case PCI_DEVFN(1, 1): + return "PEG1"; + case PCI_DEVFN(1, 2): + return "PEG2"; + }; + + struct device *const port = dev->bus->dev; + assert(port); + assert(port->bus); + + if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && + port->bus->secondary == 0 && + (port->path.pci.devfn == PCI_DEVFN(1, 0) || + port->path.pci.devfn == PCI_DEVFN(1, 1) || + port->path.pci.devfn == PCI_DEVFN(1, 2))) + return "DEV0"; + + return NULL; +} +#endif + +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .disable = pcie_disable, + .init = pci_dev_init, + .ops_pci = &pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = pcie_acpi_name, +#endif +}; + +static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, + 0 }; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1)) This looks nicer in new ASL syntax:
Local0 = _SB.PCI0.MCHC.DVEN >> 3 Return Local0 & 1
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1: Code-Review+1
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
This looks nicer in new ASL syntax: […]
Do you want me to resubmit this way? I honestly just cut and pasted the code from the sandybridge version. I can redo it and retest it if you'd like though. Assume that aside from the "3" it's the same code for all 3 instances of this? Thank you.
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1:
(1 comment)
Replied to comment
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Do you want me to resubmit this way? I honestly just cut and pasted the code from the sandybridge v […]
Does not appear that it likes this syntax; I tried and got the following error when building the dsdt: dsdt.asl 627: Return Local0 & 1 Error 6114 - ^ Result is not used, operator has no effect
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Does not appear that it likes this syntax; I tried and got the following error when building the dsd […]
Sry, "Return ((_SB.PCI0.MCHC.DVEN >> 3) & 1)" should work.
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1:
(1 comment)
updated comments
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Sry, "Return ((_SB.PCI0.MCHC.DVEN >> 3) & 1)" should work.
Just to be clear, that's replace: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) Return (And (Local0, 1)) with: Return ((_SB.PCI0.MCHC.DVEN >> 3) & 1) Correct?
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1:
(1 comment)
comments added
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Just to be clear, that's replace: […]
Confirmed that replacing both lines with just Return ((_SB.PCI0.MCHC.DVEN >> 3) & 0xf) works. Note the change to 0xf, I am testing this now to see if it makes dGPU work under Windows. If it does I'll post an updated commit with 0xf, and if not I'll post one as-is with just 1. This does work under Linux (Ubuntu 18.04.4 with 5.3.0-28 kernel, both Nouveau and Nvidia-Proprietary are able to render to this card, although Nouveau is noticeably slower than proprietary).
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Confirmed that replacing both lines with just Return ((_SB.PCI0.MCHC.DVEN >> 3) & 0xf) works. […]
Please test Return (((_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf)
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 1:
(1 comment)
Updated comments
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Please test Return (((_SB.PCI0.MCHC. […]
Confirmed working in Linux. Still want to test it in Windows, but I'll submit it upstream just the same.
Hello Patrick Rudolph, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38743
to look at the new patch set (#2).
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from sandybridge with vendor IDs updated to the correct haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-29 kernel. Without patches dmesg reports noveau is unable to read the ROM of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With patches drm appears to be initalized and dmesg only reports an error I assume is related to the Optimus setup of "DRM: Pointer to TMDS table invalid".
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan macromorgan@hotmail.com --- M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl A src/northbridge/intel/haswell/acpi/peg.asl A src/northbridge/intel/haswell/pcie.c 5 files changed, 153 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38743/2
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 2:
(1 comment)
Updated with new patchset.
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Confirmed working in Linux. […]
Updated with new patchset.
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@12 PS2, Line 12: Tested on t440p Just FYI - Patchset 1 and 2 have been tested successfully on Linux. Patchset 1 tested successfully on Linux (Ubuntu 18.04.4 with 5.3.0-28 kernel) and unsuccessfully on Windows 10 (Windows 10 x64 1909). In Windows the PCI 16x and 8x bridges are hidden and dGPU not available.
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 2:
(1 comment)
Confirmed patchset 2 still works on Linux, does not work on Windows 10.
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@12 PS2, Line 12: Tested on t440p
Just FYI - Patchset 1 and 2 have been tested successfully on Linux. […]
Confirmed that everything still renders correctly on Ubuntu with the current patchset. Windows now sees the GPU, however loading the driver causes it to bluescreen.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@11 PS2, Line 11: sandybridge Sandybridge
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@13 PS2, Line 13: noveau Nouveau
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@13 PS2, Line 13: Without patches dmesg reports noveau is : unable to read the ROM of the dGPU as it has an invalid checksum (I : checked that the ROM in CBFS is correct). Did you talk to the Nouveau folks? Sounds like something that can be fixed in Linux.
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@15 PS2, Line 15: drm DRM
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@16 PS2, Line 16: initalized initialized
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... PS2, Line 19: Name (_ADR, 0x00010000) Use tabs?
Hello Patrick Rudolph, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38743
to look at the new patch set (#3).
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the Haswell north bridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from Sandybridge with vendor IDs updated to the correct Haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-29 kernel. Without patches dmesg reports Nouveau is unable to read the ROM of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With patches DRM appears to be initialized and dmesg only reports an error I assume is related to the Optimus setup of "DRM: Pointer to TMDS table invalid".
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan macromorgan@hotmail.com --- M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl A src/northbridge/intel/haswell/acpi/peg.asl A src/northbridge/intel/haswell/pcie.c 5 files changed, 153 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38743/3
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 3:
(7 comments)
Updated comments.
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@11 PS2, Line 11: sandybridge
Sandybridge
Ack
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@12 PS2, Line 12: Tested on t440p
Confirmed that everything still renders correctly on Ubuntu with the current patchset. […]
Done
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@13 PS2, Line 13: noveau
Nouveau
Ack
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@13 PS2, Line 13: Without patches dmesg reports noveau is : unable to read the ROM of the dGPU as it has an invalid checksum (I : checked that the ROM in CBFS is correct).
Did you talk to the Nouveau folks? Sounds like something that can be fixed in Linux.
Negative. When I Googled the message it appeared to be related to the Optimus setup where the nVidia chip has no attached displays (in the muxless setup this is how it works apparently). I assume the message is benign. https://lkml.org/lkml/2019/6/2/59
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@15 PS2, Line 15: drm
DRM
Ack
https://review.coreboot.org/c/coreboot/+/38743/2//COMMIT_MSG@16 PS2, Line 16: initalized
initialized
Ack
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... PS2, Line 19: Name (_ADR, 0x00010000) I assume I already did? Sorry is my tab format incorrect? Still new to this.
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 3:
(1 comment)
resolved comment (I think, I thought I used tabs).
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... PS2, Line 19: Name (_ADR, 0x00010000)
Use tabs?
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... PS2, Line 19: Name (_ADR, 0x00010000)
I assume I already did? Sorry is my tab format incorrect? Still new to this.
Sorry, I hit a Gerrit bug (in Firefox 72.0.1), and it didn’t show it until after selecting that part with the mouse.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Updated with new patchset.
Still not correct. Correct is Return (((_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf) as it would return 0 or 0xf
Hello Patrick Rudolph, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38743
to look at the new patch set (#4).
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the Haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from Sandybridge with vendor IDs updated to the correct Haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is unable to read the ROM of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With patches DRM works correctly with both the Nouveau driver and the Nvidia proprietary driver. Windows 10 1909 also tested but generates bluescreen once GPU driver is loaded.
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan macromorgan@hotmail.com --- M Documentation/mainboard/lenovo/t440p.md M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl A src/northbridge/intel/haswell/acpi/peg.asl A src/northbridge/intel/haswell/pcie.c 6 files changed, 155 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38743/4
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 4:
(2 comments)
Replied to comments.
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... PS2, Line 19: Name (_ADR, 0x00010000)
Sorry, I hit a Gerrit bug (in Firefox 72.0. […]
Done
https://review.coreboot.org/c/coreboot/+/38743/2/src/northbridge/intel/haswe... PS2, Line 19: Name (_ADR, 0x00010000)
Done
Done
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 4:
(1 comment)
Replied to comments.
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/1/src/northbridge/intel/haswe... PS1, Line 23: ShiftRight (_SB.PCI0.MCHC.DVEN, 3, Local0) : Return (And (Local0, 1))
Still not correct. Correct is […]
Fixed with latest patchset.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
(11 comments)
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@11 PS5, Line 11: Sandybridge Sandy Bridge
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@14 PS5, Line 14: ROM VBIOS, rather
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@15 PS5, Line 15: With patches With what patches? Did you mean:
With this patch, DRM works ...
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@17 PS5, Line 17: Windows 10 1909 also tested but generates bluescreen once GPU : driver is loaded. You might want to dump the vendor DSDT. I think Nvidia Windows drivers heavily rely on ACPI table contents to do switchable graphics, so it's not a surprise that the driver just doesn't work without those.
https://review.coreboot.org/c/coreboot/+/38743/5/Documentation/mainboard/len... File Documentation/mainboard/lenovo/t440p.md:
https://review.coreboot.org/c/coreboot/+/38743/5/Documentation/mainboard/len... PS5, Line 61: - dGPU (must be enabled in CMOS options) Can't it be enabled by default? There's straps to detect its presence.
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 17: PEGP Haswell ACPI says that this should be PEG0
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 26: DEV0 This should be PEGP, and it is device 0 function 0 of the dGPU (or whatever)
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 29: } Haswell ACPI says that you are missing PEGA, right after PEGP:
Device (PEGA) { Name(_ADR, 0x00000001) }
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 42: PEGP When changing the ASL code, also change this
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 53: if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && : port->bus->secondary == 0 && : (port->path.pci.devfn == PCI_DEVFN(1, 0) || : port->path.pci.devfn == PCI_DEVFN(1, 1) || : port->path.pci.devfn == PCI_DEVFN(1, 2))) : return "DEV0"; And this would need to be changed. For example, PEG0 could be:
if (port->bus->secondary == 0) { switch (port->path.pci.devfn) { case PCI_DEVFN(1, 0): switch (dev->path.pci.devfn) { case PCI_DEVFN(0, 0): return "PEGP";
case PCI_DEVFN(0, 1): return "PEGA"; } break; } }
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 83: 0 }; This fits on the previous line
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 17: PEGP
Haswell ACPI says that this should be PEG0
What's "haswell ACPI"? The spec doesn't enforce names at all.
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 26: DEV0
This should be PEGP, and it is device 0 function 0 of the dGPU (or whatever)
No.
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 29: }
Haswell ACPI says that you are missing PEGA, right after PEGP: […]
This is sometimes used for the dGPU audio device. Out of scope.
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 53: if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && : port->bus->secondary == 0 && : (port->path.pci.devfn == PCI_DEVFN(1, 0) || : port->path.pci.devfn == PCI_DEVFN(1, 1) || : port->path.pci.devfn == PCI_DEVFN(1, 2))) : return "DEV0";
And this would need to be changed. For example, PEG0 could be: […]
That doesn't cover device 01.1 or 01.2.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 17: PEGP
What's "haswell ACPI"? The spec doesn't enforce names at all.
Reference code and the ACPI tables of my main laptop, which is Optimus-capable.
The spec might not enforce any names, but the Nvidia drivers might...
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 26: DEV0
No.
Yes. We can be like this all day if you want.
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 29: }
This is sometimes used for the dGPU audio device. Out of scope.
Would be nice to know if its lack is what makes the Windows drivers crash.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 53: if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && : port->bus->secondary == 0 && : (port->path.pci.devfn == PCI_DEVFN(1, 0) || : port->path.pci.devfn == PCI_DEVFN(1, 1) || : port->path.pci.devfn == PCI_DEVFN(1, 2))) : return "DEV0";
That doesn't cover device 01.1 or 01.2.
Yes. As I said, "PEG0 could be". In any case, it's the same thing for these two as well:
if (port->bus->secondary == 0) { switch (port->path.pci.devfn) { case PCI_DEVFN(1, 0): case PCI_DEVFN(1, 1): case PCI_DEVFN(1, 2): switch (dev->path.pci.devfn) { case PCI_DEVFN(0, 0): return "PEGP";
case PCI_DEVFN(0, 1): return "PEGA"; } break; } }
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 17: PEGP
Reference code and the ACPI tables of my main laptop, which is Optimus-capable. […]
Guessing doesn't help here. If you can't prove this can safely ignored. This patch doesn't add support for Nvidia Optimus BTW.
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 26: DEV0
Yes. We can be like this all day if you want.
Please stop this destructive behavior or you'll be reported. There's nothing wrong with this ACPI code, and there's no need to change anything. Please note: this is coreboot and not the firmware of your main laptop.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 17: PEGP
Guessing doesn't help here. If you can't prove this can safely ignored. […]
Whatever
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 26: DEV0
Please stop this destructive behavior or you'll be reported. […]
Whatever
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
Uhm, folks, why did such a simple naming issue escalate like this?
Some general statements about that:
- It's sometimes useful to do what other platforms with the same chipset do so drivers are happier.
- We can still change object names later once we see that it improves matters in some way.
- I understood Angel's remarks to be suggestions with some reasoning (even if badly phrased). Pointing out that you want to keep the names is okay. Explaining why is even better.
- That passive-aggressive "No." isn't helpful. Neither are "Yes" or "Whatever". As such, I'd be careful about assigning "destructive behavior" to any single participant in this exchange. Cut it down and let's go back to the code, okay?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
(4 comments)
Please fix the notes on the commit message. A follow-up can fix the remaining issues with the proprietary windows driver.
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@17 PS5, Line 17: Windows 10 1909 also tested but generates bluescreen once GPU : driver is loaded.
You might want to dump the vendor DSDT. […]
It's likely looking for ACPI mandatory functions like _DOD, _DSS, ... That should be fixed in a separate commit as it requires reverse engineering the Nvidia driver.
https://review.coreboot.org/c/coreboot/+/38743/5/Documentation/mainboard/len... File Documentation/mainboard/lenovo/t440p.md:
https://review.coreboot.org/c/coreboot/+/38743/5/Documentation/mainboard/len... PS5, Line 61: - dGPU (must be enabled in CMOS options)
Can't it be enabled by default? There's straps to detect its presence.
Usually it's disabled as it draws additional 5Watt in idle
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 42: PEGP
When changing the ASL code, also change this
Done
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 53: if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && : port->bus->secondary == 0 && : (port->path.pci.devfn == PCI_DEVFN(1, 0) || : port->path.pci.devfn == PCI_DEVFN(1, 1) || : port->path.pci.devfn == PCI_DEVFN(1, 2))) : return "DEV0";
Yes. As I said, "PEG0 could be". In any case, it's the same thing for these two as well: […]
Done
Hello Patrick Rudolph, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38743
to look at the new patch set (#6).
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the Haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated to the correct Haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is unable to read the VBIOS of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With this patch DRM works correctly with both the Nouveau driver and the Nvidia proprietary driver. Windows 10 1909 also tested but generates bluescreen once GPU driver is loaded.
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan macromorgan@hotmail.com --- M Documentation/mainboard/lenovo/t440p.md M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl A src/northbridge/intel/haswell/acpi/peg.asl A src/northbridge/intel/haswell/pcie.c 6 files changed, 154 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38743/6
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 6:
(5 comments)
Fixed issues.
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@11 PS5, Line 11: Sandybridge
Sandy Bridge
Fixed with patchset 6.
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@14 PS5, Line 14: ROM
VBIOS, rather
Fixed with patchset 6.
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@15 PS5, Line 15: With patches
With what patches? Did you mean: […]
Clarified on patchset 6.
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@17 PS5, Line 17: Windows 10 1909 also tested but generates bluescreen once GPU : driver is loaded.
It's likely looking for ACPI mandatory functions like _DOD, _DSS, ... […]
Here's a dump of both stock and corebooted (with this patch applied) DSDTs for this board, both with the dGPU enabled.
https://gist.github.com/macromorgan/640addff8577ec732efcb610ee0a00a6
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 83: 0 };
This fits on the previous line
Fixed in patchset 6.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the Haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated to the correct Haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is unable to read the VBIOS of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With this patch DRM works correctly with both the Nouveau driver and the Nvidia proprietary driver. Windows 10 1909 also tested but generates bluescreen once GPU driver is loaded.
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan macromorgan@hotmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M Documentation/mainboard/lenovo/t440p.md M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl A src/northbridge/intel/haswell/acpi/peg.asl A src/northbridge/intel/haswell/pcie.c 6 files changed, 154 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md index 98c1da5..fb01870 100644 --- a/Documentation/mainboard/lenovo/t440p.md +++ b/Documentation/mainboard/lenovo/t440p.md @@ -36,10 +36,7 @@ - Cannot get the mainboard serial number from the mainboard: the OEM UEFI firmware gets the serial number from an "emulated EEPROM" via I/O port 0x1630/0x1634, but it's still unknown how to make it work - -## Untested - -- the dGPU model +- The dGPU does not currently work in Windows.
## Working
@@ -61,6 +58,7 @@ - CMOS options: wlan, trackpoint, fn_ctrl_swap - internal flashing when IFD is unlocked - using `me_cleaner` +- dGPU (must be enabled in CMOS options)
[Lenovo ThinkPad T440p]: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-... [Hardware Maintenance Manual]: https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/t440p_hmm_en_sp4... diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b986336..73a20f2 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -19,6 +19,7 @@
ramstage-y += memmap.c ramstage-y += northbridge.c +ramstage-y += pcie.c ramstage-y += gma.c
ramstage-y += acpi.c diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 45ebff2..2db72d7 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -16,6 +16,7 @@
#include "../haswell.h" #include "hostbridge.asl" +#include "peg.asl" #include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 19d788c..d567701 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -36,7 +36,8 @@ MHEN, 1, // Enable , 13, // MHBR, 22, // MCHBAR - + Offset (0x54), + DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl new file mode 100644 index 0000000..c4af375 --- /dev/null +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph siro@das-labor.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + Method (_STA) + { + Return (((_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG1) +{ + Name (_ADR, 0x00010001) + + Method (_STA) + { + Return (((_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG2) +{ + Name (_ADR, 0x00010002) + + Method (_STA) + { + Return (((_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c new file mode 100644 index 0000000..b3a21bf --- /dev/null +++ b/src/northbridge/intel/haswell/pcie.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph siro@das-labor.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <assert.h> + +static void pcie_disable(struct device *dev) +{ + printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev)); + dev->enabled = 0; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static const char *pcie_acpi_name(const struct device *dev) +{ + assert(dev); + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + assert(dev->bus); + if (dev->bus->secondary == 0) + switch (dev->path.pci.devfn) { + case PCI_DEVFN(1, 0): + return "PEGP"; + case PCI_DEVFN(1, 1): + return "PEG1"; + case PCI_DEVFN(1, 2): + return "PEG2"; + }; + + struct device *const port = dev->bus->dev; + assert(port); + assert(port->bus); + + if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && + port->bus->secondary == 0 && + (port->path.pci.devfn == PCI_DEVFN(1, 0) || + port->path.pci.devfn == PCI_DEVFN(1, 1) || + port->path.pci.devfn == PCI_DEVFN(1, 2))) + return "DEV0"; + + return NULL; +} +#endif + +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .disable = pcie_disable, + .init = pci_dev_init, + .ops_pci = &pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = pcie_acpi_name, +#endif +}; + +static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, 0 }; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Name of user not set (Code Review)
-
Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)