Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38743 )
Change subject: nb/intel/haswell/peg: Add PEG driver stub ......................................................................
Patch Set 5:
(11 comments)
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@11 PS5, Line 11: Sandybridge Sandy Bridge
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@14 PS5, Line 14: ROM VBIOS, rather
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@15 PS5, Line 15: With patches With what patches? Did you mean:
With this patch, DRM works ...
https://review.coreboot.org/c/coreboot/+/38743/5//COMMIT_MSG@17 PS5, Line 17: Windows 10 1909 also tested but generates bluescreen once GPU : driver is loaded. You might want to dump the vendor DSDT. I think Nvidia Windows drivers heavily rely on ACPI table contents to do switchable graphics, so it's not a surprise that the driver just doesn't work without those.
https://review.coreboot.org/c/coreboot/+/38743/5/Documentation/mainboard/len... File Documentation/mainboard/lenovo/t440p.md:
https://review.coreboot.org/c/coreboot/+/38743/5/Documentation/mainboard/len... PS5, Line 61: - dGPU (must be enabled in CMOS options) Can't it be enabled by default? There's straps to detect its presence.
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 17: PEGP Haswell ACPI says that this should be PEG0
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 26: DEV0 This should be PEGP, and it is device 0 function 0 of the dGPU (or whatever)
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 29: } Haswell ACPI says that you are missing PEGA, right after PEGP:
Device (PEGA) { Name(_ADR, 0x00000001) }
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 42: PEGP When changing the ASL code, also change this
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 53: if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && : port->bus->secondary == 0 && : (port->path.pci.devfn == PCI_DEVFN(1, 0) || : port->path.pci.devfn == PCI_DEVFN(1, 1) || : port->path.pci.devfn == PCI_DEVFN(1, 2))) : return "DEV0"; And this would need to be changed. For example, PEG0 could be:
if (port->bus->secondary == 0) { switch (port->path.pci.devfn) { case PCI_DEVFN(1, 0): switch (dev->path.pci.devfn) { case PCI_DEVFN(0, 0): return "PEGP";
case PCI_DEVFN(0, 1): return "PEGA"; } break; } }
https://review.coreboot.org/c/coreboot/+/38743/5/src/northbridge/intel/haswe... PS5, Line 83: 0 }; This fits on the previous line