Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Added GBYT4 port
Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/unk/Kconfig A src/mainboard/unk/Kconfig.name A src/mainboard/unk/gbyt4/Kconfig A src/mainboard/unk/gbyt4/Kconfig.name A src/mainboard/unk/gbyt4/Makefile.inc A src/mainboard/unk/gbyt4/acpi/dptf.asl A src/mainboard/unk/gbyt4/acpi/ec.asl A src/mainboard/unk/gbyt4/acpi/mainboard.asl A src/mainboard/unk/gbyt4/acpi/superio.asl A src/mainboard/unk/gbyt4/acpi_tables.c A src/mainboard/unk/gbyt4/board_info.txt A src/mainboard/unk/gbyt4/cmos.layout A src/mainboard/unk/gbyt4/devicetree.cb A src/mainboard/unk/gbyt4/dsdt.asl A src/mainboard/unk/gbyt4/early_init.c A src/mainboard/unk/gbyt4/gpio.c A src/mainboard/unk/gbyt4/irqroute.c A src/mainboard/unk/gbyt4/irqroute.h A src/mainboard/unk/gbyt4/mainboard.c A src/mainboard/unk/gbyt4/romstage.c 20 files changed, 792 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/1
diff --git a/src/mainboard/unk/Kconfig b/src/mainboard/unk/Kconfig new file mode 100644 index 0000000..86fe2d6 --- /dev/null +++ b/src/mainboard/unk/Kconfig @@ -0,0 +1,19 @@ +if VENDOR_UNK + +choice + prompt "Mainboard model" + +source "src/mainboard/unk/*/Kconfig.name" + +endchoice + +source "src/mainboard/unk/*/Kconfig" + +config MAINBOARD_VENDOR + default "Unknown" + +config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + +endif # VENDOR_UNK diff --git a/src/mainboard/unk/Kconfig.name b/src/mainboard/unk/Kconfig.name new file mode 100644 index 0000000..a5f8bf4 --- /dev/null +++ b/src/mainboard/unk/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_UNK + bool "Unknown" diff --git a/src/mainboard/unk/gbyt4/Kconfig b/src/mainboard/unk/gbyt4/Kconfig new file mode 100644 index 0000000..b57f977 --- /dev/null +++ b/src/mainboard/unk/gbyt4/Kconfig @@ -0,0 +1,24 @@ +if BOARD_UNK_GBYT4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "unk/gbyt4" + +config MAINBOARD_PART_NUMBER + string + default "GBYT4" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "UNKNOWN" + +endif # BOARD_KM_GBYT4 diff --git a/src/mainboard/unk/gbyt4/Kconfig.name b/src/mainboard/unk/gbyt4/Kconfig.name new file mode 100644 index 0000000..29c4e9d --- /dev/null +++ b/src/mainboard/unk/gbyt4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_UNK_GBYT4 + bool "GBYT4" diff --git a/src/mainboard/unk/gbyt4/Makefile.inc b/src/mainboard/unk/gbyt4/Makefile.inc new file mode 100644 index 0000000..2bde1bd --- /dev/null +++ b/src/mainboard/unk/gbyt4/Makefile.inc @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += irqroute.c gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + +# Temporary shit to test MRC +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd diff --git a/src/mainboard/unk/gbyt4/acpi/dptf.asl b/src/mainboard/unk/gbyt4/acpi/dptf.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/dptf.asl diff --git a/src/mainboard/unk/gbyt4/acpi/ec.asl b/src/mainboard/unk/gbyt4/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/ec.asl diff --git a/src/mainboard/unk/gbyt4/acpi/mainboard.asl b/src/mainboard/unk/gbyt4/acpi/mainboard.asl new file mode 100644 index 0000000..f343574 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Level, ActiveHigh, Exclusive, PullNone,, + "\_SB.GPSC") { 14 } + + /* Mic Detect (index 1) */ + GpioInt (Level, ActiveHigh, Exclusive, PullNone,, + "\_SB.GPSC") { 15 } + }) +} diff --git a/src/mainboard/unk/gbyt4/acpi/superio.asl b/src/mainboard/unk/gbyt4/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/superio.asl diff --git a/src/mainboard/unk/gbyt4/acpi_tables.c b/src/mainboard/unk/gbyt4/acpi_tables.c new file mode 100644 index 0000000..41ec5f9 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi_tables.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include <soc/iomap.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 0; + + /* Enable DPTF */ + gnvs->dpte = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/unk/gbyt4/board_info.txt b/src/mainboard/unk/gbyt4/board_info.txt new file mode 100644 index 0000000..5152b2a --- /dev/null +++ b/src/mainboard/unk/gbyt4/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Unknown +Board name: GBYT4 +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/unk/gbyt4/cmos.layout b/src/mainboard/unk/gbyt4/cmos.layout new file mode 100644 index 0000000..da1b185 --- /dev/null +++ b/src/mainboard/unk/gbyt4/cmos.layout @@ -0,0 +1,89 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/unk/gbyt4/devicetree.cb b/src/mainboard/unk/gbyt4/devicetree.cb new file mode 100644 index 0000000..d442127 --- /dev/null +++ b/src/mainboard/unk/gbyt4/devicetree.cb @@ -0,0 +1,94 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Do not route USB ports to XHCI + register "usb_route_to_xhci" = "0" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 10.0 off end # MMC + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 off end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC45 + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 off end # HDA + device pci 1c.0 on end # PCI-e #1 (LAN1) + device pci 1c.1 on end # PCI-e #2 (LAN2) + device pci 1c.2 on end # PCI-e #3 (LAN3) + device pci 1c.3 on end # PCI-e #4 (LAN4) + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + + device pci 1f.0 on # LPC + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + irq 0x70 = 9 + io 0x62 = 0x0a20 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/unk/gbyt4/dsdt.asl b/src/mainboard/unk/gbyt4/dsdt.asl new file mode 100644 index 0000000..fb037b1 --- /dev/null +++ b/src/mainboard/unk/gbyt4/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ENABLE_TPM + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/baytrail/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/unk/gbyt4/early_init.c b/src/mainboard/unk/gbyt4/early_init.c new file mode 100644 index 0000000..89da435 --- /dev/null +++ b/src/mainboard/unk/gbyt4/early_init.c @@ -0,0 +1,11 @@ +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, 0x01) + +void bootblock_mainboard_early_init(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/unk/gbyt4/gpio.c b/src/mainboard/unk/gbyt4/gpio.c new file mode 100644 index 0000000..b5e68c1 --- /dev/null +++ b/src/mainboard/unk/gbyt4/gpio.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <mainboard/unk/gbyt4/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/unk/gbyt4/irqroute.c b/src/mainboard/unk/gbyt4/irqroute.c new file mode 100644 index 0000000..6fa0366 --- /dev/null +++ b/src/mainboard/unk/gbyt4/irqroute.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/unk/gbyt4/irqroute.h b/src/mainboard/unk/gbyt4/irqroute.h new file mode 100644 index 0000000..7dd9ad2 --- /dev/null +++ b/src/mainboard/unk/gbyt4/irqroute.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) diff --git a/src/mainboard/unk/gbyt4/mainboard.c b/src/mainboard/unk/gbyt4/mainboard.c new file mode 100644 index 0000000..b6ccc7f --- /dev/null +++ b/src/mainboard/unk/gbyt4/mainboard.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG(VGA_ROM_RUN) +#include <x86emu/x86emu.h> +#endif +#include <acpi/acpi.h> +#include <arch/interrupt.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <bootstate.h> + +void mainboard_suspend_resume(void) +{ +} + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video BIOS default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +static void mainboard_init(struct device *dev) +{ + +} + +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + return 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/unk/gbyt4/romstage.c b/src/mainboard/unk/gbyt4/romstage.c new file mode 100644 index 0000000..3ca7f77 --- /dev/null +++ b/src/mainboard/unk/gbyt4/romstage.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/mrc_wrapper.h> +#include <soc/romstage.h> + +//static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +//{ +// int ram_id = 0; +// +// /* The ram_id[2:0] pullups are too large for the default 20K +// * pulldown on the pad. Therefore, disable the internal pull resistor to +// * read high values correctly. */ +// ssus_disable_internal_pull(GPIO_SSUS_37_PAD); +// ssus_disable_internal_pull(GPIO_SSUS_38_PAD); +// ssus_disable_internal_pull(GPIO_SSUS_39_PAD); +//#ifdef GPIO_SSUS_40_PAD_USE_PULLDOWN +// /* To prevent floating pin on shipped systems. */ +// ssus_enable_internal_pull(GPIO_SSUS_40_PAD, PAD_PULL_DOWN | PAD_PU_20K); +//#elif defined(GPIO_SSUS_40_PAD) +// ssus_disable_internal_pull(GPIO_SSUS_40_PAD); +//#endif +// ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); +// ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); +// ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); +//#ifdef GPIO_SSUS_40_PAD +// ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3); +//#endif +// printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); +// +// if (ram_id >= total_spds) +// return NULL; +// +// /* Single channel configs */ +// if (dual_channel_config & (1 << ram_id)) +// *dual = 1; +// +// return &spd_file_content[SPD_SIZE * ram_id]; +//} + +void mainboard_fill_mrc_params(struct mrc_params *mp) +{ + /*void *spd_content;*/ + int dual_channel = 0; + void *spd_file; + size_t spd_fsize; + + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_fsize); + if (!spd_file) + die("SPD data not found."); + + /*spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, + &dual_channel);*/ + + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; + mp->mainboard.dram_is_slotted = 1; + + mp->mainboard.dram_data[0] = spd_file; + if (dual_channel) + mp->mainboard.dram_data[1] = spd_file; +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/gpi... File src/mainboard/unk/gbyt4/gpio.c:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/gpi... PS1, Line 208: struct soc_gpio_config* mainboard_get_gpios(void) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/irq... File src/mainboard/unk/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/irq... PS1, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/irq... PS1, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/rom... File src/mainboard/unk/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/rom... PS1, Line 56: &dual_channel);*/ code indent should use tabs where possible
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 1:
(15 comments)
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/Kconfig File src/mainboard/unk/Kconfig:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/Kconfig@1 PS1, Line 1: UNK I'd use "unknown" in symbol and folder names, it's clearer
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/acp... File src/mainboard/unk/gbyt4/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/acp... PS1, Line 3: Scope (_SB.PCI0.LPEA) This is for LPE audio, if the board doesn't have any audio support, then I'd drop it
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... File src/mainboard/unk/gbyt4/cmos.layout:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... PS1, Line 12: #96 4 r 0 status_c_rsvd You can drop all commented-out entries. They can only bitrot 😄
The most offensive ones are the "unused" and the last one that says "amd_reserved"
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... PS1, Line 55: # SandyBridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3 Not Sandy Bridge
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... File src/mainboard/unk/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 12: 0x1 0x3 is the mask for 2 ports
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 69: off on
It's the SPI controller where the flash chip sits, AFAIK
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 86: space
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... File src/mainboard/unk/gbyt4/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 22: Scope (_SB) { : Device (PCI0) : { Ugh, that inconsistent brace placement... After removing unneeded lines, you can have a single set of braces:
Device (_SB.PCI0) { #include <soc/intel/baytrail/acpi/southcluster.asl> }
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 25: //#include <soc/intel/baytrail/acpi/northcluster.asl> You can drop this commented-out include
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 27: #include <drivers/intel/gma/acpi/default_brightness_levels.asl> If your board doesn't have an integrated LCD, this can be removed
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 31: #include "acpi/dptf.asl" Since DPTF is not enabled, you can drop this and remove the file
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 35: #include "acpi/mainboard.asl" If this file is empty, you can remove this line
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/ear... File src/mainboard/unk/gbyt4/early_init.c:
PS1: I am not sure if this code is being called... To be sure, you can move this to romstage.c, more or less like I did on the Asrock Q1900M:
https://review.coreboot.org/c/coreboot/+/39658/4/src/mainboard/asrock/q1900m...
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/gpi... File src/mainboard/unk/gbyt4/gpio.c:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/gpi... PS1, Line 208: struct soc_gpio_config* mainboard_get_gpios(void)
"foo* bar" should be "foo *bar"
Would be good to fix
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/rom... File src/mainboard/unk/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/rom... PS1, Line 9: //static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) You know you can comment things using preprocessor, right? 😄
#if 0 /* Tons of spaghetti code */ #endif
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... File src/mainboard/unk/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 12: 0x1
0x3 is the mask for 2 ports
I see there's only one SATA port, but I'm fairly sure the mPCIe slot is actually mSATA (Bay Trail only has four PCIe lanes, and if there are four NICs using them all...)
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/acp... File src/mainboard/unk/gbyt4/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/acp... PS1, Line 3: Scope (_SB.PCI0.LPEA)
This is for LPE audio, if the board doesn't have any audio support, then I'd drop it
I can delete the GpioInt lines but the ResourceTemplate needs to remain otherwise it doesn't build.
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... File src/mainboard/unk/gbyt4/cmos.layout:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... PS1, Line 12: #96 4 r 0 status_c_rsvd
You can drop all commented-out entries. They can only bitrot 😄 […]
I will drop them. And they also should be dropped from google/rambi and many other boards with the exact same file copy pasted.
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... PS1, Line 55: # SandyBridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3
Not Sandy Bridge
Should it be renamed to BayTrail or dropped entirely?
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... File src/mainboard/unk/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 12: 0x1
I see there's only one SATA port, but I'm fairly sure the mPCIe slot is actually mSATA (Bay Trail on […]
I will change it to 3, just the comment i copied along with the base device tree from rambi (incorrectly) suggested that it meant two.
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 69: off
on […]
From the data sheet it looks like it's a different SPI controller not the same as the flashchip is on (e.g. SIO SPI vs PCU SPI).
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43087/2/src/mainboard/unk/gbyt4/gpi... File src/mainboard/unk/gbyt4/gpio.c:
https://review.coreboot.org/c/coreboot/+/43087/2/src/mainboard/unk/gbyt4/gpi... PS2, Line 208: struct soc_gpio_config* mainboard_get_gpios(void) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/43087/2/src/mainboard/unk/gbyt4/irq... File src/mainboard/unk/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/2/src/mainboard/unk/gbyt4/irq... PS2, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/2/src/mainboard/unk/gbyt4/irq... PS2, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/2/src/mainboard/unk/gbyt4/rom... File src/mainboard/unk/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/2/src/mainboard/unk/gbyt4/rom... PS2, Line 56: &dual_channel);*/ code indent should use tabs where possible
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#3).
Change subject: Added GBYT4 port ......................................................................
Added GBYT4 port
Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 18 files changed, 687 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... PS3, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... PS3, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... PS3, Line 21: I have to move this back to early_init.c, the board doesnt boot and there is no output otherwise.
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... PS3, Line 21:
I have to move this back to early_init.c, the board doesnt boot and there is no output otherwise.
More correctly it does boot if it's here, but there is serial output only after romstage, and it takes 5-10 minutes just to reach romstage.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#4).
Change subject: Added GBYT4 port ......................................................................
Added GBYT4 port
Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 693 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/4/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/4/src/mainboard/bostentech/gb... PS4, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/4/src/mainboard/bostentech/gb... PS4, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#5).
Change subject: Added GBYT4 port ......................................................................
Added GBYT4 port
Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 684 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 5: Code-Review+1
(48 comments)
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/gpio.c:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/bostentech/gb... PS1, Line 208: Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/gpio.c:
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 7: GPIO_FUNC(2, PULL_UP, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_UP, 20K), I'd say these shouldn't be pulling anything
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 10: GPIO_FUNC(0, PULL_DISABLE, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K), Uh, function 0 is reserved? No idea
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 19: GPIO_FUNC(1, PULL_DOWN, 20K), I'd try removing the pull
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 24: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), I'd say these don't need pull down
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 40: GPIO_FUNC(2, PULL_DOWN, 20K), I'd say this doesn't need a pull
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 41: GPIO_FUNC(1, PULL_UP, 20K), SATA LED, does it work as intended with this pull?
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 41: : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), These are PCIe clock request pins. I'd drop the pull and see if the Ethernet NICs still work.
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 46: GPIO_FUNC(0, PULL_UP, 20K), SD-related, probably NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 47: GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), HDA-related, if there's no audio on your board then this should be NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 55: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), MMC-related, unused?
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 66: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), SD2, unused
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 72: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), SD3, unused
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 81: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), LPC pins, use GPIO_FUNC1
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 86: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), More LPC clock stuff, they can also use GPIO_FUNC1
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 89: GPIO_FUNC(1, PULL_UP, 20K), SERIRQ, probably doesn't need pullups
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 90: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), SMBus, should be GPIO_FUNC1
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 93: GPIO_FUNC(1, PULL_DOWN, 20K) Speaker
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 94: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), Strap pins, probably unused
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 96: GPIO_FUNC(1, PULL_UP, 20K), Integrated UART TXD, likely NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 97: GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), Probably NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 100: GPIO_FUNC(1, PULL_DOWN, 20K), Integrated UART RXD, probably NC as well
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 101: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), I2S, pretty sure it's NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 105: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), SPI controller for dedicated hardware, not for the SPI flash so NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 109: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), UART1, most likely not connected
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 113: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), UART2, most likely NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 117: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), I2C ports for touchpad/touchscreen, most likely NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 117: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(2, PULL_UP, 20K), : GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(0, PULL_UP, 20K), I2C ports, unused
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 133: GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K), PWM pins, probably unused because they are wired as GPIOs
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 135: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), Platform clocks, most likely NC.
Out of curiosity, I checked my Q1900M: it can either use these pins or a regular crystal, and it's using the latter.
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 147: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), This looks wrong, function 1 is reserved for these two
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 146: GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), I'd say these are all NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 151: GPIO_FUNC(1, PULL_DOWN, 20K), GPIO_FUNC1 (PMC_SUSCLK1)
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 152: GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), Most likely NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 154: GPIO_FUNC(0, PULL_DISABLE, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K), NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 156: GPIO_FUNC(0, PULL_UP, 20K), Probably NC
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 157: GPIO_FUNC(0, PULL_DOWN, 20K), GPIO_FUNC0 (SUSPWRDNACK)
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 158: GPIO_FUNC(0, PULL_DOWN, 20K), GPIO_FUNC0 (SUSCLK)
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 159: GPIO_FUNC(0, PULL_DOWN, 20K), NC, probably?
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 160: GPIO_FUNC(2, PULL_DISABLE, 20K), GPIO_FUNC2 (USB_ULPI_RST#)
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 161: GPIO_FUNC(0, PULL_UP, 20K), GPIO_FUNC0 (PMC_WAKE_PCIE[0])
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 162: GPIO_FUNC(0, PULL_UP, 20K), This is the power button that needs the pullup, right?
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 163: GPIO_FUNC(1, PULL_UP, 20K), NC, most likely
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 164: GPIO_FUNC(0, PULL_DOWN, 20K), GPIO_FUNC0 (PMC_SUS_STAT#)
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 165: GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(0, PULL_UP, 20K), GPIO_FUNC0 (USB_OC0 and USB_OC1)
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 167: GPIO_FUNC(1, PULL_UP, 20K), NC?
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 168: GPIO_FUNC(0, PULL_DISABLE, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(2, PULL_UP, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K), XDP stuff, most likely NC?
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 177: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DISABLE, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), This is most likely NC as well, it's USB ULPI and would only be used in tablets, if at all...
http://web.archive.org/web/20131212023536/http://www.ulpi.org/
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/6/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/6/src/mainboard/bostentech/gb... PS6, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/6/src/mainboard/bostentech/gb... PS6, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/7/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/7/src/mainboard/bostentech/gb... PS7, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/7/src/mainboard/bostentech/gb... PS7, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/8/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/8/src/mainboard/bostentech/gb... PS8, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/8/src/mainboard/bostentech/gb... PS8, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/10/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/10/src/mainboard/bostentech/g... PS10, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/10/src/mainboard/bostentech/g... PS10, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/11/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/11/src/mainboard/bostentech/g... PS11, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/11/src/mainboard/bostentech/g... PS11, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#12).
Change subject: Added GBYT4 port ......................................................................
Added GBYT4 port
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 684 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/12
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/12/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/12/src/mainboard/bostentech/g... PS12, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/12/src/mainboard/bostentech/g... PS12, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#13).
Change subject: Added GBYT4 port ......................................................................
Added GBYT4 port
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 686 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/13
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/13/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/13/src/mainboard/bostentech/g... PS13, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/13/src/mainboard/bostentech/g... PS13, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: Added GBYT4 port ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/13//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43087/13//COMMIT_MSG@7 PS13, Line 7: Added GBYT4 port Please add a prefix, and use present tense imperative mood:
mb/bostentech: Add GBYT4 port
https://review.coreboot.org/c/coreboot/+/43087/13//COMMIT_MSG@8 PS13, Line 8: As there is no documentation, it would be great, if you added more information about what you tested (hardware ports, payloads, OS, … with versions).
Please also mention, what board you based your port on – if you did.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#14).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an ITE8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch #43133) - Booting from SATA works with GRUB2, SATA works in Linux - AHCI timeouts in SeaBIOS, SATA drives not recognized (believed to be a SeaBIOS bug) - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 686 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/14
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 14:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/13//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43087/13//COMMIT_MSG@7 PS13, Line 7: Added GBYT4 port
Please add a prefix, and use present tense imperative mood: […]
Done
https://review.coreboot.org/c/coreboot/+/43087/13//COMMIT_MSG@8 PS13, Line 8:
As there is no documentation, it would be great, if you added more information about what you tested […]
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#15).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an ITE8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch #43133) - Booting from SATA works with GRUB2, SATA works in Linux - AHCI timeouts in SeaBIOS, SATA drives not recognized (believed to be a SeaBIOS bug) - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 686 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/15
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 15:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/15/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/15/src/mainboard/bostentech/g... PS15, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/15/src/mainboard/bostentech/g... PS15, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#16).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an ITE8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch #43133) - Booting from SATA works with GRUB2, SATA works in Linux - AHCI timeouts in SeaBIOS, SATA drives not recognized (believed to be a SeaBIOS bug) - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 686 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/16
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 16:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/16/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/16/src/mainboard/bostentech/g... PS16, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/16/src/mainboard/bostentech/g... PS16, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 17:
(10 comments)
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/Kconfig File src/mainboard/unk/Kconfig:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/Kconfig@1 PS1, Line 1: UNK
I'd use "unknown" in symbol and folder names, it's clearer
Proper vendor name was added instead.
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/acp... File src/mainboard/unk/gbyt4/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/acp... PS1, Line 3: Scope (_SB.PCI0.LPEA)
I can delete the GpioInt lines but the ResourceTemplate needs to remain otherwise it doesn't build.
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... File src/mainboard/unk/gbyt4/cmos.layout:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... PS1, Line 12: #96 4 r 0 status_c_rsvd
I will drop them. […]
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... File src/mainboard/unk/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 12: 0x1
I will change it to 3, just the comment i copied along with the base device tree from rambi (incorre […]
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... File src/mainboard/unk/gbyt4/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 22: Scope (_SB) { : Device (PCI0) : {
Ugh, that inconsistent brace placement... […]
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 25: //#include <soc/intel/baytrail/acpi/northcluster.asl>
You can drop this commented-out include
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 27: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
If your board doesn't have an integrated LCD, this can be removed
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 31: #include "acpi/dptf.asl"
Since DPTF is not enabled, you can drop this and remove the file
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dsd... PS1, Line 35: #include "acpi/mainboard.asl"
If this file is empty, you can remove this line
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/ear... File src/mainboard/unk/gbyt4/early_init.c:
PS1:
I am not sure if this code is being called... To be sure, you can move this to romstage. […]
Serial only works properly in bootblock, if it's called here.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/17/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/17/src/mainboard/bostentech/g... PS17, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/17/src/mainboard/bostentech/g... PS17, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 18:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... PS18, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... PS18, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 18:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... PS18, Line 78: io 0x60 = 0x0a30 just wondering: does accessing these ranges work? I'm not so familiar with how baytrail sets up LPC IO decode ranges.
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... PS18, Line 123: #if CONFIG(VGA_ROM_RUN) if you use regular C code instead of preprocessor, it will still get build-tested even if CONFIG_VGA_ROM_RUN is not set even though the linker will optimize things so it does not end up in the final binary.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#20).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an ITE8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch #43133) - Booting from SATA works with GRUB2, SATA works in Linux - AHCI timeouts in SeaBIOS, SATA drives not recognized (believed to be a SeaBIOS bug) - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 686 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/20
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... PS18, Line 123: #if CONFIG(VGA_ROM_RUN)
if you use regular C code instead of preprocessor, it will still get build-tested even if CONFIG_VGA […]
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 20:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/20/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/20/src/mainboard/bostentech/g... PS20, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/20/src/mainboard/bostentech/g... PS20, Line 15: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#23).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an ITE8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch #43133) - Booting from SATA works with GRUB2, SATA works in Linux - AHCI timeouts in SeaBIOS, SATA drives not recognized (believed to be a SeaBIOS bug) - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 685 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/23
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 23:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/23/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/23/src/mainboard/bostentech/g... PS23, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/23/src/mainboard/bostentech/g... PS23, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 24:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/24/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/24/src/mainboard/bostentech/g... PS24, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/24/src/mainboard/bostentech/g... PS24, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#25).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an ITE8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch #43133) - Booting from SATA works with GRUB2, SATA works in Linux - AHCI timeouts in SeaBIOS, SATA drives not recognized (believed to be a SeaBIOS bug) - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 685 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/25
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 25:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/25/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/25/src/mainboard/bostentech/g... PS25, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/25/src/mainboard/bostentech/g... PS25, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 25:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43087/25/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/43087/25/src/mainboard/bostentech/g... PS25, Line 123: #if CONFIG(VGA_ROM_RUN) I am not sure how to handle the x86emu stuff above without using the preprocessor.
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... File src/mainboard/unk/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 86:
space
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/gpi... File src/mainboard/unk/gbyt4/gpio.c:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/gpi... PS1, Line 208: struct soc_gpio_config* mainboard_get_gpios(void)
Would be good to fix
Done
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 26:
(50 comments)
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... PS18, Line 78: io 0x60 = 0x0a30
just wondering: does accessing these ranges work? I'm not so familiar with how baytrail sets up LPC […]
I could just remove it, the environment controller is not actually needed in the devices built around this board, but it has a fan header on the board.
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/gpio.c:
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 7: GPIO_FUNC(2, PULL_UP, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_UP, 20K),
I'd say these shouldn't be pulling anything
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 19: GPIO_FUNC(1, PULL_DOWN, 20K),
I'd try removing the pull
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 24: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K),
I'd say these don't need pull down
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 40: GPIO_FUNC(2, PULL_DOWN, 20K),
I'd say this doesn't need a pull
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 41: GPIO_FUNC(1, PULL_UP, 20K),
SATA LED, does it work as intended with this pull?
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 41: : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
These are PCIe clock request pins. I'd drop the pull and see if the Ethernet NICs still work.
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 46: GPIO_FUNC(0, PULL_UP, 20K),
SD-related, probably NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 47: GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K), : GPIO_FUNC(2, PULL_DOWN, 20K),
HDA-related, if there's no audio on your board then this should be NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 55: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K),
MMC-related, unused?
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 66: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
SD2, unused
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 72: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
SD3, unused
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 81: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
LPC pins, use GPIO_FUNC1
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 86: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
More LPC clock stuff, they can also use GPIO_FUNC1
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 89: GPIO_FUNC(1, PULL_UP, 20K),
SERIRQ, probably doesn't need pullups
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 90: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
SMBus, should be GPIO_FUNC1
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 93: GPIO_FUNC(1, PULL_DOWN, 20K)
Speaker
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 94: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K),
Strap pins, probably unused
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 96: GPIO_FUNC(1, PULL_UP, 20K),
Integrated UART TXD, likely NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 97: GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K),
Probably NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 100: GPIO_FUNC(1, PULL_DOWN, 20K),
Integrated UART RXD, probably NC as well
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 101: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K),
I2S, pretty sure it's NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 105: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K),
SPI controller for dedicated hardware, not for the SPI flash so NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 109: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
UART1, most likely not connected
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 113: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
UART2, most likely NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 117: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
I2C ports for touchpad/touchscreen, most likely NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 117: GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(2, PULL_UP, 20K), : GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(0, PULL_UP, 20K),
I2C ports, unused
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 133: GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K),
PWM pins, probably unused because they are wired as GPIOs
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 135: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K),
Platform clocks, most likely NC. […]
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 147: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K),
This looks wrong, function 1 is reserved for these two
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 146: GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K),
I'd say these are all NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 151: GPIO_FUNC(1, PULL_DOWN, 20K),
GPIO_FUNC1 (PMC_SUSCLK1)
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 152: GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K),
Most likely NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 154: GPIO_FUNC(0, PULL_DISABLE, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K),
NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 156: GPIO_FUNC(0, PULL_UP, 20K),
Probably NC
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 157: GPIO_FUNC(0, PULL_DOWN, 20K),
GPIO_FUNC0 (SUSPWRDNACK)
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 158: GPIO_FUNC(0, PULL_DOWN, 20K),
GPIO_FUNC0 (SUSCLK)
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 159: GPIO_FUNC(0, PULL_DOWN, 20K),
NC, probably?
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 160: GPIO_FUNC(2, PULL_DISABLE, 20K),
GPIO_FUNC2 (USB_ULPI_RST#)
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 161: GPIO_FUNC(0, PULL_UP, 20K),
GPIO_FUNC0 (PMC_WAKE_PCIE[0])
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 163: GPIO_FUNC(1, PULL_UP, 20K),
NC, most likely
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 164: GPIO_FUNC(0, PULL_DOWN, 20K),
GPIO_FUNC0 (PMC_SUS_STAT#)
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 165: GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(0, PULL_UP, 20K),
GPIO_FUNC0 (USB_OC0 and USB_OC1)
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 167: GPIO_FUNC(1, PULL_UP, 20K),
NC?
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 168: GPIO_FUNC(0, PULL_DISABLE, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_DOWN, 20K), : GPIO_FUNC(0, PULL_UP, 20K), : GPIO_FUNC(2, PULL_UP, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K), : GPIO_FUNC(0, PULL_DISABLE, 20K),
XDP stuff, most likely NC?
Done
https://review.coreboot.org/c/coreboot/+/43087/5/src/mainboard/bostentech/gb... PS5, Line 177: GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_DISABLE, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K), : GPIO_FUNC(1, PULL_UP, 20K), : GPIO_FUNC(1, PULL_DOWN, 20K),
This is most likely NC as well, it's USB ULPI and would only be used in tablets, if at all... […]
Done
https://review.coreboot.org/c/coreboot/+/43087/25/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/43087/25/src/mainboard/bostentech/g... PS25, Line 123: #if CONFIG(VGA_ROM_RUN)
I am not sure how to handle the x86emu stuff above without using the preprocessor.
Done
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/3/src/mainboard/bostentech/gb... PS3, Line 21:
More correctly it does boot if it's here, but there is serial output only after romstage, and it tak […]
Done
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... File src/mainboard/unk/gbyt4/cmos.layout:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/cmo... PS1, Line 55: # SandyBridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3
Should it be renamed to BayTrail or dropped entirely?
Done (dropped entries)
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... File src/mainboard/unk/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/1/src/mainboard/unk/gbyt4/dev... PS1, Line 69: off
From the data sheet it looks like it's a different SPI controller not the same as the flashchip is o […]
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 26:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/26/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/26/src/mainboard/bostentech/g... PS26, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/26/src/mainboard/bostentech/g... PS26, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... PS18, Line 78: io 0x60 = 0x0a30
I could just remove it, the environment controller is not actually needed in the devices built aroun […]
Wait, is said fan controlled by the Super I/O? If so, I'd keep the LDN
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/18/src/mainboard/bostentech/g... PS18, Line 78: io 0x60 = 0x0a30
Wait, is said fan controlled by the Super I/O? If so, I'd keep the LDN
It's only an unused fan header, and I can't tell if it's on the SuperIO without more testing. I will keep the LDN for now just in case.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 27:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 27: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@9 PS27, Line 9: - Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) Please wrap lines around at 72 characters
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@16 PS27, Line 16: ITE8728F nit: IT8728F
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@20 PS27, Line 20: #43133 CB:43133
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 83: spurious tab?
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 13: : /* NOTE: SPD must be read manually as mrc.bin's SMBus support is broken */ : enable_smbus(); : i2c_eeprom_read(0x50, 0, sizeof(spd_buf), spd_buf); Could we have this workaround in common code? If dram_info_location is set to SMBUS, then read the SPDs into an array.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 11: register "ide_legacy_combined" = "0x0" You can drop this
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 28:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... PS28, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... PS28, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 28: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... PS28, Line 123: #if CONFIG(VGA_ROM_RUN) Do you need preprocessor for this? With regular C code it gets buildtested.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... PS28, Line 123: #if CONFIG(VGA_ROM_RUN)
Do you need preprocessor for this? With regular C code it gets buildtested.
It's currently the default for baytrail. I think it would be better to leave it like this and factor it out at some point (google/rambi has the same thing)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 13: : /* NOTE: SPD must be read manually as mrc.bin's SMBus support is broken */ : enable_smbus(); : i2c_eeprom_read(0x50, 0, sizeof(spd_buf), spd_buf);
Could we have this workaround in common code? If dram_info_location is set to SMBUS, then read the S […]
Ack (can be fixed later)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#29).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an IT8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch CB:43133) - Booting from SATA works with GRUB2, SATA works in Linux - Patch CB:44088 fixes SATA in SeaBIOS - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 678 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/29
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 29:
(5 comments)
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@9 PS27, Line 9: - Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware)
Please wrap lines around at 72 characters
Done
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@16 PS27, Line 16: ITE8728F
nit: IT8728F
Done
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@20 PS27, Line 20: #43133
CB:43133
Done
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 11: register "ide_legacy_combined" = "0x0"
You can drop this
Done
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 13: : /* NOTE: SPD must be read manually as mrc.bin's SMBus support is broken */ : enable_smbus(); : i2c_eeprom_read(0x50, 0, sizeof(spd_buf), spd_buf);
Ack (can be fixed later)
I pushed a commit that moves this to soc code.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 29:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/29/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/29/src/mainboard/bostentech/g... PS29, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/29/src/mainboard/bostentech/g... PS29, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 29:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... PS28, Line 123: #if CONFIG(VGA_ROM_RUN)
It's currently the default for baytrail. […]
I can't easily do that, as x86emu doesn't get built if VGA_ROM_RUN is disabled and the code above failes to build.
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 29:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 83:
spurious tab?
Done
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 29:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/43087/28/src/mainboard/bostentech/g... PS28, Line 123: #if CONFIG(VGA_ROM_RUN)
I can't easily do that, as x86emu doesn't get built if VGA_ROM_RUN is disabled and the code above fa […]
Ack
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#31).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an IT8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch CB:43133) - Booting from SATA works with GRUB2, SATA works in Linux - Patch CB:44088 fixes SATA in SeaBIOS - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 678 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/31
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 31:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/31/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/31/src/mainboard/bostentech/g... PS31, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/31/src/mainboard/bostentech/g... PS31, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 31: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/31/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/31/src/mainboard/bostentech/g... PS31, Line 6: #include <soc/mrc_wrapper.h> only this one is needed now?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43087
to look at the new patch set (#33).
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an IT8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch CB:43133) - Booting from SATA works with GRUB2, SATA works in Linux - Patch CB:44088 fixes SATA in SeaBIOS - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 674 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/33
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 33:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43087/31/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/31/src/mainboard/bostentech/g... PS31, Line 6: #include <soc/mrc_wrapper.h>
only this one is needed now?
romstage.h is also needed as it provides the prototype for mainboard_fill_mrc_params, I removed everything else.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 33:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/33/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/33/src/mainboard/bostentech/g... PS33, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/33/src/mainboard/bostentech/g... PS33, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 33: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 33: Code-Review+2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 34:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43087/34/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/irqroute.h:
https://review.coreboot.org/c/coreboot/+/43087/34/src/mainboard/bostentech/g... PS34, Line 6: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43087/34/src/mainboard/bostentech/g... PS34, Line 14: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
mb/bostentech: Add GBYT4 port
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an IT8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch CB:43133) - Booting from SATA works with GRUB2, SATA works in Linux - Patch CB:44088 fixes SATA in SeaBIOS - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything
Used rambi as an example, but almost everything is modified as the two boards are very different.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43087 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/bostentech/Kconfig A src/mainboard/bostentech/Kconfig.name A src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/Kconfig.name A src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/acpi/ec.asl A src/mainboard/bostentech/gbyt4/acpi/mainboard.asl A src/mainboard/bostentech/gbyt4/acpi/superio.asl A src/mainboard/bostentech/gbyt4/acpi_tables.c A src/mainboard/bostentech/gbyt4/board_info.txt A src/mainboard/bostentech/gbyt4/cmos.layout A src/mainboard/bostentech/gbyt4/devicetree.cb A src/mainboard/bostentech/gbyt4/dsdt.asl A src/mainboard/bostentech/gbyt4/early_init.c A src/mainboard/bostentech/gbyt4/gpio.c A src/mainboard/bostentech/gbyt4/irqroute.c A src/mainboard/bostentech/gbyt4/irqroute.h A src/mainboard/bostentech/gbyt4/mainboard.c A src/mainboard/bostentech/gbyt4/romstage.c 19 files changed, 674 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/bostentech/Kconfig b/src/mainboard/bostentech/Kconfig new file mode 100644 index 0000000..15a7657 --- /dev/null +++ b/src/mainboard/bostentech/Kconfig @@ -0,0 +1,19 @@ +if VENDOR_BOSTENTECH + +choice + prompt "Mainboard model" + +source "src/mainboard/bostentech/*/Kconfig.name" + +endchoice + +source "src/mainboard/bostentech/*/Kconfig" + +config MAINBOARD_VENDOR + default "Shenzhen Bostrontium Teng Technology" + +config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + +endif # VENDOR_BOSTENTECH diff --git a/src/mainboard/bostentech/Kconfig.name b/src/mainboard/bostentech/Kconfig.name new file mode 100644 index 0000000..619b526 --- /dev/null +++ b/src/mainboard/bostentech/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_BOSTENTECH + bool "Shenzhen Bostrontium Teng Technology" diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig new file mode 100644 index 0000000..a267840 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -0,0 +1,24 @@ +if BOARD_BOSTENTECH_GBYT4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "bostentech/gbyt4" + +config MAINBOARD_PART_NUMBER + string + default "GBYT4-4L" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Shenzhen Bostrontium Teng Technology" + +endif # BOARD_BOSTENTECH_GBYT4 diff --git a/src/mainboard/bostentech/gbyt4/Kconfig.name b/src/mainboard/bostentech/gbyt4/Kconfig.name new file mode 100644 index 0000000..c420d5b --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_BOSTENTECH_GBYT4 + bool "GBYT4" diff --git a/src/mainboard/bostentech/gbyt4/Makefile.inc b/src/mainboard/bostentech/gbyt4/Makefile.inc new file mode 100644 index 0000000..11a2a4a --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += irqroute.c gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/bostentech/gbyt4/acpi/ec.asl b/src/mainboard/bostentech/gbyt4/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/acpi/ec.asl diff --git a/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl b/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl new file mode 100644 index 0000000..d679d2e --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * NOTE: this has to be here even when the board has no LPE audio, otherwise + * it breaks the SOC specific ACPI code + */ +Scope (_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () {}) +} diff --git a/src/mainboard/bostentech/gbyt4/acpi/superio.asl b/src/mainboard/bostentech/gbyt4/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/acpi/superio.asl diff --git a/src/mainboard/bostentech/gbyt4/acpi_tables.c b/src/mainboard/bostentech/gbyt4/acpi_tables.c new file mode 100644 index 0000000..162a08c --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/acpi_tables.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include <soc/iomap.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM not present */ + gnvs->tpmp = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_DESKTOP; +} diff --git a/src/mainboard/bostentech/gbyt4/board_info.txt b/src/mainboard/bostentech/gbyt4/board_info.txt new file mode 100644 index 0000000..0fe176f --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Shenzhen Bostrontium Teng Technology +Board name: GBYT4 +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/bostentech/gbyt4/cmos.layout b/src/mainboard/bostentech/gbyt4/cmos.layout new file mode 100644 index 0000000..f0d18dd --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/cmos.layout @@ -0,0 +1,48 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +# coreboot config options: cpu +400 1 e 2 hyper_threading +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/bostentech/gbyt4/devicetree.cb b/src/mainboard/bostentech/gbyt4/devicetree.cb new file mode 100644 index 0000000..15a5d86 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/devicetree.cb @@ -0,0 +1,90 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x3" + register "sata_ahci" = "0x1" + + # Do not route USB ports to XHCI + register "usb_route_to_xhci" = "0" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 10.0 off end # MMC + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC45 + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 off end # HDA + device pci 1c.0 on end # PCI-e #1 (LAN1) + device pci 1c.1 on end # PCI-e #2 (LAN2) + device pci 1c.2 on end # PCI-e #3 (LAN3) + device pci 1c.3 on end # PCI-e #4 (LAN4) + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + + device pci 1f.0 on # LPC + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + irq 0x70 = 9 + io 0x62 = 0x0a20 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/bostentech/gbyt4/dsdt.asl b/src/mainboard/bostentech/gbyt4/dsdt.asl new file mode 100644 index 0000000..56e01c4 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/baytrail/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/baytrail/acpi/southcluster.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/bostentech/gbyt4/early_init.c b/src/mainboard/bostentech/gbyt4/early_init.c new file mode 100644 index 0000000..9b12a3d --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/early_init.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, 0x01) + +void bootblock_mainboard_early_init(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/bostentech/gbyt4/gpio.c b/src/mainboard/bostentech/gbyt4/gpio.c new file mode 100644 index 0000000..e1d5df8 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/gpio.c @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_INPUT, /* GPIO_S0_NC[00] */ + GPIO_INPUT, /* GPIO_S0_NC[01] */ + GPIO_INPUT, /* GPIO_S0_NC[02] */ + GPIO_INPUT, /* GPIO_S0_NC[03] */ + GPIO_INPUT, /* GPIO_S0_NC[04] */ + GPIO_INPUT, /* GPIO_S0_NC[05] */ + GPIO_INPUT, /* GPIO_S0_NC[06] */ + GPIO_INPUT, /* GPIO_S0_NC[07] */ + GPIO_INPUT, /* GPIO_S0_NC[08] */ + GPIO_INPUT, /* GPIO_S0_NC[09] */ + GPIO_INPUT, /* GPIO_S0_NC[10] */ + GPIO_INPUT, /* GPIO_S0_NC[11] */ + GPIO_INPUT, /* GPIO_S0_NC[12] */ + GPIO_INPUT, /* GPIO_S0_NC[13] */ + GPIO_INPUT, /* GPIO_S0_NC[14] */ + GPIO_INPUT, /* GPIO_S0_NC[15] */ + GPIO_INPUT, /* GPIO_S0_NC[16] */ + GPIO_INPUT, /* GPIO_S0_NC[17] */ + GPIO_INPUT, /* GPIO_S0_NC[18] */ + GPIO_INPUT, /* GPIO_S0_NC[19] */ + GPIO_INPUT, /* GPIO_S0_NC[20] */ + GPIO_INPUT, /* GPIO_S0_NC[21] */ + GPIO_INPUT, /* GPIO_S0_NC[22] */ + GPIO_INPUT, /* GPIO_S0_NC[23] */ + GPIO_INPUT, /* GPIO_S0_NC[24] */ + GPIO_INPUT, /* GPIO_S0_NC[25] */ + GPIO_INPUT, /* GPIO_S0_NC[26] */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_INPUT, /* GPIO_S0_SC[000] */ + GPIO_INPUT, /* GPIO_S0_SC[001] */ + GPIO_FUNC1, /* SATA_LED# */ + GPIO_FUNC1, /* PCIE_CLKREQ[0]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[1]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[2]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[3]# */ + GPIO_INPUT, /* GPIO_S0_SC[007] */ + GPIO_INPUT, /* GPIO_S0_SC[008] */ + GPIO_INPUT, /* GPIO_S0_SC[009] */ + GPIO_INPUT, /* GPIO_S0_SC[010] */ + GPIO_INPUT, /* GPIO_S0_SC[011] */ + GPIO_INPUT, /* GPIO_S0_SC[012] */ + GPIO_INPUT, /* GPIO_S0_SC[013] */ + GPIO_INPUT, /* GPIO_S0_SC[014] */ + GPIO_INPUT, /* GPIO_S0_SC[015] */ + GPIO_INPUT, /* GPIO_S0_SC[016] */ + GPIO_INPUT, /* GPIO_S0_SC[017] */ + GPIO_INPUT, /* GPIO_S0_SC[018] */ + GPIO_INPUT, /* GPIO_S0_SC[019] */ + GPIO_INPUT, /* GPIO_S0_SC[020] */ + GPIO_INPUT, /* GPIO_S0_SC[021] */ + GPIO_INPUT, /* GPIO_S0_SC[022] */ + GPIO_INPUT, /* GPIO_S0_SC[023] */ + GPIO_INPUT, /* GPIO_S0_SC[024] */ + GPIO_INPUT, /* GPIO_S0_SC[025] */ + GPIO_INPUT, /* GPIO_S0_SC[026] */ + GPIO_INPUT, /* GPIO_S0_SC[027] */ + GPIO_INPUT, /* GPIO_S0_SC[028] */ + GPIO_INPUT, /* GPIO_S0_SC[029] */ + GPIO_INPUT, /* GPIO_S0_SC[030] */ + GPIO_INPUT, /* GPIO_S0_SC[031] */ + GPIO_INPUT, /* GPIO_S0_SC[032] */ + GPIO_INPUT, /* GPIO_S0_SC[033] */ + GPIO_INPUT, /* GPIO_S0_SC[034] */ + GPIO_INPUT, /* GPIO_S0_SC[035] */ + GPIO_INPUT, /* GPIO_S0_SC[036] */ + GPIO_INPUT, /* GPIO_S0_SC[037] */ + GPIO_INPUT, /* GPIO_S0_SC[038] */ + GPIO_INPUT, /* GPIO_S0_SC[039] */ + GPIO_INPUT, /* GPIO_S0_SC[040] */ + GPIO_INPUT, /* GPIO_S0_SC[041] */ + GPIO_FUNC1, /* ILB_LPC_AD[0] */ + GPIO_FUNC1, /* ILB_LPC_AD[1] */ + GPIO_FUNC1, /* ILB_LPC_AD[2] */ + GPIO_FUNC1, /* ILB_LPC_AD[3] */ + GPIO_FUNC1, /* ILB_LPC_FRAME# */ + GPIO_FUNC1, /* ILB_LPC_CLK[0] */ + GPIO_FUNC1, /* ILB_LPC_CLK[1] */ + GPIO_FUNC1, /* ILB_LPC_CLKRUN# */ + GPIO_FUNC1, /* ILB_LPC_SERIRQ */ + GPIO_FUNC1, /* PCU_SMB_DATA */ + GPIO_FUNC1, /* PCU_SMB_CLK */ + GPIO_FUNC1, /* PCU_SMB_ALERT# */ + GPIO_FUNC1, /* ILB_8254_SPKR */ + GPIO_INPUT, /* GPIO_S0_SC[055] */ + GPIO_INPUT, /* GPIO_S0_SC[056] */ + GPIO_INPUT, /* GPIO_S0_SC[057] */ + GPIO_INPUT, /* GPIO_S0_SC[058] */ + GPIO_INPUT, /* GPIO_S0_SC[059] */ + GPIO_INPUT, /* GPIO_S0_SC[060] */ + GPIO_INPUT, /* GPIO_S0_SC[061] */ + GPIO_INPUT, /* GPIO_S0_SC[062] */ + GPIO_INPUT, /* GPIO_S0_SC[063] */ + GPIO_INPUT, /* GPIO_S0_SC[064] */ + GPIO_INPUT, /* GPIO_S0_SC[065] */ + GPIO_INPUT, /* GPIO_S0_SC[066] */ + GPIO_INPUT, /* GPIO_S0_SC[067] */ + GPIO_INPUT, /* GPIO_S0_SC[068] */ + GPIO_INPUT, /* GPIO_S0_SC[069] */ + GPIO_INPUT, /* GPIO_S0_SC[070] */ + GPIO_INPUT, /* GPIO_S0_SC[071] */ + GPIO_INPUT, /* GPIO_S0_SC[072] */ + GPIO_INPUT, /* GPIO_S0_SC[073] */ + GPIO_INPUT, /* GPIO_S0_SC[074] */ + GPIO_INPUT, /* GPIO_S0_SC[075] */ + GPIO_INPUT, /* GPIO_S0_SC[076] */ + GPIO_INPUT, /* GPIO_S0_SC[077] */ + GPIO_INPUT, /* GPIO_S0_SC[078] */ + GPIO_INPUT, /* GPIO_S0_SC[079] */ + GPIO_INPUT, /* GPIO_S0_SC[080] */ + GPIO_INPUT, /* GPIO_S0_SC[081] */ + GPIO_INPUT, /* GPIO_S0_SC[082] */ + GPIO_INPUT, /* GPIO_S0_SC[083] */ + GPIO_INPUT, /* GPIO_S0_SC[084] */ + GPIO_INPUT, /* GPIO_S0_SC[085] */ + GPIO_INPUT, /* GPIO_S0_SC[086] */ + GPIO_INPUT, /* GPIO_S0_SC[087] */ + GPIO_INPUT, /* GPIO_S0_SC[088] */ + GPIO_INPUT, /* GPIO_S0_SC[089] */ + GPIO_INPUT, /* GPIO_S0_SC[090] */ + GPIO_INPUT, /* GPIO_S0_SC[091] */ + GPIO_INPUT, /* GPIO_S0_SC[092] */ + GPIO_INPUT, /* GPIO_S0_SC[093] */ + GPIO_INPUT, /* GPIO_S0_SC[094] */ + GPIO_INPUT, /* GPIO_S0_SC[095] */ + GPIO_INPUT, /* GPIO_S0_SC[096] */ + GPIO_INPUT, /* GPIO_S0_SC[097] */ + GPIO_INPUT, /* GPIO_S0_SC[098] */ + GPIO_INPUT, /* GPIO_S0_SC[099] */ + GPIO_INPUT, /* GPIO_S0_SC[100] */ + GPIO_INPUT, /* GPIO_S0_SC[101] */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_INPUT, /* GPIO_S5[00] */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[1]# */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[2]# */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[3]# */ + GPIO_INPUT, /* GPIO_S5[04] */ + GPIO_INPUT, /* GPIO_S5[05] */ + GPIO_INPUT, /* GPIO_S5[06] */ + GPIO_INPUT, /* GPIO_S5[07] */ + GPIO_INPUT, /* GPIO_S5[08] */ + GPIO_INPUT, /* GPIO_S5[09] */ + GPIO_INPUT, /* GPIO_S5[10] */ + GPIO_INPUT, /* GPIO_S5[11] */ + GPIO_INPUT, /* GPIO_S5[12] */ + GPIO_INPUT, /* GPIO_S5[13] */ + GPIO_INPUT, /* GPIO_S5[14] */ + GPIO_FUNC0, /* PMC_WAKE_PCIE[0]# */ + GPIO_FUNC(0, PULL_UP, 20K), /* PMC_PWRBTN# */ + GPIO_INPUT, /* GPIO_S5[17] */ + GPIO_INPUT, /* GPIO_S5[18] */ + GPIO_INPUT, /* GPIO_S5[19] */ + GPIO_INPUT, /* GPIO_S5[20] */ + GPIO_INPUT, /* GPIO_S5[21] */ + GPIO_INPUT, /* GPIO_S5[22] */ + GPIO_INPUT, /* GPIO_S5[23] */ + GPIO_INPUT, /* GPIO_S5[24] */ + GPIO_INPUT, /* GPIO_S5[25] */ + GPIO_INPUT, /* GPIO_S5[26] */ + GPIO_INPUT, /* GPIO_S5[27] */ + GPIO_INPUT, /* GPIO_S5[28] */ + GPIO_INPUT, /* GPIO_S5[29] */ + GPIO_INPUT, /* GPIO_S5[30] */ + GPIO_INPUT, /* GPIO_S5[31] */ + GPIO_INPUT, /* GPIO_S5[32] */ + GPIO_INPUT, /* GPIO_S5[33] */ + GPIO_INPUT, /* GPIO_S5[34] */ + GPIO_INPUT, /* GPIO_S5[35] */ + GPIO_INPUT, /* GPIO_S5[36] */ + GPIO_INPUT, /* GPIO_S5[37] */ + GPIO_INPUT, /* GPIO_S5[38] */ + GPIO_INPUT, /* GPIO_S5[39] */ + GPIO_INPUT, /* GPIO_S5[40] */ + GPIO_INPUT, /* GPIO_S5[41] */ + GPIO_INPUT, /* GPIO_S5[42] */ + GPIO_INPUT, /* GPIO_S5[43] */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/bostentech/gbyt4/irqroute.c b/src/mainboard/bostentech/gbyt4/irqroute.c new file mode 100644 index 0000000..6fa0366 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/irqroute.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/bostentech/gbyt4/irqroute.h b/src/mainboard/bostentech/gbyt4/irqroute.h new file mode 100644 index 0000000..9460622 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/irqroute.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) diff --git a/src/mainboard/bostentech/gbyt4/mainboard.c b/src/mainboard/bostentech/gbyt4/mainboard.c new file mode 100644 index 0000000..c385846 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/mainboard.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG(VGA_ROM_RUN) +#include <x86emu/x86emu.h> +#endif +#include <acpi/acpi.h> +#include <arch/interrupt.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <bootstate.h> + +void mainboard_suspend_resume(void) +{ +} + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video BIOS default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +static void mainboard_init(struct device *dev) +{ + +} + +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + return 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/bostentech/gbyt4/romstage.c b/src/mainboard/bostentech/gbyt4/romstage.c new file mode 100644 index 0000000..ec18cfc --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/romstage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/mrc_wrapper.h> +#include <soc/romstage.h> + +void mainboard_fill_mrc_params(struct mrc_params *mp) +{ + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_SMBUS; + mp->mainboard.dram_is_slotted = 1; + mp->mainboard.spd_addrs[0] = 0x50; /* Board only has one slot */ +}
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