Máté Kukri has uploaded this change for review.
Added GBYT4 port
Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe
---
A src/mainboard/unk/Kconfig
A src/mainboard/unk/Kconfig.name
A src/mainboard/unk/gbyt4/Kconfig
A src/mainboard/unk/gbyt4/Kconfig.name
A src/mainboard/unk/gbyt4/Makefile.inc
A src/mainboard/unk/gbyt4/acpi/dptf.asl
A src/mainboard/unk/gbyt4/acpi/ec.asl
A src/mainboard/unk/gbyt4/acpi/mainboard.asl
A src/mainboard/unk/gbyt4/acpi/superio.asl
A src/mainboard/unk/gbyt4/acpi_tables.c
A src/mainboard/unk/gbyt4/board_info.txt
A src/mainboard/unk/gbyt4/cmos.layout
A src/mainboard/unk/gbyt4/devicetree.cb
A src/mainboard/unk/gbyt4/dsdt.asl
A src/mainboard/unk/gbyt4/early_init.c
A src/mainboard/unk/gbyt4/gpio.c
A src/mainboard/unk/gbyt4/irqroute.c
A src/mainboard/unk/gbyt4/irqroute.h
A src/mainboard/unk/gbyt4/mainboard.c
A src/mainboard/unk/gbyt4/romstage.c
20 files changed, 792 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/1
diff --git a/src/mainboard/unk/Kconfig b/src/mainboard/unk/Kconfig
new file mode 100644
index 0000000..86fe2d6
--- /dev/null
+++ b/src/mainboard/unk/Kconfig
@@ -0,0 +1,19 @@
+if VENDOR_UNK
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/unk/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/unk/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ default "Unknown"
+
+config MAINBOARD_FAMILY
+ string
+ default MAINBOARD_PART_NUMBER
+
+endif # VENDOR_UNK
diff --git a/src/mainboard/unk/Kconfig.name b/src/mainboard/unk/Kconfig.name
new file mode 100644
index 0000000..a5f8bf4
--- /dev/null
+++ b/src/mainboard/unk/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_UNK
+ bool "Unknown"
diff --git a/src/mainboard/unk/gbyt4/Kconfig b/src/mainboard/unk/gbyt4/Kconfig
new file mode 100644
index 0000000..b57f977
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/Kconfig
@@ -0,0 +1,24 @@
+if BOARD_UNK_GBYT4
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_BAYTRAIL
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select SUPERIO_ITE_IT8728F
+
+config MAINBOARD_DIR
+ string
+ default "unk/gbyt4"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "GBYT4"
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+ string
+ default "UNKNOWN"
+
+endif # BOARD_KM_GBYT4
diff --git a/src/mainboard/unk/gbyt4/Kconfig.name b/src/mainboard/unk/gbyt4/Kconfig.name
new file mode 100644
index 0000000..29c4e9d
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_UNK_GBYT4
+ bool "GBYT4"
diff --git a/src/mainboard/unk/gbyt4/Makefile.inc b/src/mainboard/unk/gbyt4/Makefile.inc
new file mode 100644
index 0000000..2bde1bd
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/Makefile.inc
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += irqroute.c gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c
+
+# Temporary shit to test MRC
+cbfs-files-y += spd.bin
+spd.bin-file := spd.bin
+spd.bin-type := spd
diff --git a/src/mainboard/unk/gbyt4/acpi/dptf.asl b/src/mainboard/unk/gbyt4/acpi/dptf.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/acpi/dptf.asl
diff --git a/src/mainboard/unk/gbyt4/acpi/ec.asl b/src/mainboard/unk/gbyt4/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/acpi/ec.asl
diff --git a/src/mainboard/unk/gbyt4/acpi/mainboard.asl b/src/mainboard/unk/gbyt4/acpi/mainboard.asl
new file mode 100644
index 0000000..f343574
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/acpi/mainboard.asl
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.LPEA)
+{
+ Name (GBUF, ResourceTemplate ()
+ {
+ /* Jack Detect (index 0) */
+ GpioInt (Level, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 14 }
+
+ /* Mic Detect (index 1) */
+ GpioInt (Level, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 15 }
+ })
+}
diff --git a/src/mainboard/unk/gbyt4/acpi/superio.asl b/src/mainboard/unk/gbyt4/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/acpi/superio.asl
diff --git a/src/mainboard/unk/gbyt4/acpi_tables.c b/src/mainboard/unk/gbyt4/acpi_tables.c
new file mode 100644
index 0000000..41ec5f9
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/acpi_tables.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <types.h>
+#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* TPM Present */
+ gnvs->tpmp = 0;
+
+ /* Enable DPTF */
+ gnvs->dpte = 0;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+ fadt->preferred_pm_profile = PM_MOBILE;
+}
diff --git a/src/mainboard/unk/gbyt4/board_info.txt b/src/mainboard/unk/gbyt4/board_info.txt
new file mode 100644
index 0000000..5152b2a
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/board_info.txt
@@ -0,0 +1,7 @@
+Vendor name: Unknown
+Board name: GBYT4
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/unk/gbyt4/cmos.layout b/src/mainboard/unk/gbyt4/cmos.layout
new file mode 100644
index 0000000..da1b185
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/cmos.layout
@@ -0,0 +1,89 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/unk/gbyt4/devicetree.cb b/src/mainboard/unk/gbyt4/devicetree.cb
new file mode 100644
index 0000000..d442127
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/devicetree.cb
@@ -0,0 +1,94 @@
+chip soc/intel/baytrail
+
+ register "usb2_comp_bg" = "0x4700"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ # IGD Displays
+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+
+ # Do not route USB ports to XHCI
+ register "usb_route_to_xhci" = "0"
+
+ # USB Port Disable Mask
+ register "usb2_port_disable_mask" = "0x0"
+ register "usb3_port_disable_mask" = "0x0"
+
+ # USB PHY settings
+ register "usb2_per_port_lane0" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+ register "usb2_per_port_lane1" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+ register "usb2_per_port_lane2" = "0x00049209"
+ register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+ register "usb2_per_port_lane3" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+ # Disable SLP_X stretching after SUS power well fail.
+ register "disable_slp_x_stretch_sus_fail" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 10.0 off end # MMC
+ device pci 11.0 off end # SDIO
+ device pci 12.0 off end # SD
+ device pci 13.0 on end # SATA
+ device pci 14.0 off end # XHCI
+ device pci 15.0 off end # LPE
+ device pci 17.0 off end # MMC45
+ device pci 18.0 off end # SIO_DMA1
+ device pci 18.1 off end # I2C1
+ device pci 18.2 off end # I2C2
+ device pci 18.3 off end # I2C3
+ device pci 18.4 off end # I2C4
+ device pci 18.5 off end # I2C5
+ device pci 18.6 off end # I2C6
+ device pci 18.7 off end # I2C7
+ device pci 1a.0 on end # TXE
+ device pci 1b.0 off end # HDA
+ device pci 1c.0 on end # PCI-e #1 (LAN1)
+ device pci 1c.1 on end # PCI-e #2 (LAN2)
+ device pci 1c.2 on end # PCI-e #3 (LAN3)
+ device pci 1c.3 on end # PCI-e #4 (LAN4)
+ device pci 1d.0 on end # EHCI
+ device pci 1e.0 off end # SIO_DMA2
+ device pci 1e.1 off end # PWM1
+ device pci 1e.2 off end # PWM2
+ device pci 1e.3 off end # HSUART1
+ device pci 1e.4 off end # HSUART2
+ device pci 1e.5 off end # SPI
+
+ device pci 1f.0 on # LPC
+ chip superio/ite/it8728f
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # COM1
+ io 0x60 = 0x03f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off end # COM2
+ device pnp 2e.3 off end # Parallel port
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0x0a30
+ irq 0x70 = 9
+ io 0x62 = 0x0a20
+ end
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.a off end # CIR
+ end
+ end
+
+ device pci 1f.3 on end # SMBus
+ end
+end
diff --git a/src/mainboard/unk/gbyt4/dsdt.asl b/src/mainboard/unk/gbyt4/dsdt.asl
new file mode 100644
index 0000000..fb037b1
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/dsdt.asl
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define ENABLE_TPM
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/baytrail/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/baytrail/acpi/globalnvs.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ //#include <soc/intel/baytrail/acpi/northcluster.asl>
+ #include <soc/intel/baytrail/acpi/southcluster.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ #include "acpi/dptf.asl"
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/unk/gbyt4/early_init.c b/src/mainboard/unk/gbyt4/early_init.c
new file mode 100644
index 0000000..89da435
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/early_init.c
@@ -0,0 +1,11 @@
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, 0x01)
+
+void bootblock_mainboard_early_init(void)
+{
+ /* Enable serial port */
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/unk/gbyt4/gpio.c b/src/mainboard/unk/gbyt4/gpio.c
new file mode 100644
index 0000000..b5e68c1
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/gpio.c
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <mainboard/unk/gbyt4/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+ GPIO_FUNC(2, PULL_UP, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(2, PULL_DISABLE, 20K),
+ GPIO_FUNC(2, PULL_DISABLE, 20K),
+ GPIO_FUNC(2, PULL_DISABLE, 20K),
+ GPIO_FUNC(2, PULL_DISABLE, 20K),
+ GPIO_FUNC(2, PULL_DISABLE, 20K),
+ GPIO_FUNC(2, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(2, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(2, PULL_DISABLE, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_DOWN, 20K),
+ GPIO_FUNC(0, PULL_UP, 20K),
+ GPIO_FUNC(2, PULL_UP, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(0, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_DISABLE, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_FUNC(1, PULL_UP, 20K),
+ GPIO_FUNC(1, PULL_DOWN, 20K),
+ GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+};
+
+static struct soc_gpio_config gpio_config = {
+ .ncore = gpncore_gpio_map,
+ .score = gpscore_gpio_map,
+ .ssus = gpssus_gpio_map,
+ .core_dirq = &core_dedicated_irq,
+ .sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+ return &gpio_config;
+}
diff --git a/src/mainboard/unk/gbyt4/irqroute.c b/src/mainboard/unk/gbyt4/irqroute.c
new file mode 100644
index 0000000..6fa0366
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/irqroute.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/unk/gbyt4/irqroute.h b/src/mainboard/unk/gbyt4/irqroute.h
new file mode 100644
index 0000000..7dd9ad2
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/irqroute.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, DISABLE), \
+ PIRQ_PIC(B, DISABLE), \
+ PIRQ_PIC(C, DISABLE), \
+ PIRQ_PIC(D, DISABLE), \
+ PIRQ_PIC(E, DISABLE), \
+ PIRQ_PIC(F, DISABLE), \
+ PIRQ_PIC(G, DISABLE), \
+ PIRQ_PIC(H, DISABLE)
diff --git a/src/mainboard/unk/gbyt4/mainboard.c b/src/mainboard/unk/gbyt4/mainboard.c
new file mode 100644
index 0000000..b6ccc7f
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/mainboard.c
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#if CONFIG(VGA_ROM_RUN)
+#include <x86emu/x86emu.h>
+#endif
+#include <acpi/acpi.h>
+#include <arch/interrupt.h>
+#include <smbios.h>
+#include <soc/gpio.h>
+#include <bootstate.h>
+
+void mainboard_suspend_resume(void)
+{
+}
+
+#if CONFIG(VGA_ROM_RUN)
+static int int15_handler(void)
+{
+ int res = 1;
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video BIOS default
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001;
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV
+ * bit 2 = EFP (HDMI)
+ * bit 3 = LFP (eDP)*
+ * bit 4 = CRT2
+ * bit 5 = TV2
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0008;
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0003;
+ res = 1;
+ break;
+ case 0x5f70:
+ switch ((X86_CX >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG,
+ "Unknown INT15 5f70 function: 0x%02x\n",
+ ((X86_CX >> 8) & 0xff));
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+static void mainboard_init(struct device *dev)
+{
+
+}
+
+static int mainboard_smbios_data(struct device *dev, int *handle,
+ unsigned long *current)
+{
+ return 0;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->get_smbios_data = mainboard_smbios_data;
+#if CONFIG(VGA_ROM_RUN)
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/unk/gbyt4/romstage.c b/src/mainboard/unk/gbyt4/romstage.c
new file mode 100644
index 0000000..3ca7f77
--- /dev/null
+++ b/src/mainboard/unk/gbyt4/romstage.c
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+//static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
+//{
+// int ram_id = 0;
+//
+// /* The ram_id[2:0] pullups are too large for the default 20K
+// * pulldown on the pad. Therefore, disable the internal pull resistor to
+// * read high values correctly. */
+// ssus_disable_internal_pull(GPIO_SSUS_37_PAD);
+// ssus_disable_internal_pull(GPIO_SSUS_38_PAD);
+// ssus_disable_internal_pull(GPIO_SSUS_39_PAD);
+//#ifdef GPIO_SSUS_40_PAD_USE_PULLDOWN
+// /* To prevent floating pin on shipped systems. */
+// ssus_enable_internal_pull(GPIO_SSUS_40_PAD, PAD_PULL_DOWN | PAD_PU_20K);
+//#elif defined(GPIO_SSUS_40_PAD)
+// ssus_disable_internal_pull(GPIO_SSUS_40_PAD);
+//#endif
+// ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
+// ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
+// ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
+//#ifdef GPIO_SSUS_40_PAD
+// ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3);
+//#endif
+// printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
+//
+// if (ram_id >= total_spds)
+// return NULL;
+//
+// /* Single channel configs */
+// if (dual_channel_config & (1 << ram_id))
+// *dual = 1;
+//
+// return &spd_file_content[SPD_SIZE * ram_id];
+//}
+
+void mainboard_fill_mrc_params(struct mrc_params *mp)
+{
+ /*void *spd_content;*/
+ int dual_channel = 0;
+ void *spd_file;
+ size_t spd_fsize;
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_fsize);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ /*spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
+ &dual_channel);*/
+
+ mp->mainboard.dram_type = DRAM_DDR3L;
+ mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM;
+ mp->mainboard.dram_is_slotted = 1;
+
+ mp->mainboard.dram_data[0] = spd_file;
+ if (dual_channel)
+ mp->mainboard.dram_data[1] = spd_file;
+}
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