Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mb/asus/p8z77-m: New board ......................................................................
mb/asus/p8z77-m: New board
Constructed out of a mix of autoport results, p8z77-m_pro, and inteltool/superiotool dumps.
Does not yet boot. Submitting for eyeballs and help.
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c A src/mainboard/asus/p8z77-m/mainboard.c 17 files changed, 969 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/1
diff --git a/src/mainboard/asus/p8z77-m/Kconfig b/src/mainboard/asus/p8z77-m/Kconfig new file mode 100644 index 0000000..260597d --- /dev/null +++ b/src/mainboard/asus/p8z77-m/Kconfig @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8Z77_M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select SUPERIO_NUVOTON_NCT6779D + +config MAINBOARD_DIR + string + default "asus/p8z77-m" + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-M" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asus/p8z77-m/Kconfig.name b/src/mainboard/asus/p8z77-m/Kconfig.name new file mode 100644 index 0000000..a797a5b --- /dev/null +++ b/src/mainboard/asus/p8z77-m/Kconfig.name @@ -0,0 +1,15 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_ASUS_P8Z77_M + bool "P8Z77-M" diff --git a/src/mainboard/asus/p8z77-m/Makefile.inc b/src/mainboard/asus/p8z77-m/Makefile.inc new file mode 100644 index 0000000..a12efbb --- /dev/null +++ b/src/mainboard/asus/p8z77-m/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8z77-m/acpi/ec.asl b/src/mainboard/asus/p8z77-m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-m/acpi/platform.asl b/src/mainboard/asus/p8z77-m/acpi/platform.asl new file mode 100644 index 0000000..d2cad26 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/acpi/platform.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asus/p8z77-m/acpi/superio.asl b/src/mainboard/asus/p8z77-m/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/asus/p8z77-m/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/p8z77-m/acpi_tables.c b/src/mainboard/asus/p8z77-m/acpi_tables.c new file mode 100644 index 0000000..9c22f19 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/acpi_tables.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic vladocb@protonmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* critical temp that will shutdown the pc == 95C degrees */ + gnvs->tcrt = 95; + + /* temp to start throttling the cpu == 85C */ + gnvs->tpsv = 85; +} diff --git a/src/mainboard/asus/p8z77-m/cmos.default b/src/mainboard/asus/p8z77-m/cmos.default new file mode 100644 index 0000000..725ab98 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/cmos.default @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic vladocb@protonmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +boot_option=Fallback +debug_level=Debug +gfx_uma_size=224M +nmi=Enable +sata_mode=AHCI +#usb3_xxxx options are only used with MRC blob, ignored else +usb3_mode=Enable +usb3_drv=Enable +usb3_streams=Enable diff --git a/src/mainboard/asus/p8z77-m/cmos.layout b/src/mainboard/asus/p8z77-m/cmos.layout new file mode 100644 index 0000000..da29d1c --- /dev/null +++ b/src/mainboard/asus/p8z77-m/cmos.layout @@ -0,0 +1,185 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic vladocb@protonmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused +#400 8 r 0 reserved for century byte + +# ----------------------------------------------------------------- +# coreboot config options: southbridge + +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +408 1 e 1 nmi + +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# ----------------------------------------------------------------- +# coreboot config options: northbridge + +# gfx_uma_size +# Quantity of shared video memory the IGP can use +# +416 5 e 7 gfx_uma_size + +# ----------------------------------------------------------------- +# coreboot config options: usb3 + +# usb3_mode +# Controls how the motherboard's USB3 ports act at boot time +421 2 e 8 usb3_mode + +# usb3_drv +# Load (or not) pre-OS xHCI USB3 bios driver +# +423 1 e 1 usb3_drv + +# usb3_streams +# Streams can provide more speed (as they can use 64Kb packets), +# but they might cause incompatibilities with some devices. +# +424 1 e 1 usb3_streams + +# ----------------------------------------------------------------- +# Sandy/Ivy Bridge MRC Scrambler Seed values +# note: MUST NOT be covered by checksum! +464 32 r 0 mrc_scrambler_seed +496 32 r 0 mrc_scrambler_seed_s3 +528 16 r 0 mrc_scrambler_seed_chk + +# ----------------------------------------------------------------- +# coreboot config options: check sums +544 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +# power_on_after_fail +5 0 Disable +5 1 Enable +5 2 Keep + +# sata_mode +6 0 AHCI +6 1 Compatible + +# gfx_uma_size (Intel IGP Video RAM size) +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 544M +7 17 576M +7 18 608M +7 19 640M +7 20 672M +7 21 704M +7 22 736M +7 23 768M +7 24 800M +7 25 832M +7 26 864M +7 27 896M +7 28 928M +7 29 960M +7 30 992M + +# usb3_mode +# Disable = Use the port always as USB 2.0 for compatibility +# Enable = Use the port always as USB 3.0 for speed +# Auto = Initialize the port as USB 2.0, until the OS loads +# xHCI USB 3.0 driver +# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver +# and the computer is reset, keep the USB 3.0 mode. +# +8 0 Disable +8 1 Enable +8 2 Auto +8 3 SmartAuto + +# ----------------------------------------------------------------- +# <startBit[must be byte-aligned]> <endBit[must be byte aligned]> +# <bit where to start storing checksum[must be 16bits-aligned]> +checksums + +checksum 392 431 544 diff --git a/src/mainboard/asus/p8z77-m/data.vbt b/src/mainboard/asus/p8z77-m/data.vbt new file mode 100644 index 0000000..26ab42d --- /dev/null +++ b/src/mainboard/asus/p8z77-m/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8z77-m/devicetree.cb b/src/mainboard/asus/p8z77-m/devicetree.cb new file mode 100644 index 0000000..03a20b9 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/devicetree.cb @@ -0,0 +1,108 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x1043 0x84ca inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "gen4_dec" = "0x00000000" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" # the 4 ports + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 # COM2 address + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS2 KBC + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on end # GPIOs 6-8 + device pnp 2e.8 off end # WDT1 GPIO 0-1 + device pnp 2e.9 off end # GPIO 1-8 + device pnp 2e.a on # ACPI + drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3 + drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility + end + device pnp 2e.b off end # HWM, LED + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f on # GPIO PP/OD + drq 0xe6 = 0x7f # GP7 PP + end + device pnp 2e.14 on end # Port 80 UART + device pnp 2e.16 off end # Deep sleep + end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8z77-m/dsdt.asl b/src/mainboard/asus/p8z77-m/dsdt.asl new file mode 100644 index 0000000..62d44ea --- /dev/null +++ b/src/mainboard/asus/p8z77-m/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic vladocb@protonmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/p8z77-m/early_init.c b/src/mainboard/asus/p8z77-m/early_init.c new file mode 100644 index 0000000..52c0e03 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/early_init.c @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> + +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#include <option.h> + +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/pei_data.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* {enable, current, oc_pin} */ + { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ + { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ + { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ + { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ + { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ + { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ + { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ + { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ + { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ + { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ + { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ + { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ + { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ + { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ +}; + +/* Global config register values. */ +static const u8 register_values[] = { + /* + * Before accessing CR10, CR11, CR13 and CR14, CR26 [Bit4] must be set to logic 1. + * - NCT6779D datasheet, page 293 + */ + /* reg, value */ + 0x26, (1 << 4), + 0x13, 0xff, /* IRQs 0-15 active low */ + 0x14, 0xff, + 0x1b, 0x60, + 0x22, 0xdf, /* Power down UART B */ + 0x2a, 0x48, /* UART A instead of GPIO8x */ + 0x2c, 0x00, /* PECI */ +}; + +void bootblock_mainboard_early_init(void) +{ + int max = ARRAY_SIZE(register_values); + int i; + + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + + /* Set registers as specified in the register_values[] array. */ + for (i = 0; i < max; i += 2) + pnp_write_config(SERIAL_DEV, register_values[i], register_values[i + 1]); + + pnp_set_logical_device(SERIAL_DEV); + pnp_set_enable(SERIAL_DEV, 0); + pnp_set_iobase(SERIAL_DEV, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_enable(SERIAL_DEV, 1); + nuvoton_pnp_exit_conf_state(SERIAL_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* + * USB3 mode: + * 0 = Disable: work always as USB 2.0(ehci) + * 1 = Enable: work always as USB 3.0(xhci) + * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver + * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver + * and reboots, it will keep the USB3.0 speed + */ + int usb3_mode = 1; + get_option(&usb3_mode, "usb3_mode"); + usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */ + + /* Load USB3 pre-OS xHCI driver */ + int usb3_drv = 1; + get_option(&usb3_drv, "usb3_drv"); + usb3_drv &= 0x1; /* ensure it's 0/1 only */ + + /* Use USB3 xHCI streams */ + int usb3_streams = 1; + get_option(&usb3_streams, "usb3_streams"); + usb3_streams &= 0x1; /* ensure it's 0/1 only */ + + struct pei_data pd = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ + .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ + .dimm_channel0_disabled = 0, /* Both DIMM enabled */ + .dimm_channel1_disabled = 0, /* Both DIMM enabled */ + .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ + .usb_port_config = { + /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 1, 0x0080 }, /* USB3 ETH top connector */ + { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ + { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ + { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ + { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ + { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ + { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ + { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ + { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ + }, + .usb3 = { + /* 0=Disable; 1=Enable (start at USB3 speed) + * 2=Auto (start as USB2 speed until OS loads) + * 3=Smart Auto (like Auto but keep speed on reboot) + */ + usb3_mode, + /* 4 bit switch mask. 0=not switchable, 1=switchable + * Means once it's loaded the OS, it can swap ports + * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf + */ + 0xf, + usb3_drv, /* 1=Load xHCI pre-OS drv */ + /* 0=Don't use xHCI streams for better compatibility + * 1=use xHCI streams for better speed + */ + usb3_streams + }, + /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */ + .ddr3lv_support = 1, + /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, + * but might cause some system instability ! + */ + .pcie_init = 1, + /* Command Rate. 0=Auto; 1=1N; 2=2N. + * Leave it always at Auto for compatibility & stability + */ + .nmode = 0, + /* DDR refresh rate. 0=Auto based on DRAM's temperature; + * 1=Normal rate for speed; 2=Double rate for stability + */ + .ddr_refresh_rate_config = 0 + }; + + /* copy the data to output PEI */ + *pei_data = pd; +} diff --git a/src/mainboard/asus/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8z77-m/gma-mainboard.ads new file mode 100644 index 0000000..d7afe73 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8z77-m/gpio.c b/src/mainboard/asus/p8z77-m/gpio.c new file mode 100644 index 0000000..03e1507 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/gpio.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-m/hda_verb.c b/src/mainboard/asus/p8z77-m/hda_verb.c new file mode 100644 index 0000000..f240025 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/hda_verb.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x104384a8, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384a8), + AZALIA_PIN_CFG(0, 0x11, 0x90430130), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4016c629), + AZALIA_PIN_CFG(0, 0x1e, 0x01446140), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8z77-m/mainboard.c b/src/mainboard/asus/p8z77-m/mainboard.c new file mode 100644 index 0000000..b97b648 --- /dev/null +++ b/src/mainboard/asus/p8z77-m/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +};
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 4:
This change is ready for review.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/4//COMMIT_MSG@17 PS4, Line 17: - Native and MRC raminit With all memory sticks you have?
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 4:
Patch Set 4:
(1 comment)
So far I tested 3 sets of memory sticks. I have one set that works reliably. The other two are SODIMMs on adapters and are failing. In all 3 cases native and MRC yield same results - if native fails MRC also fails.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 4:
I think your port is another variant compared to this one: https://review.coreboot.org/c/coreboot/+/25662
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 4:
(15 comments)
Patch Set 4:
I think your port is another variant compared to this one: https://review.coreboot.org/c/coreboot/+/25662
It could be added as a variant, but I would wait a bit. I want to see if merging all the Asus sandy/ivy boards would be feasible. There's only two different SuperIOs.
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 21: select INTEL_INT15 This is used with the VBIOS, but I don't think anyone should be using it
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/board_info.txt:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 6: Flashrom support: ? Does `sudo flashrom -p internal --ifd -i bios -w build/coreboot.rom -N` work?
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/cmos.default:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 21: else otherwise
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 14: # FIXME: check gfx.ndid and gfx.did : register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" : register "gfx.ndid" = "3" Just remove them. They cause ACPI errors.
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 17: 0x0 0
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 25: 0x0 0
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 29: 0x0 0
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 37: register "gen4_dec" = "0x00000000" It's zero, you can remove it
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 53: Audio Audio It's stereo audio!
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 64: LPC bridge PCI-LPC bridge Some obnoxious redundancy here
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 95: # Deep sleep This comment is not aligned
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 17: #define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 Not needed.
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 88: void mainboard_fill_pei_data(struct pei_data *pei_data) I think you need to guard these
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 32: Internal At least "Internal" is not there. Replace it with:
Others => Disabled
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/mainboard.c:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 10: fix those values Or remove the entire file.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#5).
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
mainboard: New ivybridge board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- SeaBIOS boot - USB2 / USB3 - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/8x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 907 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/5
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 5:
(16 comments)
https://review.coreboot.org/c/coreboot/+/38988/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/4//COMMIT_MSG@17 PS4, Line 17: - Native and MRC raminit
With all memory sticks you have?
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 21: select INTEL_INT15
This is used with the VBIOS, but I don't think anyone should be using it
Want to test without this option?
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/board_info.txt:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 6: Flashrom support: ?
Does `sudo flashrom -p internal --ifd -i bios -w build/coreboot. […]
Needs kernel parameter iomem=relaxed. But it worked much faster than serprog on Arduino Mega.
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/cmos.default:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 21: else
otherwise
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 14: # FIXME: check gfx.ndid and gfx.did : register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" : register "gfx.ndid" = "3"
Just remove them. They cause ACPI errors.
Could we do same to p8z77-m_pro? and fix its Win10 ACPI errors?
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 17: 0x0
0
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 25: 0x0
0
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 29: 0x0
0
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 37: register "gen4_dec" = "0x00000000"
It's zero, you can remove it
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 53: Audio Audio
It's stereo audio!
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 64: LPC bridge PCI-LPC bridge
Some obnoxious redundancy here
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 95: # Deep sleep
This comment is not aligned
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 17: #define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0
Not needed.
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 88: void mainboard_fill_pei_data(struct pei_data *pei_data)
I think you need to guard these
Guard for bootblock or romstage?
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 32: Internal
At least "Internal" is not there. Replace it with: […]
This entire list has been distilled after more testing. Turns out to be identical to p8z77-m_pro.
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/mainboard.c:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 10: fix those values
Or remove the entire file.
Removed and it works just as well if not better.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 5: Code-Review+1
(11 comments)
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 21: select INTEL_INT15
Want to test without this option?
This option is for the code in mainboard.c, which got removed. So, you should also remove this option here.
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 8: pc PC
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 8: shutdown shut down
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 11: cpu CPU
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/board_info.txt:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 6: Flashrom support: ?
Needs kernel parameter iomem=relaxed. But it worked much faster than serprog on Arduino Mega.
Yes, bitbanging SPI is a bit slow. Even if iomem=relaxed is needed (another option is to unload some drivers, but I forget which), flashrom support should be `y`
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 14: # FIXME: check gfx.ndid and gfx.did : register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" : register "gfx.ndid" = "3"
Could we do same to p8z77-m_pro? and fix its Win10 ACPI errors?
I did that on CB:39184
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 4: // define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 Still there!
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 88: void mainboard_fill_pei_data(struct pei_data *pei_data)
Guard for bootblock or romstage?
I see the guards are not needed anymore.
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 32: Internal
This entire list has been distilled after more testing. Turns out to be identical to p8z77-m_pro.
Ack
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 12: FIXME Fixed already, I guess?
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 14: rear nit: it's a desktop mainboard, it is assumed that all video ports will be on its rear side
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 5:
Also, please rebase on current master. For some reason Jenkins complains...
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#6).
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
mainboard: New ivybridge board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- SeaBIOS boot - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/8x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 882 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 6: Code-Review+1
(27 comments)
The Asus P8Z77-V LX2 is also in the tree, if you want to use it as a reference
https://review.coreboot.org/c/coreboot/+/38988/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/1//COMMIT_MSG@12 PS1, Line 12: Does not yet boot. Submitting for eyeballs and help.
Any logs?
Ack
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 21: select INTEL_INT15
This option is for the code in mainboard.c, which got removed. […]
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Kconfig:
PS6: Use SPDX here as well
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Kconfig.name:
PS6: SPDX here as well (or drop the copyright notices, we don't usually have them on these files)
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Makefile.inc:
PS6: Also SPDX
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 8: shutdown
shut down
Done
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 8: pc
PC
Done
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 11: cpu
CPU
Done
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/board_info.txt:
https://review.coreboot.org/c/coreboot/+/38988/4/src/mainboard/asus/p8z77-m/... PS4, Line 6: Flashrom support: ?
Yes, bitbanging SPI is a bit slow. […]
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/cmos.default:
PS6: This should be SPDX
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/cmos.layout:
PS6: SPDX here as well
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/devicetree.cb:
PS6: SPDX here as well
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 44: device pci 14.0 on end # USB 3.0 Controller I like aligning the "end" words with an extra space on the "on" lines
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 51: device pci 1c.0 on end # PCIe Port #1 What's on each PCIe root port? e.g.:
device pci 1c.5 on end # PCIe Port #6: Realtek RTL8111 GbE NIC
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 98: SATA Controller 1 SATA Controller (AHCI)
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 100: SATA Controller 2 SATA Controller (Legacy)
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 4: // define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0
Still there!
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 25: #include <drivers/intel/gma/acpi/default_brightness_levels.asl> Not needed anymore
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 34: { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ My OCD would appreciate an extra space before the single-digit numbers for alignment purposes
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 59: ARRAY_SIZE(register_values) You can put this inside the loop
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 60: int strictly speaking, size_t
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 68: Doing it this way saves a config state re-entry. Not sure if it's worth the hassle, though
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 113: struct pei_data pd = { I think it's better to set the non-default fields directly:
pei_data->spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 };
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 131: Asus 2203 bios shows XUECA016, but no EC It's a desktop board, these don't use an EC (Embedded Controller)
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 154: /* These comments should start like this:
/* * foo bar ...
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 12: FIXME
Fixed already, I guess?
Done
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 14: rear
nit: it's a desktop mainboard, it is assumed that all video ports will be on its rear side
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#7).
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
mainboard: New ivybridge board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- SeaBIOS boot - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/8x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 944 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... PS7, Line 108: for (i = 0; i < max; i += 2) { braces {} are not necessary for single statement blocks
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 7:
(13 comments)
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 44: device pci 14.0 on end # USB 3.0 Controller
I like aligning the "end" words with an extra space on the "on" lines
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 51: device pci 1c.0 on end # PCIe Port #1
What's on each PCIe root port? e.g.: […]
Ack
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 98: SATA Controller 1
SATA Controller (AHCI)
Ack
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 100: SATA Controller 2
SATA Controller (Legacy)
Ack
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/5/src/mainboard/asus/p8z77-m/... PS5, Line 4: // define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0
Done
Ack
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 34: { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
My OCD would appreciate an extra space before the single-digit numbers for alignment purposes
Not quite in this case. The header is actually labeled USB2_910 on the PCB. I plan on updating to that in the next patch set.
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 59: ARRAY_SIZE(register_values)
You can put this inside the loop
Ack
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 60: int
strictly speaking, size_t
Ack
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 68: Doing it this way saves a config state re-entry.
Not sure if it's worth the hassle, though
If the compiled binary code is shorter; since all pnp_xxx() functions are inlined except {enter,exit}_conf_state, if there is a way to enable serial reliably with this construct, I'd gladly do it.
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 113: struct pei_data pd = {
I think it's better to set the non-default fields directly: […]
Ack
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 131: Asus 2203 bios shows XUECA016, but no EC
It's a desktop board, these don't use an EC (Embedded Controller)
Ack
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 154: /*
These comments should start like this: […]
Ack
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... PS7, Line 108: for (i = 0; i < max; i += 2) {
braces {} are not necessary for single statement blocks
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 7:
(8 comments)
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Kconfig:
PS6:
Use SPDX here as well
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Kconfig.name:
PS6:
SPDX here as well (or drop the copyright notices, we don't usually have them on these files)
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/Makefile.inc:
PS6:
Also SPDX
Done
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/acpi/superio.asl:
PS7: Maybe this should be moved to superio/nuvoton/nct6779d/acpi ?
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/cmos.default:
PS6:
This should be SPDX
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/cmos.layout:
PS6:
SPDX here as well
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/devicetree.cb:
PS6:
SPDX here as well
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 34: { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
Not quite in this case. The header is actually labeled USB2_910 on the PCB. […]
Sorry, I meant the "Port X" at the beginning of the comments:
{ 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: New ivybridge board ASUS P8Z77-M ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG@7 PS7, Line 7: mainboard: New ivybridge board ASUS P8Z77-M Please make it a statement by adding a verb (in imperative mood):
mainboard: Add new Ivy Bridge board ASUS P8Z77-M
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG@13 PS7, Line 13: - SeaBIOS boot What version, and what OS?
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG@18 PS7, Line 18: - Hardware monitoring under Linux What version?
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG@24 PS7, Line 24: - 2ch sound playback, Linux and Windows What versions?
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... PS7, Line 6: Return(Package(){0,0}) Add spaces (`util/autoport/ec_none.go`).
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#8).
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
mainboard: Add new Ivy Bridge board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- SeaBIOS boot - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux 5.4.24 - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/8x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows 10 1903 with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 942 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/8/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/8/src/mainboard/asus/p8z77-m/... PS8, Line 108: for (i = 0; i < max; i += 2) { braces {} are not necessary for single statement blocks
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#9).
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
mainboard: Add new Ivy Bridge board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- SeaBIOS boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/8x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 941 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 10: Code-Review+1
(10 comments)
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 7: select BOARD_ROMSIZE_KB_8192 nit: sort these alphabetically?
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 6: # ----------------------------------------------------------------- : # Status Register A : # ----------------------------------------------------------------- : # Status Register B : # ----------------------------------------------------------------- : # Status Register C : #96 4 r 0 status_c_rsvd : #100 1 r 0 uf_flag : #101 1 r 0 af_flag : #102 1 r 0 pf_flag : #103 1 r 0 irqf_flag : # ----------------------------------------------------------------- : # Status Register D : #104 7 r 0 status_d_rsvd : #111 1 r 0 valid_cmos_ram : # ----------------------------------------------------------------- : # Diagnostic Status Register : #112 8 r 0 diag_rsvd1 We can get rid of this I think
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 21: Series 6 Cougar Point PCH Series 7 Panther Point PCH
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 33: on Please add a 2nd space after the "on" words, so that the "end" words are all aligned
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 38: I think there's mixed tabs/spaces right before the comments
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 40: slots Slots, in plural? There are two PCIe slots, the one closest to the CPU is on `device pci 01.0` and is electrically x16, and the other slot is `device pci 1c.0`, but it's electrically x4 (note how PCIe ports 2, 3 and 4 are disabled)
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 108: for (i = 0; i < max; i += 2) Why not do it like the Asus P8Z77-V LX2 does it?
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 158: .pei_version = PEI_VERSION, : .mchbar = (uintptr_t)DEFAULT_MCHBAR, : .dmibar = (uintptr_t)DEFAULT_DMIBAR, : .epbar = DEFAULT_EPBAR, : .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, : .smbusbar = SMBUS_IO_BASE, : .wdbbar = 0x4000000, : .wdbsize = 0x1000, : .hpet_address = CONFIG_HPET_ADDRESS, : .rcba = (uintptr_t)DEFAULT_RCBABASE, : .pmbase = DEFAULT_PMBASE, : .gpiobase = DEFAULT_GPIOBASE, : .thermalbase = 0xfed08000, Half of these are already set on the `pei_data` struct pointer parameter. If you change this code to update the members of `pei_data` directly, it will be much more concise.
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 217: P8Z77-M Pro Copypasta! 😄
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/gpio.c:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 2: /* This file is part of the coreboot project. */ We got rid of these comments
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 10:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 7: select BOARD_ROMSIZE_KB_8192
nit: sort these alphabetically?
Is same structure for all P8Z77 boards. Gotta sort'em all?
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 34: { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
Sorry, I meant the "Port X" at the beginning of the comments: […]
Done
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 108: for (i = 0; i < max; i += 2)
Why not do it like the Asus P8Z77-V LX2 does it?
Bootblock code space efficiency. Z77-V uses a string of pnp_write_config() which takes 8 bytes for each board-specific SIO writes, LDN changes included; my setup takes 32 bytes plus 2 bytes per write. Z77-M has 31 such writes including serial port enable, this setup would take 94 bytes versus 248 bytes if it does it like Z77-V. nuvoton_enable_serial() gets optimized away because it's not used, saving another 105 bytes. If I convert, the same setup would take 239 more bytes.
Direct pnp_write_config() calls are more concise, if the board needs 5 such config writes or less.
I plan to attempt to use a cut down Linux kernel as payload, so again every byte counts. On that note, I am going to see if there's any chance to cut sandy/ivy CPU bootblock size to 32KiB, since I saw that bootblock code for all 3 P8Z77 boards weigh in at a little over 16KiB, console included. We could save more with LTO.
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 158: .pei_version = PEI_VERSION, : .mchbar = (uintptr_t)DEFAULT_MCHBAR, : .dmibar = (uintptr_t)DEFAULT_DMIBAR, : .epbar = DEFAULT_EPBAR, : .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, : .smbusbar = SMBUS_IO_BASE, : .wdbbar = 0x4000000, : .wdbsize = 0x1000, : .hpet_address = CONFIG_HPET_ADDRESS, : .rcba = (uintptr_t)DEFAULT_RCBABASE, : .pmbase = DEFAULT_PMBASE, : .gpiobase = DEFAULT_GPIOBASE, : .thermalbase = 0xfed08000,
Half of these are already set on the `pei_data` struct pointer parameter. […]
Thanks for the tip. Will be done in next patch set.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 100: int unsigned int
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 108: for (i = 0; i < max; i += 2)
Bootblock code space efficiency. […]
Difficult question how to optimize between code size and readability. Maybe add this as a separate commit, and keep it unmerged, until it’s clear that you need the 239 bytes?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#11).
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
mainboard: Add new Ivy Bridge board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- SeaBIOS boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 899 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/11
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 11: Code-Review+1
(18 comments)
a
https://review.coreboot.org/c/coreboot/+/38988/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/1//COMMIT_MSG@7 PS1, Line 7: New board
Add Sandybridge board Asus P8Z77-M
Done
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG@7 PS7, Line 7: mainboard: New ivybridge board ASUS P8Z77-M
Please make it a statement by adding a verb (in imperative mood): […]
Done
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG@13 PS7, Line 13: - SeaBIOS boot
What version, and what OS?
Done. I expect SeaBIOS version to be the currently-default version.
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG@18 PS7, Line 18: - Hardware monitoring under Linux
What version?
Done (stated above)
https://review.coreboot.org/c/coreboot/+/38988/7//COMMIT_MSG@24 PS7, Line 24: - 2ch sound playback, Linux and Windows
What versions?
Done (stated above)
https://review.coreboot.org/c/coreboot/+/38988/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/11//COMMIT_MSG@7 PS11, Line 7: Ivy nit: this board also supports Sandy Bridge CPUs
https://review.coreboot.org/c/coreboot/+/38988/11//COMMIT_MSG@12 PS11, Line 12: With which CPU did you test this port?
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... PS7, Line 6: Return(Package(){0,0})
Add spaces (`util/autoport/ec_none.go`).
Ack (IMHO, we should auto-format ASL)
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 6: # ----------------------------------------------------------------- : # Status Register A : # ----------------------------------------------------------------- : # Status Register B : # ----------------------------------------------------------------- : # Status Register C : #96 4 r 0 status_c_rsvd : #100 1 r 0 uf_flag : #101 1 r 0 af_flag : #102 1 r 0 pf_flag : #103 1 r 0 irqf_flag : # ----------------------------------------------------------------- : # Status Register D : #104 7 r 0 status_d_rsvd : #111 1 r 0 valid_cmos_ram : # ----------------------------------------------------------------- : # Diagnostic Status Register : #112 8 r 0 diag_rsvd1
We can get rid of this I think
Done
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 21: Series 6 Cougar Point PCH
Series 7 Panther Point PCH
Done
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 33: on
Please add a 2nd space after the "on" words, so that the "end" words are all aligned
Done
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 38:
I think there's mixed tabs/spaces right before the comments
Done
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 40: slots
Slots, in plural? There are two PCIe slots, the one closest to the CPU is on `device pci 01. […]
Done
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 25: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
Not needed anymore
*poke*
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 100: int
unsigned int
*poke*
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 108: for (i = 0; i < max; i += 2)
Difficult question how to optimize between code size and readability. […]
IMHO, it's well-commented code, so I don't mind keeping it like this. I'd add the rationale as a comment though. (See current patchset)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 48: static const u8 register_values[] = { I'd strongly recommend adding some comment here explaining this is done to save some bytes. Otherwise, people may be tempted to change this to align it with other boards.
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/gpio.c:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 2: /* This file is part of the coreboot project. */
We got rid of these comments
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/7/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/acpi/superio.asl:
PS7:
Maybe this should be moved to superio/nuvoton/nct6779d/acpi ?
Ack (can be done later)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 11:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 29: config MAX_CPUS : int : default 8 already set in cpu/intel/model_206ax
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 98: # gfx_uma_size (Intel IGP Video RAM size) : 7 0 32M : 7 1 64M : 7 2 96M : 7 3 128M : 7 4 160M : 7 5 192M : 7 6 224M : 7 7 256M : 7 8 288M : 7 9 320M : 7 10 352M : 7 11 384M : 7 12 416M : 7 13 448M : 7 14 480M : 7 15 512M : 7 16 544M : 7 17 576M : 7 18 608M : 7 19 640M : 7 20 672M : 7 21 704M : 7 22 736M : 7 23 768M : 7 24 800M : 7 25 832M : 7 26 864M : 7 27 896M : 7 28 928M : 7 29 960M : 7 30 992M From "Document Number: 326765-005Desktop 3rd Generation Intel®Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®Processor FamilyDatasheet – Volume 2 of 2"
Encodings are as follows: 0h = 0 MB 1h = 32 MB 2h = 64 MB 3h = 96 MB 4h = 128 MB 5h = 160 MB 6h = 192 MB 7h = 224 MB 8h = 256 MB 9h = 288 MB Ah = 320 MB Bh = 352 MB Ch = 384 MB Dh = 416 MB Eh = 448 MB Fh = 480 MB 10h = 512 MB 11h = 1 GB
So the last part is not linear. 1G is not an option on sandybridge btw
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 48: static const u8 register_values[] = {
I'd strongly recommend adding some comment here explaining this is done to save some bytes. Otherwise, people may be tempted to change this to align it with other boards.
I don't think it's worth it to save a few bytes here over using proper code.
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1, nuvoton_enable_serial()
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 164: pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */ has a devicetree option "max_mem_clock_mhz" but it looks like some other boards also set this in C code.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 164: pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */
has a devicetree option "max_mem_clock_mhz" but it looks like some other boards also set this in C c […]
The devicetree option also affects native raminit.
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 165: pei->usb_port_config = { : /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ : { 1, 0, 0x0080 }, : { 1, 0, 0x0080 }, : { 1, 1, 0x0080 }, : { 1, 1, 0x0080 }, : { 1, 2, 0x0080 }, : { 1, 2, 0x0080 }, : { 1, 3, 0x0080 }, : { 1, 3, 0x0080 }, : { 1, 4, 0x0080 }, : { 1, 4, 0x0080 }, : { 1, 6, 0x0080 }, : { 1, 5, 0x0080 }, : { 1, 5, 0x0080 }, : { 1, 6, 0x0080 } : }; I don't think this compiles.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#12).
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
mainboard: Add new board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 893 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/12
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 12:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38988/12/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/12/src/mainboard/asus/p8z77-m... PS12, Line 57: * trailing whitespace
https://review.coreboot.org/c/coreboot/+/38988/12/src/mainboard/asus/p8z77-m... PS12, Line 173: }; trailing whitespace
https://review.coreboot.org/c/coreboot/+/38988/12/src/mainboard/asus/p8z77-m... PS12, Line 226: pei->usb3.preboot_support = usb3_drv; trailing whitespace
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#13).
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
mainboard: Add new board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 893 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/13
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 13:
(10 comments)
https://review.coreboot.org/c/coreboot/+/38988/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/11//COMMIT_MSG@7 PS11, Line 7: Ivy
nit: this board also supports Sandy Bridge CPUs
*wink*
https://review.coreboot.org/c/coreboot/+/38988/11//COMMIT_MSG@12 PS11, Line 12:
With which CPU did you test this port?
Added to commit message.
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 29: config MAX_CPUS : int : default 8
already set in cpu/intel/model_206ax
Done
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 98: # gfx_uma_size (Intel IGP Video RAM size) : 7 0 32M : 7 1 64M : 7 2 96M : 7 3 128M : 7 4 160M : 7 5 192M : 7 6 224M : 7 7 256M : 7 8 288M : 7 9 320M : 7 10 352M : 7 11 384M : 7 12 416M : 7 13 448M : 7 14 480M : 7 15 512M : 7 16 544M : 7 17 576M : 7 18 608M : 7 19 640M : 7 20 672M : 7 21 704M : 7 22 736M : 7 23 768M : 7 24 800M : 7 25 832M : 7 26 864M : 7 27 896M : 7 28 928M : 7 29 960M : 7 30 992M
From "Document Number: 326765-005Desktop 3rd Generation Intel®Core™ Processor Family, Desktop Intel® […]
Intel's doc are hard to believe, with a substantial typo on the same page. Yes, I downloaded that doc today. I'll boot test more next week.
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/6/src/mainboard/asus/p8z77-m/... PS6, Line 25: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
*poke*
Done
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 100: int
unsigned int
Done. But honestly, it doesn't make a difference.
https://review.coreboot.org/c/coreboot/+/38988/10/src/mainboard/asus/p8z77-m... PS10, Line 217: P8Z77-M Pro
Copypasta! 😄
Ack
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 48: static const u8 register_values[] = {
I'd strongly recommend adding some comment here explaining this is done to save some bytes. […]
If an entire comment block doesn't get the message through...
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1,
nuvoton_enable_serial()
See above.
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 165: pei->usb_port_config = { : /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ : { 1, 0, 0x0080 }, : { 1, 0, 0x0080 }, : { 1, 1, 0x0080 }, : { 1, 1, 0x0080 }, : { 1, 2, 0x0080 }, : { 1, 2, 0x0080 }, : { 1, 3, 0x0080 }, : { 1, 3, 0x0080 }, : { 1, 4, 0x0080 }, : { 1, 4, 0x0080 }, : { 1, 6, 0x0080 }, : { 1, 5, 0x0080 }, : { 1, 5, 0x0080 }, : { 1, 6, 0x0080 } : };
I don't think this compiles.
Now it should, that it has been redone.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1,
See above.
No I meant that nuvoton_enable_serial is an existing function that should be called instead reimplementing it here.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 98: # gfx_uma_size (Intel IGP Video RAM size) : 7 0 32M : 7 1 64M : 7 2 96M : 7 3 128M : 7 4 160M : 7 5 192M : 7 6 224M : 7 7 256M : 7 8 288M : 7 9 320M : 7 10 352M : 7 11 384M : 7 12 416M : 7 13 448M : 7 14 480M : 7 15 512M : 7 16 544M : 7 17 576M : 7 18 608M : 7 19 640M : 7 20 672M : 7 21 704M : 7 22 736M : 7 23 768M : 7 24 800M : 7 25 832M : 7 26 864M : 7 27 896M : 7 28 928M : 7 29 960M : 7 30 992M
Intel's doc are hard to believe, with a substantial typo on the same page. […]
Vendor EFI should have an option to choose the stolen graphics memory size, from what I can see it's the same encoding as in the datasheet.
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1,
See above. […]
Another option is to put it behind an `if (CONFIG(CONSOLE_SERIAL))` or similar, if not enabled it shouldn't even end up being compiled in
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1,
Another option is to put it behind an `if (CONFIG(CONSOLE_SERIAL))` or similar, if not enabled it sh […]
I recommend against that. You could have a bootblock with serial console disabled but later stages that have it enabled.
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1,
I recommend against that. […]
Angel: You mean CONFIG(BOOTBLOCK_CONSOLE)? But Arthur has a point. If not here, where else do we still have code to initialize serial console?
Arthur: See my earlier comments with the rationale. There's 105 bytes of savings here.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1,
Angel: You mean CONFIG(BOOTBLOCK_CONSOLE)? But Arthur has a point. […]
Oh, I did that already: CB:43582
I didn't do it to slim down the coreboot.rom, but rather to make serialice work without needing to filter Super I/O configuration cycles. Since `nuvoton_enable_serial` disables the UART LDN when programming the base address, it kills serialice (where the SUT and a VM communicate through a serial port)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#14).
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
mainboard: Add new board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 898 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/14
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38988/14/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/14/src/mainboard/asus/p8z77-m... PS14, Line 111: /* trailing whitespace
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#15).
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
mainboard: Add new board ASUS P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p8z77-m/Kconfig A src/mainboard/asus/p8z77-m/Kconfig.name A src/mainboard/asus/p8z77-m/Makefile.inc A src/mainboard/asus/p8z77-m/acpi/ec.asl A src/mainboard/asus/p8z77-m/acpi/platform.asl A src/mainboard/asus/p8z77-m/acpi/superio.asl A src/mainboard/asus/p8z77-m/acpi_tables.c A src/mainboard/asus/p8z77-m/board_info.txt A src/mainboard/asus/p8z77-m/cmos.default A src/mainboard/asus/p8z77-m/cmos.layout A src/mainboard/asus/p8z77-m/data.vbt A src/mainboard/asus/p8z77-m/devicetree.cb A src/mainboard/asus/p8z77-m/dsdt.asl A src/mainboard/asus/p8z77-m/early_init.c A src/mainboard/asus/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8z77-m/gpio.c A src/mainboard/asus/p8z77-m/hda_verb.c 17 files changed, 898 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/15
Attention is currently required from: Keith Hui. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new board ASUS P8Z77-M ......................................................................
Patch Set 16: Code-Review+1
(1 comment)
Patchset:
PS16: It’d be nice to get this in.
Attention is currently required from: Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 18:
(9 comments)
This change is ready for review.
Patchset:
PS18:
After https://review.coreboot. […]
Yep. This is the plan. Update to follow.
File src/mainboard/asus/p8z77-m/cmos.default:
https://review.coreboot.org/c/coreboot/+/38988/comment/33ec9c1e_a823a364 PS18, Line 6: Enable
I'd disable NMIs by default.
Done
File src/mainboard/asus/p8z77-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/comment/380657ef_c82da04b PS18, Line 6: register "c1_acpower" = "1" : register "c1_battery" = "1" : register "c2_acpower" = "3" : register "c2_battery" = "3" : register "c3_acpower" = "5" : register "c3_battery" = "5"
These were deduplicated and changed to `acpi_cX`
Ack
File src/mainboard/asus/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/comment/f11fd951_625b7741 PS18, Line 7: 0x02, /* DSDT revision: ACPI 2.0 and up */
ACPI_DSDT_REV_2
Done
File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/comment/0549c5bb_162462cc PS18, Line 69: static const u8 register_values[] = {
Do all of these values need to be programmed so early? If not, I'd program them through the devicetr […]
I was able to move all to devicetree without immediate issues.
https://review.coreboot.org/c/coreboot/+/38988/comment/66f7f295_d0109daa PS18, Line 187: int usb3_mode = 1; : get_option(&usb3_mode, "usb3_mode");
I've changed the option API, this should now be: […]
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/cf9cd4ce_3de6eb25 PS18, Line 201: pei->system_type = 1; /* 0=Mobile, 1=Desktop/Server */
Should already be set automatically by chipset code.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/59075617_3ef56902 PS18, Line 203: 4
sizeof(spdaddr)
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/32c0f22b_5abcd1cd PS18, Line 209: ARRAY_SIZE
This should be `sizeof`
Done
Attention is currently required from: Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons, Arthur Heymans. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 19:
(1 comment)
File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/comment/4a26d1b8_05de925f PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1,
Oh, I did that already: CB:43582 […]
Ack
Attention is currently required from: Patrick Georgi, Martin Roth, Paul Menzel, Arthur Heymans, Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 19: Code-Review+1
(18 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/comment/274c965a_6efa34e2 PS19, Line 9: dumps. nit: Since CB:60006 the commit message line length limit is 72. This part goes past the limit.
https://review.coreboot.org/c/coreboot/+/38988/comment/b67b3273_a49d313c PS19, Line 14: tests nit: Since CB:60006 the commit message line length limit is 72. This part goes past the limit.
https://review.coreboot.org/c/coreboot/+/38988/comment/35eb7c7c_9fcad759 PS19, Line 27: Anything not working or untested?
Patchset:
PS19: Looks pretty good!
File src/mainboard/asus/p8x7x-series/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/38988/comment/04f6b0db_5e06699a PS19, Line 46: select SUPERIO_NUVOTON_NCT6779D
'SUPERIO' may be misspelled - perhaps ''?
*slaps checkpatch*
https://review.coreboot.org/c/coreboot/+/38988/comment/a23d838a_55060575 PS19, Line 47: select USE_NATIVE_RAMINIT If you select this, it's impossible to use MRC.bin with this board, so all the MRC.bin-specific code is useless. It's still possible to use native raminit without this select (`USE_NATIVE_RAMINIT` is user-configurable, it has a Kconfig prompt).
In the commit message you said you've tested MRC.bin, but I imagine this was before converting this board into a variant.
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/38988/comment/a5d06ec4_41416426 PS19, Line 4: #include <southbridge/intel/bd82x6x/nvs.h> Hmmm, this doesn't exist. This file isn't being compiled in, and can be dropped.
https://review.coreboot.org/c/coreboot/+/38988/comment/c10bdf55_019a57ed PS19, Line 8: /* Critical temp: Shut down the PC at 95 degrees C */ : gnvs->tcrt = 95; : : /* Start throttling the CPU at 85 degrees C */ : gnvs->tpsv = 85; These values aren't used anywhere. The entire file can be dropped.
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38988/comment/a0295d40_181a9395 PS19, Line 26: 1 After CB:39828 this should be 2 bits, there's three possible settings for `sata_mode`
https://review.coreboot.org/c/coreboot/+/38988/comment/e5b0368b_ffc9f835 PS19, Line 95: 6 0 AHCI : 6 1 Compatible After CB:39828 this should be expanded accordingly:
6 0 AHCI 6 1 Compatible 6 2 Legacy
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/comment/a0d2ab64_02f895cc PS19, Line 10: /* OEM revision */ autoport adds this comment, but it's not true. I'd remove it.
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/comment/c4504717_3d8e7468 PS19, Line 1: /* SPDX-License-Identifier: GPL-2.0-or-later */ nit: add a blank line before the #includes
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/comment/3e29735e_225d720f PS19, Line 6: device pci 00.0 on end # Host bridge : device pci 01.0 on end # PCIe Bridge for discrete graphics : device pci 02.0 on end # Internal graphics VGA controller Already specified in the devicetree, can be dropped.
https://review.coreboot.org/c/coreboot/+/38988/comment/51889aec_eee386d2 PS19, Line 11: register "pcie_port_coalesce" = "1" Shouldn't be needed, `device pci 1c.0` is enabled.
https://review.coreboot.org/c/coreboot/+/38988/comment/f42b4e3a_ebe2d15a PS19, Line 12: register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII : register "sata_port_map" = "0x3f" : register "spi_lvscc" = "0x2005" : register "spi_uvscc" = "0x2005" : register "superspeed_capable_ports" = "0x0000000f" : register "xhci_overcurrent_mapping" = "0x00000c03" : register "xhci_switchable_ports" = "0x0000000f" # the 4 ports Already specified in the devicetree, can be dropped.
https://review.coreboot.org/c/coreboot/+/38988/comment/764c3238_efcedef9 PS19, Line 20: device pci 14.0 on end # USB 3.0 Controller : device pci 16.0 on end # Management Engine Interface 1 : device pci 16.1 off end # Management Engine Interface 2 : device pci 16.2 off end # Management Engine IDE Redirect : device pci 16.3 off end # Management Engine Keyboard/Text : device pci 1a.0 on end # USB2 EHCI #2 : device pci 1b.0 on end # High Definition Audio controller Already specified in the devicetree, can be dropped.
https://review.coreboot.org/c/coreboot/+/38988/comment/66e2cb8b_b0b34a2f PS19, Line 35: device pci 1d.0 on end # USB2 EHCI #1 : device pci 1e.0 off end # PCI bridge Already specified in the devicetree, can be dropped.
https://review.coreboot.org/c/coreboot/+/38988/comment/3650e02a_702addc8 PS19, Line 99: device pci 1f.2 on end # SATA Controller (AHCI) : device pci 1f.3 on end # SMBus : device pci 1f.5 off end # SATA Controller (Legacy ports 4-5) : device pci 1f.6 off end # Thermal Already specified in the devicetree, can be dropped.
Attention is currently required from: Martin Roth - Personal, Paul Menzel, Arthur Heymans, Keith Hui. Hello build bot (Jenkins), Martin Roth - Personal, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38988
to look at the new patch set (#20).
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
mainboard/asus/p8x7x-series: Add new variant P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Not working:
- PS/2 mouse - 6ch analog audio out - PCI POST card in PCI slot
Untested:
- PS/2 keyboard - Internal USB3 ports - Digital audio out
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com --- M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt A src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default A src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout A src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt A src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c A src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c A src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 11 files changed, 585 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/20
Attention is currently required from: Martin Roth - Personal, Paul Menzel, Arthur Heymans, Keith Hui. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 20:
(4 comments)
File src/mainboard/asus/p8x7x-series/Kconfig.name:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136062): https://review.coreboot.org/c/coreboot/+/38988/comment/dccb3e7a_7887d96a PS20, Line 46: select SUPERIO_NUVOTON_NCT6779D 'SUPERIO' may be misspelled - perhaps ''?
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136062): https://review.coreboot.org/c/coreboot/+/38988/comment/8eb3b84c_fc06ae13 PS20, Line 9: #include <superio/nuvoton/common/nuvoton.h> 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136062): https://review.coreboot.org/c/coreboot/+/38988/comment/487f85ea_37d39c67 PS20, Line 10: #include <superio/nuvoton/nct6779d/nct6779d.h> 'superio' may be misspelled - perhaps ''?
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136062): https://review.coreboot.org/c/coreboot/+/38988/comment/a56c9011_586b962d PS20, Line 18: chip superio/nuvoton/nct6779d 'superio' may be misspelled - perhaps ''?
Attention is currently required from: Martin Roth - Personal, Paul Menzel, Arthur Heymans, Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 20: Code-Review+1
(17 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/comment/3f9fd3d4_315f2fa0 PS19, Line 9: dumps.
nit: Since CB:60006 the commit message line length limit is 72. This part goes past the limit.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/5005f96a_61db09a0 PS19, Line 14: tests
nit: Since CB:60006 the commit message line length limit is 72. This part goes past the limit.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/b1e01dd8_19d9acb2 PS19, Line 27:
Anything not working or untested?
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/comment/ce50e94d_e803cd0c PS20, Line 32: 6ch analog audio out Interesting, what doesn't work?
File src/mainboard/asus/p8x7x-series/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/38988/comment/558a1c1b_aa3b0107 PS19, Line 47: select USE_NATIVE_RAMINIT
If you select this, it's impossible to use MRC.bin with this board, so all the MRC. […]
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/38988/comment/440e27f1_3b13f755 PS19, Line 4: #include <southbridge/intel/bd82x6x/nvs.h>
Hmmm, this doesn't exist. This file isn't being compiled in, and can be dropped.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/bb954b43_5c57d500 PS19, Line 8: /* Critical temp: Shut down the PC at 95 degrees C */ : gnvs->tcrt = 95; : : /* Start throttling the CPU at 85 degrees C */ : gnvs->tpsv = 85;
These values aren't used anywhere. The entire file can be dropped.
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38988/comment/68d6f94b_b9f6e751 PS19, Line 26: 1
After CB:39828 this should be 2 bits, there's three possible settings for `sata_mode`
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/ad92138e_2a0b9836 PS19, Line 95: 6 0 AHCI : 6 1 Compatible
After CB:39828 this should be expanded accordingly: […]
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38988/comment/4f133764_565d347b PS19, Line 10: /* OEM revision */
autoport adds this comment, but it's not true. I'd remove it.
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/comment/cae31609_419c7381 PS19, Line 1: /* SPDX-License-Identifier: GPL-2.0-or-later */
nit: add a blank line before the #includes
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38988/comment/61d05a90_4f89e9f8 PS19, Line 6: device pci 00.0 on end # Host bridge : device pci 01.0 on end # PCIe Bridge for discrete graphics : device pci 02.0 on end # Internal graphics VGA controller
Already specified in the devicetree, can be dropped.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/f2fde4df_6af62935 PS19, Line 11: register "pcie_port_coalesce" = "1"
Shouldn't be needed, `device pci 1c.0` is enabled.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/ca49f8c7_464d48fe PS19, Line 12: register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII : register "sata_port_map" = "0x3f" : register "spi_lvscc" = "0x2005" : register "spi_uvscc" = "0x2005" : register "superspeed_capable_ports" = "0x0000000f" : register "xhci_overcurrent_mapping" = "0x00000c03" : register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
Already specified in the devicetree, can be dropped.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/8100d1e0_b22c6b17 PS19, Line 20: device pci 14.0 on end # USB 3.0 Controller : device pci 16.0 on end # Management Engine Interface 1 : device pci 16.1 off end # Management Engine Interface 2 : device pci 16.2 off end # Management Engine IDE Redirect : device pci 16.3 off end # Management Engine Keyboard/Text : device pci 1a.0 on end # USB2 EHCI #2 : device pci 1b.0 on end # High Definition Audio controller
Already specified in the devicetree, can be dropped.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/5aff8bdf_1d54f0c0 PS19, Line 35: device pci 1d.0 on end # USB2 EHCI #1 : device pci 1e.0 off end # PCI bridge
Already specified in the devicetree, can be dropped.
Done
https://review.coreboot.org/c/coreboot/+/38988/comment/5b10773f_5d676a2c PS19, Line 99: device pci 1f.2 on end # SATA Controller (AHCI) : device pci 1f.3 on end # SMBus : device pci 1f.5 off end # SATA Controller (Legacy ports 4-5) : device pci 1f.6 off end # Thermal
Already specified in the devicetree, can be dropped.
Done
Attention is currently required from: Martin Roth - Personal, Paul Menzel, Angel Pons, Arthur Heymans. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 20:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/comment/77322339_f5f1da66 PS20, Line 32: 6ch analog audio out
Interesting, what doesn't work?
Since you asked, I tested again. I did get a control to "switch" it into 4ch and 6ch analog modes in alsamixer. I then used speaker-test from alsa-utils with two set of wired speakers connected per mainboard manual (front to lime, rear to blue). I get sound out of both set of speakers with front channels, effectively no sound from rear channels, and absolute silence from LFE. Totally doesn't sound right.
Attention is currently required from: Martin Roth - Personal, Paul Menzel, Angel Pons, Arthur Heymans, Keith Hui. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 20:
(1 comment)
Patchset:
PS20: Just noticed: There is the topic new-mainboard for such commits.
Attention is currently required from: Martin Roth - Personal, Paul Menzel, Arthur Heymans, Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 20:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/comment/04a97940_97fe9b48 PS20, Line 32: 6ch analog audio out
Since you asked, I tested again. […]
Hmmm, from pictures I can see that the board only has three audio jacks: blue would be line in, green would be line out, and pink would be microphone in.
Attention is currently required from: Martin L. Roth, Paul Menzel, Angel Pons, Arthur Heymans. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 20:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/comment/129c0d61_b3c6958e PS20, Line 32: 6ch analog audio out
Hmmm, from pictures I can see that the board only has three audio jacks: blue would be line in, gree […]
True, but they can take on multiple roles. In an analog 5.1 setup, all 3 jacks would be outputs of some kind. How they are supposed to work is documented in the manual.
Patchset:
PS20: Ping?
Attention is currently required from: Martin L. Roth, Paul Menzel, Arthur Heymans, Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
Patch Set 20: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38988/comment/39985a2e_70fb9008 PS20, Line 32: 6ch analog audio out
True, but they can take on multiple roles. In an analog 5. […]
Hmmm, I'm pretty sure you'd need to program the codec jacks differently for this to work.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard/asus/p8x7x-series: Add new variant P8Z77-M ......................................................................
mainboard/asus/p8x7x-series: Add new variant P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps.
Working:
- Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows
Not working:
- PS/2 mouse - 6ch analog audio out - PCI POST card in PCI slot
Untested:
- PS/2 keyboard - Internal USB3 ports - Digital audio out
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38988 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt A src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default A src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout A src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt A src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c A src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c A src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 11 files changed, 585 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index 4ecb4b4..7968345 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -24,6 +24,7 @@ default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 default "p8z77-v" if BOARD_ASUS_P8Z77_V + default "p8z77-m" if BOARD_ASUS_P8Z77_M
config MAINBOARD_PART_NUMBER default "P8C WS" if BOARD_ASUS_P8C_WS @@ -31,6 +32,7 @@ default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 default "P8Z77-V" if BOARD_ASUS_P8Z77_V + default "P8Z77-M" if BOARD_ASUS_P8Z77_M
config OVERRIDE_DEVICETREE default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name index b4d8948..822f5d4 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -38,3 +38,9 @@ select MAINBOARD_USES_IFD_GBE_REGION select SUPERIO_NUVOTON_NCT6779D select USE_NATIVE_RAMINIT + +config BOARD_ASUS_P8Z77_M + bool "P8Z77-M" + select BOARD_ASUS_P8X7X_SERIES + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_NUVOTON_NCT6779D diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt new file mode 100644 index 0000000..9677474 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P8Z77M/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default new file mode 100644 index 0000000..3cc854d --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +gfx_uma_size=224M +nmi=Disable +sata_mode=AHCI +#usb3_xxxx options are only used with MRC blob, ignored otherwise +usb3_mode=Enable +usb3_drv=Enable +usb3_streams=Enable diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout new file mode 100644 index 0000000..3053b8d --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout @@ -0,0 +1,136 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: southbridge + +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +408 1 e 1 nmi + +409 2 e 5 power_on_after_fail +411 2 e 6 sata_mode + +# ----------------------------------------------------------------- +# coreboot config options: northbridge + +# gfx_uma_size +# Quantity of shared video memory the IGP can use +# +416 5 e 7 gfx_uma_size + +# ----------------------------------------------------------------- +# coreboot config options: usb3 + +# usb3_mode +# Controls how the motherboard's USB3 ports act at boot time +421 2 e 8 usb3_mode + +# usb3_drv +# Load (or not) pre-OS xHCI USB3 bios driver +# +423 1 e 1 usb3_drv + +# usb3_streams +# Streams can provide more speed (as they can use 64Kb packets), +# but they might cause incompatibilities with some devices. +# +424 1 e 1 usb3_streams + +# ----------------------------------------------------------------- +# Sandy/Ivy Bridge MRC Scrambler Seed values +# note: MUST NOT be covered by checksum! +464 32 r 0 mrc_scrambler_seed +496 32 r 0 mrc_scrambler_seed_s3 +528 16 r 0 mrc_scrambler_seed_chk + +# ----------------------------------------------------------------- +# coreboot config options: check sums +544 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +# power_on_after_fail +5 0 Disable +5 1 Enable +5 2 Keep + +# sata_mode +6 0 AHCI +6 1 Compatible +6 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 1024M + +# usb3_mode +# Disable = Use the port always as USB 2.0 for compatibility +# Enable = Use the port always as USB 3.0 for speed +# Auto = Initialize the port as USB 2.0, until the OS loads +# xHCI USB 3.0 driver +# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver +# and the computer is reset, keep the USB 3.0 mode. +# +8 0 Disable +8 1 Enable +8 2 Auto +8 3 SmartAuto + +# ----------------------------------------------------------------- +# <startBit[must be byte-aligned]> <endBit[must be byte aligned]> +# <bit where to start storing checksum[must be 16bits-aligned]> +checksums + +checksum 392 431 544 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt new file mode 100644 index 0000000..26ab42d --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c new file mode 100644 index 0000000..dfcdd23 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/pei_data.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#include <option.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* {enable, current, oc_pin} */ + {1, 2, 0}, /* Port 0: USB3 front internal header, top */ + {1, 2, 0}, /* Port 1: USB3 front internal header, bottom */ + {1, 2, 1}, /* Port 2: USB3 rear, top */ + {1, 2, 1}, /* Port 3: USB3 rear, bottom */ + {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ + {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ + {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ + {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ + {1, 2, 4}, /* Port 8: USB2 internal header USB910, top */ + {1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */ + {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ + {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ + {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ + {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* + * TODO: Put PCIe root port 7 (00:1c.6) into subtractive decode and have it accept I/O + * cycles. This should allow a POST card in the PCI slot, connected via an ASM1083 + * bridge to this port, to receive POST codes. + */ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} + +void mainboard_fill_pei_data(struct pei_data *pei) +{ + uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */ + uint16_t usbcfg[16][3] = { + /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ + {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, + {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, + {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} + }; + + memcpy(pei->spd_addresses, &spdaddr, sizeof(spdaddr)); + + pei->gbe_enable = 0; /* Board uses no Intel GbE but a RTL8111F */ + pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */ + + memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg)); + + /* ASUS P8Z77-M manual lists some supported DIMMs down to 1.25v */ + pei->ddr3lv_support = 1; + /* + * PCIe 3.0 support. As we use Ivy Bridge, let's enable it, + * but might cause some system instability! + */ + pei->pcie_init = 1; + /* + * 4 bit switch mask. 0=not switchable, 1=switchable + * Means once it's loaded the OS, it can swap ports + * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf + */ + pei->usb3.hs_port_switch_mask = 0xf; + /* + * USB 3 mode settings. + * These are obtained from option table then bit masked to keep within range. + */ + /* + * 0 = Disable: work always as USB 2.0(ehci) + * 1 = Enable: work always as USB 3.0(xhci) + * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver + * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver + * and reboots, it will keep the USB3.0 speed + */ + pei->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3; + /* 1=Load xHCI pre-OS drv */ + pei->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1; + /* + * 0=Don't use xHCI streams for better compatibility + * 1=use xHCI streams for better speed + */ + pei->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1; +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads new file mode 100644 index 0000000..1bf8323 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D port + HDMI3, -- HDMI port + Analog, -- VGA port + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c new file mode 100644 index 0000000..c1012e3 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c new file mode 100644 index 0000000..5830331 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x104384a8, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384a8), + AZALIA_PIN_CFG(0, 0x11, 0x90430130), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4016c629), + AZALIA_PIN_CFG(0, 0x1e, 0x01446140), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb new file mode 100644 index 0000000..9659ed1 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -0,0 +1,81 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1043 0x84ca inherit + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x000c0291" + + device pci 1c.0 on end # PCIe Port #1 (PCIe x4 slot) + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 (PCIe x1 slot) + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 (PCI slot via ASM1083) + device pci 1c.7 off end # PCIe Port #8 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 # COM1 address + irq 0x70 = 4 + # Below are global config settings to replicate OEM + drq 0x26 = 0x10 # Before accessing CR10/11/13/14, CR26:4 must be set to 1 + drq 0x13 = 0xff # IRQs 0-15 active low + drq 0x14 = 0xff + drq 0x1a = 0x02 + drq 0x1b = 0x60 + drq 0x2c = 0x00 # GP27, 3VSBSW#, No TSI + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS2 KBC + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + drq 0xf0 = 0x82 # KBC 12Mhz/A20 speed/sw KBRST + drq 0x2a = 0x48 # UART A, PS/2 mouse, PS/2 keyboard + drq 0x22 = 0xd7 # Power down UART B and LPT + end + device pnp 2e.6 off end # CIR + device pnp 2e.8 on # WDT1 + drq 0xe0 = 0x7f # GP07 output + drq 0xe1 = 0x80 # GP07 high + end + device pnp 2e.a on # ACPI + drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility + drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME + end + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0x290 # HWM address + io 0x62 = 0 # SB-TSI address (not used) + drq 0xe4 = 0xf9 # GP50, GP52, PWROK# + drq 0xf0 = 0x3e # Enable all fan input debouncers + end + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f on # GPIO PP/OD select + drq 0xe4 = 0xfc # GP50,GP51 PP + drq 0xe6 = 0x7f # GP7x OD + end + device pnp 2e.9 off end # GPIO 8 + device pnp 2e.308 on end # GPIO by I/O + device pnp 2e.108 on end # GPIO 0 + device pnp 2e.109 on end # GPIO 1 + device pnp 2e.209 on # GPIO 2 + drq 0xe0 = 0xbf # GP26 output + drq 0xe1 = 0xc0 # GP26 high + end + device pnp 2e.309 off end # GPIO 3 + device pnp 2e.409 off end # GPIO 4 + device pnp 2e.509 on # GPIO 5 + drq 0xf4 = 0xfc # GP50,GP51 output + drq 0xf5 = 0xc4 # GP50,GP51 low + end + device pnp 2e.609 off end # GPIO 6 + device pnp 2e.709 off end # GPIO 7 + end + end + end + end +end
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