Attention is currently required from: Martin Roth - Personal, Paul Menzel, Arthur Heymans, Keith Hui.
Patch set 20:Code-Review +1
17 comments:
Commit Message:
Patch Set #19, Line 9: dumps.
nit: Since CB:60006 the commit message line length limit is 72. This part goes past the limit.
Done
Patch Set #19, Line 14: tests
nit: Since CB:60006 the commit message line length limit is 72. This part goes past the limit.
Done
Anything not working or untested?
Done
Commit Message:
Patch Set #20, Line 32: 6ch analog audio out
Interesting, what doesn't work?
File src/mainboard/asus/p8x7x-series/Kconfig.name:
Patch Set #19, Line 47: select USE_NATIVE_RAMINIT
If you select this, it's impossible to use MRC.bin with this board, so all the MRC. […]
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/acpi_tables.c:
Patch Set #19, Line 4: #include <southbridge/intel/bd82x6x/nvs.h>
Hmmm, this doesn't exist. This file isn't being compiled in, and can be dropped.
Done
/* Critical temp: Shut down the PC at 95 degrees C */
gnvs->tcrt = 95;
/* Start throttling the CPU at 85 degrees C */
gnvs->tpsv = 85;
These values aren't used anywhere. The entire file can be dropped.
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout:
After CB:39828 this should be 2 bits, there's three possible settings for `sata_mode`
Done
6 0 AHCI
6 1 Compatible
After CB:39828 this should be expanded accordingly: […]
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/dsdt.asl:
Patch Set #19, Line 10: /* OEM revision */
autoport adds this comment, but it's not true. I'd remove it.
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c:
Patch Set #19, Line 1: /* SPDX-License-Identifier: GPL-2.0-or-later */
nit: add a blank line before the #includes
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb:
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on end # Internal graphics VGA controller
Already specified in the devicetree, can be dropped.
Done
Patch Set #19, Line 11: register "pcie_port_coalesce" = "1"
Shouldn't be needed, `device pci 1c.0` is enabled.
Done
register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII
register "sata_port_map" = "0x3f"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
Already specified in the devicetree, can be dropped.
Done
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE Redirect
device pci 16.3 off end # Management Engine Keyboard/Text
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio controller
Already specified in the devicetree, can be dropped.
Done
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
Already specified in the devicetree, can be dropped.
Done
device pci 1f.2 on end # SATA Controller (AHCI)
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller (Legacy ports 4-5)
device pci 1f.6 off end # Thermal
Already specified in the devicetree, can be dropped.
Done
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