Change in coreboot[master]: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/...
Matt Parnell has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/ec/hp/it8987e/Kconfig A src/ec/hp/it8987e/Makefile.inc A src/ec/hp/it8987e/acpi/ac.asl A src/ec/hp/it8987e/acpi/battery.asl A src/ec/hp/it8987e/acpi/ec.asl A src/ec/hp/it8987e/acpi/kb.asl A src/ec/hp/it8987e/acpi/superio.asl A src/ec/hp/it8987e/acpi/tpm.asl A src/ec/hp/it8987e/chip.h A src/ec/hp/it8987e/ec.c A src/ec/hp/it8987e/ec.h A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 31 files changed, 5,065 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/1
diff --git a/src/ec/hp/it8987e/Kconfig b/src/ec/hp/it8987e/Kconfig new file mode 100644 index 0000000..54f7896 --- /dev/null +++ b/src/ec/hp/it8987e/Kconfig @@ -0,0 +1,4 @@ +config EC_HP_IT8987E + bool + help + Interface to QUANTA/HP IT8987E Embedded Controller. diff --git a/src/ec/hp/it8987e/Makefile.inc b/src/ec/hp/it8987e/Makefile.inc new file mode 100644 index 0000000..db11205 --- /dev/null +++ b/src/ec/hp/it8987e/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_EC_HP_IT8987E),y) + +romstage-y += ec.c +ramstage-y += ec.c +smm-y += ec.c +smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/hp/it8987e/acpi/ac.asl b/src/ec/hp/it8987e/acpi/ac.asl new file mode 100644 index 0000000..bb4b4fe --- /dev/null +++ b/src/ec/hp/it8987e/acpi/ac.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { _SB }) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + Local0 = ^^PCI0.LPCB.EC0.SW2S + } + Else + { + Local0 = One + } + + Return (Local0) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/src/ec/hp/it8987e/acpi/battery.asl b/src/ec/hp/it8987e/acpi/battery.asl new file mode 100644 index 0000000..75efd92 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/battery.asl @@ -0,0 +1,252 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +Device (BAT0) +{ + Name (FRST, One) + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0xFFFFFFFF, + 0xFA, + 0x96, + 0x0A, + 0x19, + "BAT0", + " ", + " ", + " " + }) + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x2710 + }) + Name (BAST, Zero) + Name (B1ST, 0x0F) + Name (B1WT, Zero) + Name (FABL, 0xFFFFFFFF) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + B1ST = 0x1F + } + Else + { + B1ST = 0x0F + } + } + Else + { + B1ST = 0x0F + } + + Return (B1ST) /* _SB_.BAT0.B1ST */ + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + UPBI () + } + Else + { + IVBI () + } + } + Else + { + IVBI () + } + + Return (PBIF) /* _SB_.BAT0.PBIF */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + UPBS () + } + Else + { + IVBS () + } + } + Else + { + IVBS () + } + + Return (PBST) /* _SB_.BAT0.PBST */ + } + + Method (UPBI, 0, NotSerialized) + { + Local5 = ^^PCI0.LPCB.EC0.BFCC /* _SB_.PCI0.LPCB.EC0_.BFCC */ + If ((Local5 && !(Local5 & 0x8000))) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + PBIF [One] = Local5 + PBIF [0x02] = Local5 + Local2 = (Local5 / 0x64) + Local2 += One + If ((^^PCI0.LPCB.EC0.BADC < 0x0C80)) + { + Local4 = (Local2 * 0x0E) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x09) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0B) + } + ElseIf ((SMA4 == One)) + { + Local4 = (Local2 * 0x0A) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x05) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x08) + } + Else + { + Local4 = (Local2 * 0x0C) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x07) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0A) + } + + FABL = (Local4 + 0x02) + } + + Local0 = ^^PCI0.LPCB.EC0.BVLB /* _SB_.PCI0.LPCB.EC0_.BVLB */ + Local1 = ^^PCI0.LPCB.EC0.BVHB /* _SB_.PCI0.LPCB.EC0_.BVHB */ + Local1 <<= 0x08 + Local0 |= Local1 + PBIF [0x04] = Local0 + Sleep (0x32) + PBIF [0x0B] = "LION" + PBIF [0x09] = "Primary" + UPUM () + PBIF [Zero] = One + } + + Method (UPUM, 0, NotSerialized) + { + Local0 = Buffer (0x0A) + { + /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00 // .. + } + Local6 = Buffer (0x05) + { + 0x36, 0x35, 0x35, 0x33, 0x35 // 65535 + } + Local7 = Buffer (0x05) + { + 0x31, 0x32, 0x33, 0x32, 0x31 // 12321 + } + PBIF [0x0C] = "HP" + } + + Method (UPBS, 0, NotSerialized) + { + If ((BRTM == One)) + { + Local0 = ^^PCI0.LPCB.EC0.MCUR /* _SB_.PCI0.LPCB.EC0_.MCUR */ + If ((Local0 & 0x8000)) + { + If ((Local0 == 0xFFFF)) + { + PBST [One] = 0xFFFFFFFF + } + Else + { + Local1 = ~Local0 + Local1++ + Local3 = (Local1 & 0xFFFF) + PBST [One] = Local3 + } + } + Else + { + PBST [One] = Local0 + } + } + Else + { + PBST [One] = 0xFFFFFFFF + } + + Local5 = ^^PCI0.LPCB.EC0.MBRM /* _SB_.PCI0.LPCB.EC0_.MBRM */ + If (!(Local5 & 0x8000)) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + If ((Local5 != DerefOf (PBST [0x02]))) + { + PBST [0x02] = Local5 + } + } + + If ((!^^PCI0.LPCB.EC0.SW2S && (^^PCI0.LPCB.EC0.BACR == One))) + { + PBST [0x02] = FABL /* _SB_.BAT0.FABL */ + } + + PBST [0x03] = ^^PCI0.LPCB.EC0.MBCV /* _SB_.PCI0.LPCB.EC0_.MBCV */ + PBST [Zero] = ^^PCI0.LPCB.EC0.MBST /* _SB_.PCI0.LPCB.EC0_.MBST */ + } + + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = "Bad" + PBIF [0x0A] = "Bad" + PBIF [0x0B] = "Bad" + PBIF [0x0C] = "Bad" + } + + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } +} diff --git a/src/ec/hp/it8987e/acpi/ec.asl b/src/ec/hp/it8987e/acpi/ec.asl new file mode 100644 index 0000000..0692ced --- /dev/null +++ b/src/ec/hp/it8987e/acpi/ec.asl @@ -0,0 +1,1201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (PHOT, One) + Name (ECAV, Zero) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (BFFR, ResourceTemplate () + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + Return (BFFR) /* _SB_.PCI0.LPCB.EC0_._CRS.BFFR */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + ^^^GFX0.CLID = 0x03 + Return (0x0F) + } + + OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + SMPR, 8, + SMST, 8, + SMAD, 8, + SMCM, 8, + SMD0, 256, + BCNT, 8, + SMAA, 8, + Offset (0x40), + SW2S, 1, + , 2, + ACCC, 1, + TRPM, 1, + Offset (0x41), + W7OS, 1, + QWOS, 1, + , 1, + SUSE, 1, + RFLG, 1, + Offset (0x43), + , 1, + , 1, + ACPS, 1, + ACKY, 1, + GFXT, 1, + Offset (0x44), + , 7, + DSMB, 1, + Offset (0x47), + TNT2, 8, + TNT3, 8, + Offset (0x4C), + STRM, 8, + Offset (0x4E), + LIDE, 1, + Offset (0x4F), + ACID, 8, + , 2, + PTHM, 1, + , 1, + BSEV, 1, + DPTL, 1, + Offset (0x52), + ECLS, 1, + Offset (0x55), + EC45, 8, + Offset (0x58), + RTMP, 8, + TNT1, 8, + Offset (0x5F), + , 1, + Offset (0x61), + SHPM, 8, + Offset (0x67), + , 1, + , 1, + GC6R, 1, + IGC6, 1, + , 2, + PVSE, 1, + PVSS, 1, + , 3, + PLGS, 1, + , 3, + TPDF, 1, + , 4, + BCTF, 1, + BMNF, 1, + BTVD, 1, + BF10, 1, + Offset (0x6C), + GWKR, 8, + Offset (0x70), + BADC, 16, + BFCC, 16, + BVLB, 8, + BVHB, 8, + BDVO, 8, + Offset (0x7F), + ECTB, 1, + Offset (0x82), + MBST, 8, + MCUR, 16, + MBRM, 16, + MBCV, 16, + Offset (0x8B), + LEDM, 3, + Offset (0x8D), + , 5, + MBFC, 1, + Offset (0x92), + SPSV, 8, + Offset (0x94), + GSSU, 1, + GSMS, 1, + Offset (0x95), + MMST, 4, + DMST, 4, + Offset (0xA0), + QBHK, 8, + Offset (0xA2), + QBBB, 8, + Offset (0xA4), + MBTS, 1, + , 6, + BACR, 1, + Offset (0xA6), + MBDC, 8, + Offset (0xA8), + ENWD, 1, + TMPR, 1, + Offset (0xAA), + , 1, + SMSZ, 1, + , 5, + RCDS, 1, + Offset (0xAD), + SADP, 8, + Offset (0xB2), + RPM1, 8, + RPM2, 8, + Offset (0xBA), + CLOW, 8, + CMAX, 8, + Offset (0xC1), + DPPC, 8, + Offset (0xC6), + , 1, + CVTS, 1, + Offset (0xCE), + NVDX, 8, + ECDX, 8, + EBPL, 1, + Offset (0xD2), + , 7, + DLYE, 1, + Offset (0xD4), + PSHD, 8, + PSLD, 8, + DBPL, 8, + STSP, 8, + Offset (0xDA), + PSIN, 8, + PSKB, 1, + PSTP, 1, + , 1, + PWOL, 1, + RTCE, 1, + Offset (0xE0), + DLYT, 8, + DLY2, 8, + Offset (0xE6), + SFHK, 8, + Offset (0xE9), + DTMT, 8, + PL12, 8, + ETMT, 8, + Offset (0xF2), + ZPDD, 1, + , 6, + ENPA, 1, + Offset (0xF4), + SFAN, 8, + Offset (0xF9), + , 7, + FTHM, 1 + } + + Name (ECOK, Zero) + Name (BATO, Zero) + Name (BATN, Zero) + Name (BATF, 0xC0) + Name (TMEE, Zero) + Name (TMDE, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (((Arg0 == 0x03) && (Arg1 == One))) + { + ECOK = One + GBAS () + ECMI () + } + } + + Method (_GPE, 0, NotSerialized) // _GPE: General Purpose Events + { + Local0 = GGPE (0x02020017) + Return (Local0) + } + + Method (BPOL, 1, NotSerialized) + { + DBPL = Arg0 + EBPL = One + } + + Method (BPOM, 0, NotSerialized) + { + DBPL = Zero + EBPL = Zero + } + + Method (GBAS, 0, NotSerialized) + { + If ((ECOK == One)) + { + BATF = Zero + Local0 = MBTS /* _SB_.PCI0.LPCB.EC0_.MBTS */ + Local1 = SW2S /* _SB_.PCI0.LPCB.EC0_.SW2S */ + Local0 <<= 0x06 + Local1 <<= One + If (((BATO & 0x40) != Local0)) + { + BATF |= 0x40 + } + + If (((BATO & 0x02) != Local1)) + { + BATF |= 0x02 + } + + BATO = Zero + BATO = (Local0 | Local1) + } + } + + Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + BPOM () + GBAS () + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + Notify (ADP1, 0x80) // Status Change + } + + Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "_Q0D : Switch Display (Fn+F4)" + ^^^GFX0.GHDS (Zero) + Sleep (0xC8) + } + + Method (_Q10, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + Method (_Q11, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + Method (_Q15, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "!!! Wireless Button pressed !!!" + If ((OSYS >= 0x07DC)) + { + Notify (WLBT, 0x80) // Status Change + } + Else + { + If (BNLS) + { + BNLS = Zero + Local0 = One + } + Else + { + BNLS = One + Local0 = Zero + } + + If ((^^^^WMID.WMIF == One)) + { + If (((WWLS == One) & (WLDS == One))) + { + If (One) + { + SGOV (0x02070002, Local0) + } + Else + { + SGOV (0x01090008, Local0) + } + } + + If (((WBTS == One) & (BTDS == One))) + { + If (One) + { + SGOV (0x0203000C, Local0) + } + Else + { + SGOV (0x0103000C, Local0) + } + } + } + Else + { + If ((WLDS == One)) + { + If (One) + { + SGOV (0x02070002, Local0) + } + Else + { + SGOV (0x01090008, Local0) + } + } + + If ((BTDS == One)) + { + If (One) + { + SGOV (0x0203000C, Local0) + } + Else + { + SGOV (0x0103000C, Local0) + } + } + } + } + } + + Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + GBAS () + If ((0x40 & BATF)) + { + Notify (BAT0, 0x81) // Information Change + } + + Notify (BAT0, 0x80) // Status Change + If ((0x02 & BATF)) + { + Notify (ADP1, 0x80) // Status Change + PWRS = SW2S /* _SB_.PCI0.LPCB.EC0_.SW2S */ + If (SW2S) + { + ^^^^WMID.GWEV (0x03, Zero) + } + } + + PNOT () + } + } + + Method (_Q21, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((BCTF || BMNF)) + { + ^^^^WMID.GWEV (0x12, One) + } + } + } + + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + BACR = Zero + Notify (BAT0, 0x80) // Status Change + } + } + + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + Notify (BAT0, 0x80) // Status Change + } + + Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local0 = ^^RTC.RTMN /* _SB_.PCI0.LPCB.RTC_.RTMN */ + FromBCD (Local0, Local0) + Local1 = ^^RTC.RTHR /* _SB_.PCI0.LPCB.RTC_.RTHR */ + FromBCD (Local1, Local1) + Local2 = ^^RTC.RTDY /* _SB_.PCI0.LPCB.RTC_.RTDY */ + Local3 = ^^RTC.RTSE /* _SB_.PCI0.LPCB.RTC_.RTSE */ + FromBCD (Local3, Local3) + If ((ECOK == One)) + { + PSIN = 0xFF + Sleep (One) + PSLD = Local0 + PSHD = Local1 + PSIN = 0x1C + Sleep (One) + PSLD = Local2 + PSHD = Local3 + PSIN = 0x1D + } + } + + Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((ENWD == One)) + { + TMPR = One + } + } + } + + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((CVTS == One)) + { + Local0 = 0x03 + Local0 <<= 0x10 + Local0 |= 0x03 + ^^^^WFTE.WMDE (Zero, One, Local0) + Notify (VBPA, 0xCC) // Hardware-Specific + } + + If ((CVTS == Zero)) + { + Local0 = 0x02 + Local0 <<= 0x10 + Local0 |= 0x02 + ^^^^WFTE.WMDE (Zero, One, Local0) + Notify (VBPA, 0xCD) // Hardware-Specific + } + } + } + + Method (_Q49, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((PVSS == One)) + { + If ((PVSE == One)) + { + ^^^^WMID.GWEV (0x14, 0xFE) + } + Else + { + ^^^^WMID.GWEV (0x14, 0xFF) + } + } + } + } + + Method (_Q4D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x00020001, Zero) + } + + Method (_Q6F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x04, Zero) + } + + Method (_Q70, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + SGOV (0x0204000A, Zero) + } + + Method (_Q71, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + SGOV (0x0204000A, One) + } + + Method (_Q80, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Notify (_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q82, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Debug = "_Q82 : Temperature reachs for Turbo Mode OFF" + TMDE = One + Notify (_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q83, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Debug = "_Q83 : Temperature reachs for Turbo Mode ON" + TMEE = One + Notify (_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == One)) + { + PHOT = 0x02 + } + } + + Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (B0D4, 0x90) // Device-Specific + } + + Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == One)) + { + PHOT = 0x03 + } + } + + Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If (LIDE) + { + Debug = "_Q8A : LID Switch Event" + LIDE = Zero + Sleep (0x14) + Notify (LID0, 0x80) // Status Change + } + } + } + + Method (_Q8E, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (CondRefOf (_PR.PR00._PPC)) + { + Local0 = _PR.PR00._PPC () + } + + Local1 = (MPPP - One) + If ((Local0 < Local1)) + { + Local0++ + CPUS (Local0) + } + + CLOW = Local0 + } + + Method (_Q8F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (CondRefOf (_PR.PR00._PPC)) + { + Local0 = _PR.PR00._PPC () + } + + If (Local0) + { + Local0-- + CPUS (Local0) + } + + CLOW = Local0 + } + + Method (_Q99, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QA0, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QA1, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QE4, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local1 = Zero + Local0 = PKPS /* \PKPS */ + If ((Local0 > 0x80)) + { + Local0 -= 0x80 + While ((Local0 > 0x06)) + { + Local0 -= 0x10 + Local1 += 0x06 + } + + Local1 += Local0 + If (((Local1 >= 0x07) & (Local1 <= 0x0C))) + { + Local1 += 0x12 + } + ElseIf (((Local1 >= 0x0D) & (Local1 <= 0x12))) + { + Local1 += 0x06 + } + ElseIf (((Local1 >= 0x13) & (Local1 <= 0x18))) + { + Local1 -= 0x0C + } + ElseIf (((Local1 >= 0x19) & (Local1 <= 0x1E))) + { + Local1 -= 0x0C + } + + Stall (0x05) + Local0 = Zero + Local3 = OFDA /* \OFDA */ + While ((Local1 > One)) + { + Local2 = DerefOf (Local3 [Local0]) + Local0 += Local2 + Local1 -= One + } + + Stall (0x0F) + Local1 = DerefOf (Local3 [Local0]) + Local2 = Zero + Stall (0x0F) + Name (KPFT, Buffer (0xA0){}) + While ((Local2 < 0xA0)) + { + If ((Local1 > Zero)) + { + KPFT [Local2] = DerefOf (Local3 [Local0]) + Local0++ + Local1 -= One + } + Else + { + KPFT [Local2] = Zero + } + + Local2++ + Stall (0x05) + } + + PKMC = KPFT /* _SB_.PCI0.LPCB.EC0_._QE4.KPFT */ + PKWD = One + } + } + + Method (_QE5, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x12, PKPS) + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + SMW0, 16 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + SMB0, 8 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD0, 64 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD1, 128 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD2, 192 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD3, 256 + } + + Mutex (MUT0, 0x00) + Mutex (MUT1, 0x00) + Mutex (MUT2, 0x00) + Method (SMRD, 4, NotSerialized) + { + If (!ECOK) + { + Return (0xFF) + } + + If ((Arg0 != 0x07)) + { + If ((Arg0 != 0x09)) + { + If ((Arg0 != 0x0B)) + { + If ((Arg0 != 0x47)) + { + If ((Arg0 != 0xC7)) + { + Return (0x19) + } + } + } + } + } + + Acquire (MUT0, 0xFFFF) + Local0 = 0x04 + While ((Local0 > One)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + While (!Local1 = (SMST & 0xBF)) + { + Sleep (0x02) + Local3++ + If ((Local3 == 0x32)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + } + } + + If ((Local1 == 0x80)) + { + Local0 = Zero + } + Else + { + Local0-- + } + } + + If (Local0) + { + Local0 = (Local1 & 0x1F) + } + Else + { + If ((Arg0 == 0x07)) + { + Arg3 = SMB0 /* _SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0x47)) + { + Arg3 = SMB0 /* _SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0xC7)) + { + Arg3 = SMB0 /* _SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0x09)) + { + Arg3 = SMW0 /* _SB_.PCI0.LPCB.EC0_.SMW0 */ + } + + If ((Arg0 == 0x0B)) + { + Local3 = BCNT /* _SB_.PCI0.LPCB.EC0_.BCNT */ + Local2 = 0x20 + If ((Local3 > Local2)) + { + Local3 = Local2 + } + + If ((Local3 < 0x11)) + { + Local2 = FLD1 /* _SB_.PCI0.LPCB.EC0_.FLD1 */ + } + ElseIf ((Local3 < 0x19)) + { + Local2 = FLD2 /* _SB_.PCI0.LPCB.EC0_.FLD2 */ + } + Else + { + Local2 = FLD3 /* _SB_.PCI0.LPCB.EC0_.FLD3 */ + } + + Local3++ + Local4 = Buffer (Local3){} + Local3-- + Local5 = Zero + Name (OEMS, Buffer (0x46){}) + ToBuffer (Local2, OEMS) /* _SB_.PCI0.LPCB.EC0_.SMRD.OEMS */ + While ((Local3 > Local5)) + { + GBFE (OEMS, Local5, RefOf (Local6)) + PBFE (Local4, Local5, Local6) + Local5++ + } + + PBFE (Local4, Local5, Zero) + Arg3 = Local4 + } + } + + Release (MUT0) + Return (Local0) + } + + Method (SMWR, 4, NotSerialized) + { + If (!ECOK) + { + Return (0xFF) + } + + If ((Arg0 != 0x06)) + { + If ((Arg0 != 0x08)) + { + If ((Arg0 != 0x0A)) + { + If ((Arg0 != 0x46)) + { + If ((Arg0 != 0xC6)) + { + Return (0x19) + } + } + } + } + } + + Acquire (MUT0, 0xFFFF) + Local0 = 0x04 + While ((Local0 > One)) + { + If ((Arg0 == 0x06)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0x46)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0xC6)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0x08)) + { + SMW0 = Arg3 + } + + If ((Arg0 == 0x0A)) + { + SMD0 = Arg3 + } + + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + While (!Local1 = (SMST & 0xBF)) + { + Sleep (0x02) + Local3++ + If ((Local3 == 0x32)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + } + } + + If ((Local1 == 0x80)) + { + Local0 = Zero + } + Else + { + Local0-- + } + } + + If (Local0) + { + Local0 = (Local1 & 0x1F) + } + + Release (MUT0) + Return (Local0) + } + + Method (GSHK, 0, Serialized) + { + If ((ECOK == One)) + { + Local0 = SFHK /* _SB_.PCI0.LPCB.EC0_.SFHK */ + } + + Return (Local0) + } + + Method (SSHK, 1, Serialized) + { + If ((ECOK == One)) + { + SFHK = Arg0 + } + } + + Method (CPUS, 1, NotSerialized) + { + If (CondRefOf (_PR.PR00._PPC)) + { + _PR.CPPC = Arg0 + } + + If ((TCNT == 0x08)) + { + Notify (_PR.PR00, 0x80) // Performance Capability Change + Notify (_PR.PR01, 0x80) // Performance Capability Change + Notify (_PR.PR02, 0x80) // Performance Capability Change + Notify (_PR.PR03, 0x80) // Performance Capability Change + Notify (_PR.PR04, 0x80) // Performance Capability Change + Notify (_PR.PR05, 0x80) // Performance Capability Change + Notify (_PR.PR06, 0x80) // Performance Capability Change + Notify (_PR.PR07, 0x80) // Performance Capability Change + } + + If ((TCNT == 0x04)) + { + Notify (_PR.PR00, 0x80) // Performance Capability Change + Notify (_PR.PR01, 0x80) // Performance Capability Change + Notify (_PR.PR02, 0x80) // Performance Capability Change + Notify (_PR.PR03, 0x80) // Performance Capability Change + } + + If ((TCNT == 0x02)) + { + Notify (_PR.PR00, 0x80) // Performance Capability Change + Notify (_PR.PR01, 0x80) // Performance Capability Change + } + Else + { + Notify (_PR.PR00, 0x80) // Performance Capability Change + } + } + + Method (ECMI, 0, NotSerialized) + { + If ((ECOK == One)) + { + OSTD () + CLOW = Zero + CMAX = (MPPP - One) + ACKY = FNKY /* \FNKY */ + SASU () + If ((SMA4 == One)) + { + SMSZ = Zero + } + Else + { + SMSZ = One + } + + ULID (Zero) + } + } + + Method (SASU, 0, NotSerialized) + { + If ((ECOK == One)) + { + If (CondRefOf (_PR.PR00._PPC)) + { + Local0 = _PR.PR00._PPC () + } + + Local1 = (MPPP - One) + If (((SW2S == Zero) || ((SADP >= One) & ( + SADP <= 0x02)))) + { + Local0 = Zero + CPUS (Local0) + CLOW = Local0 + } + + If ((SADP == 0x03)) + { + If ((Local0 < Local1)) + { + Local0++ + CPUS (Local0) + CLOW = Local0 + } + } + } + } + + Method (RPIO, 2, NotSerialized) + { + Local0 = Zero + If ((ECOK == One)) + { + EI01 = Arg0 + EI02 = Arg1 + Local0 = EI03 /* \EI03 */ + } + + Return (Local0) + } + + Method (WPIO, 3, NotSerialized) + { + If ((ECOK == One)) + { + EI01 = Arg0 + EI02 = Arg1 + EI03 = Arg2 + } + } + + Method (ECMD, 3, NotSerialized) + { + If ((ECOK == One)) + { + WPIO (Arg0, Arg1, Arg2) + While (EI03) + { + Stall (0xFF) + } + + Local0 = RPIO (0xFB, Zero) + Return (Local0) + } + } + + Method (CBCD, 0, NotSerialized) + { + If ((ECOK == One)) + { + Local0 = MBDC /* _SB_.PCI0.LPCB.EC0_.MBDC */ + Local0 &= 0xE4 + MBDC = Local0 + } + } + + Method (ULID, 1, NotSerialized) + { + If ((ECOK == One)) + { + If ((ECLS == One)) + { + Local0 = Zero + } + Else + { + Local0 = One + } + + If (IGDS) + { + If ((Arg0 == One)) + { + If ((Local0 != LIDS)) + { + If (^^^GFX0.GLID (Local0)) + { + If ((LIDS == Zero)) + { + ^^^GFX0.CLID |= 0x80000000 /* External reference */ + } + + If ((LIDS == One)) + { + ^^^GFX0.CLID |= 0x80000001 /* External reference */ + } + } + } + } + } + + LIDS = Local0 + } + } + + Method (OSTD, 0, NotSerialized) + { + If ((ECOK == One)) + { + W7OS = Zero + SUSE = Zero + RFLG = Zero + If ((OSYS >= 0x07D0)) + { + If ((OSYS >= 0x07D9)) + { + W7OS = One + If ((OSKU == Zero)) + { + W7OS = Zero + } + } + } + Else + { + If ((OSYS == 0x03E8)) + { + RFLG = One + } + + If ((OSYS == 0x03E9)) + { + SUSE = One + } + } + } + Else + { + W7OS = Zero + SUSE = Zero + RFLG = Zero + } + } + + +#include "ac.asl" +#include "battery.asl" +#include "kb.asl" +#include "tpm.asl" +} diff --git a/src/ec/hp/it8987e/acpi/kb.asl b/src/ec/hp/it8987e/acpi/kb.asl new file mode 100644 index 0000000..bc42897 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/kb.asl @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell mparnell@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is _SB.PCI0.LPCB + +Device (PS2K) +{ + Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBWK = Arg0 + } +} + +Device (PS2M) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If ((CHID == 0x25)) + { + Return ("*SYN326A") + } + Else + { + Return ("*SYN326A") + } + } + + Method (_CID, 0, NotSerialized) // _CID: Compatible ID + { + Return (Package (0x03) + { + 0x001E2E4F, + 0x02002E4F, + 0x130FD041 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQ (Edge, ActiveHigh, Exclusive, ) + {12} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + TPWK = Arg0 + } +} diff --git a/src/ec/hp/it8987e/acpi/superio.asl b/src/ec/hp/it8987e/acpi/superio.asl new file mode 100644 index 0000000..e912e04 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/superio.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is _SB.PCI0.LPCB + +Device (SIO) +{ + Name (_HID, EisaId("PNP0A05")) + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif + +} diff --git a/src/ec/hp/it8987e/acpi/tpm.asl b/src/ec/hp/it8987e/acpi/tpm.asl new file mode 100644 index 0000000..d24d05f --- /dev/null +++ b/src/ec/hp/it8987e/acpi/tpm.asl @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell mparnell@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (_SB.TPM) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If (TCMF) + { + Return (0x01013469) + } + ElseIf ((TTDP == Zero)) + { + Return (0x310CD041) + } + Else + { + Return ("MSFT0101") + } + } + + Method (_STR, 0, NotSerialized) // _STR: Description String + { + If ((TTDP == Zero)) + { + Return (Unicode ("TPM 1.2 Device")) + } + Else + { + Return (Unicode ("TPM 2.0 Device")) + } + } + + Name (_UID, One) // _UID: Unique ID + Name (CRST, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, // Address Base + 0x00001000, // Address Length + _Y31) + Memory32Fixed (ReadOnly, + 0xFED70000, // Address Base + 0x00001000, // Address Length + _Y32) + }) + Name (CRSD, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y33) + }) + Name (CRSI, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y34) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + If ((AMDT == One)) + { + CreateDWordField (CRST, _SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address + CreateDWordField (CRST, _SB.TPM._Y31._LEN, LTFB) // _LEN: Length + MTFB = TPMB /* \TPMB */ + LTFB = 0x1000 + CreateDWordField (CRST, _SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address + CreateDWordField (CRST, _SB.TPM._Y32._LEN, LTFC) // _LEN: Length + MTFC = TPMC /* \TPMC */ + LTFC = 0x1000 + Return (CRST) /* _SB_.TPM_.CRST */ + } + Else + { + If ((DTPT == One)) + { + CreateDWordField (CRSD, _SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address + CreateDWordField (CRSD, _SB.TPM._Y33._LEN, LTFE) // _LEN: Length + MTFE = 0xFED40000 + LTFE = 0x0880 + Return (CRSD) /* _SB_.TPM_.CRSD */ + } + ElseIf ((TTPF == One)) + { + CreateDWordField (CRSI, _SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address + CreateDWordField (CRSI, _SB.TPM._Y34._LEN, LTFD) // _LEN: Length + MTFD = 0xFED40000 + LTFD = 0x5000 + Return (CRSI) /* _SB_.TPM_.CRSI */ + } + ElseIf ((TTPF == Zero)) + { + CreateDWordField (CRSI, _SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address + MTFF = TPMM /* \TPMM */ + Return (CRSI) /* _SB_.TPM_.CRSI */ + } + + MTFE = Zero + LTFE = Zero + Return (CRSI) /* _SB_.TPM_.CRSI */ + } + + Return (CRSI) /* _SB_.TPM_.CRSI */ + } + + OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000) + Field (TMMB, ByteAcc, Lock, Preserve) + { + Offset (0x04), + LCST, 32, + Offset (0x40), + CREQ, 32, + CSTS, 32, + Offset (0x4C), + SCMD, 32 + } + + OperationRegion (CRBD, SystemMemory, TPMM, 0x48) + Field (CRBD, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + HERR, 32, + Offset (0x40), + HCMD, 32, + HSTS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((TTDP == Zero)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + ElseIf ((TTDP == One)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + + Return (Zero) + } + + Method (STRT, 3, Serialized) + { + OperationRegion (TPMR, SystemMemory, FTPM, 0x1000) + Field (TPMR, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + FERR, 32, + Offset (0x0C), + BEGN, 32 + } + + Name (TIMR, Zero) + If ((ToInteger (Arg0) != Zero)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + TIMR = Zero + If ((AMDT == One)) + { + While (((BEGN == One) && (TIMR < 0x0200))) + { + If ((BEGN == One)) + { + Sleep (One) + TIMR++ + } + } + } + ElseIf ((((HSTS & 0x02) | (HSTS & One) + ) == 0x03)) + { + HCMD = One + } + Else + { + FERR = One + BEGN = Zero + } + + Return (Zero) + } + + } + + Return (One) + } + + Method (CRYF, 3, Serialized) + { + If ((ToInteger (Arg0) != One)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + Name (TPMV, Package (0x02) + { + One, + Package (0x02) + { + One, + 0x20 + } + }) + If ((_STA () == Zero)) + { + Return (Package (0x01) + { + Zero + }) + } + + Return (TPMV) /* _SB_.TPM_.CRYF.TPMV */ + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} + + + +Scope (_SB.TPM) +{ + OperationRegion (TSMI, SystemIO, SMIA, 0x02) + Field (TSMI, WordAcc, NoLock, Preserve) + { + SMI, 16 + } + + OperationRegion (ATNV, SystemMemory, PPIM, PPIL) + Field (ATNV, AnyAcc, NoLock, Preserve) + { + RQST, 32, + RCNT, 32, + ERRO, 32, + FLAG, 32, + MISC, 32, + OPTN, 32, + SRSP, 32 + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + Case (One) + { + If ((PPIV == Zero)) + { + Return ("1.2") + } + Else + { + Return ("1.3") + } + } + Case (0x02) + { + RQST = DerefOf (Arg3 [Zero]) + SRSP = Zero + FLAG = 0x02 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* _SB_.TPM_.SRSP */ + } + Case (0x03) + { + Name (PPI1, Package (0x02) + { + Zero, + Zero + }) + PPI1 [One] = RQST /* _SB_.TPM_.RQST */ + Return (PPI1) /* _SB_.TPM_._DSM.PPI1 */ + } + Case (0x04) + { + Return (TRST) /* \TRST */ + } + Case (0x05) + { + Name (PPI2, Package (0x03) + { + Zero, + Zero, + Zero + }) + SRSP = Zero + FLAG = 0x05 + SMI = OFST /* \OFST */ + PPI2 [One] = RCNT /* _SB_.TPM_.RCNT */ + PPI2 [0x02] = ERRO /* _SB_.TPM_.ERRO */ + Return (PPI2) /* _SB_.TPM_._DSM.PPI2 */ + } + Case (0x06) + { + Return (0x03) + } + Case (0x07) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x07 + OPTN = Zero + If ((RQST == 0x17)) + { + ToInteger (DerefOf (Arg3 [One]), OPTN) /* _SB_.TPM_.OPTN */ + } + + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* _SB_.TPM_.SRSP */ + } + Case (0x08) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x08 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* _SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x09 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* _SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + + If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) + { + Return (CRYF (Arg1, Arg2, Arg3)) + } + + If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4"))) + { + Return (STRT (Arg1, Arg2, Arg3)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Method (TPTS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0x04) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + Case (0x05) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + + } + } +} diff --git a/src/ec/hp/it8987e/chip.h b/src/ec/hp/it8987e/chip.h new file mode 100644 index 0000000..1bc9949 --- /dev/null +++ b/src/ec/hp/it8987e/chip.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _EC_HP_IT8987E_CHIP_H +#define _EC_HP_IT8987E_CHIP_H + +#include <device/device.h> + +struct chip_operations; +extern struct chip_operations ec_quanta_it8987e_ops; + +struct ec_quanta_it8987e_config { +}; + +#endif /* _EC_HP_IT8987E_CHIP_H */ diff --git a/src/ec/hp/it8987e/ec.c b/src/ec/hp/it8987e/ec.c new file mode 100644 index 0000000..db6fe3c --- /dev/null +++ b/src/ec/hp/it8987e/ec.c @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> + +#include "ec.h" +#include "chip.h" + +/* helper functions from drivers/pc80/keyboard.c */ +static int input_buffer_empty(u16 status_reg) +{ + u32 timeout; + for (timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF); + timeout--) { + udelay(1000); + } + + if (!timeout) { + printk(BIOS_WARNING, "EC-IT8987E Unexpected input buffer full\n"); + printk(BIOS_WARNING, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg)); + } + return !!timeout; +} + + +static int output_buffer_full(u16 status_reg) +{ + u32 timeout; + for (timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg) + & KBD_OBF) == 0); timeout--) { + udelay(1000); + } + + if (!timeout) { + printk(BIOS_INFO, "EC-IT8987E output buffer result timeout\n"); + printk(BIOS_INFO, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg)); + } + return !!timeout; +} + + + +/* The IT8987E 60/64 EC registers are the same command/status IB/OB KBC pair. + * Check status from 64 port before each command. + * + * Ex. Get panel ID command C43/D77 + * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port + * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port + * Check OBF set. Then Get Data(0x03:panel ID) from 0x60 + * Different commands return may or may not respond and may have multiple + * bytes. Keep it simple for nor + */ + +u8 ec_kbc_read_ob(void) +{ + if (!output_buffer_full(KBD_STATUS)) return 0; + return inb(KBD_DATA); +} + +void ec_kbc_write_cmd(u8 cmd) +{ + if (!input_buffer_empty(KBD_STATUS)) return; + outb(cmd, KBD_COMMAND); +} + +void ec_kbc_write_ib(u8 data) +{ + if (!input_buffer_empty(KBD_STATUS)) return; + outb(data, KBD_DATA); +} + + +/* + * These functions are for accessing the IT8987E device RAM space via 0x66/0x68 + */ + +u8 ec_read_ob(void) +{ + if (!output_buffer_full(EC_SC)) return 0; + return inb(EC_DATA); +} + +void ec_write_cmd(u8 cmd) +{ + if (!input_buffer_empty(EC_SC)) return; + outb(cmd, EC_SC); +} + +void ec_write_ib(u8 data) +{ + if (!input_buffer_empty(EC_SC)) return; + outb(data, EC_DATA); +} + +u8 ec_read(u16 addr) +{ + ec_write_cmd(RD_EC); + ec_write_ib(addr); + return ec_read_ob(); +} + +void ec_write(u16 addr, u8 data) +{ + ec_write_cmd(WR_EC); + ec_write_ib(addr); + ec_write_ib(data); +} + +#ifndef __PRE_RAM__ + +u8 ec_it8987e_get_event(void) +{ + u8 cmd = 0; + u8 status = inb(EC_SC); + if (status & SCI_EVT) { + ec_write_cmd(QR_EC); + cmd = ec_read_ob(); + } else if (status & SMI_EVT) { + ec_kbc_write_cmd(EC_KBD_SMI_EVENT); + cmd = ec_kbc_read_ob(); + } + return cmd; +} + +void ec_it8987e_enable_wake_events(void) +{ + /* + * Set the bit in ECRAM that will enable the Lid switch as a wake source + */ + u8 reg8 = ec_read(EC_WAKE_SRC_ENABLE); + ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE); +} + +#ifndef __SMM__ +static void it8987e_init(struct device *dev) +{ + if (!dev->enabled) + return; + + printk(BIOS_DEBUG, "Quanta IT8987E: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static struct device_operations ops = { + .init = it8987e_init, + .read_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, 0, 0, 0, } +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations ec_quanta_it8987e_ops = { + CHIP_NAME("QUANTA IT8987E EC") + .enable_dev = enable_dev +}; +#endif /* ! __SMM__ */ +#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/hp/it8987e/ec.h b/src/ec/hp/it8987e/ec.h new file mode 100644 index 0000000..f87b2c0 --- /dev/null +++ b/src/ec/hp/it8987e/ec.h @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Modified by Matt Parnell mparnell@gmail.com to support ITL 8987E + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * EC communication interface for QUANTA IT8987E Embedded Controller. + */ + +#ifndef _EC_HP_IT8987E_EC_H +#define _EC_HP_IT8987E_EC_H + +#define EC_IO 0x100 /* Mainboard specific. Could be Kconfig option */ +#define EC_IO_HIGH EC_IO + 1 +#define EC_IO_LOW EC_IO + 2 +#define EC_IO_DATA EC_IO + 3 + +/* Wait 400ms for keyboard controller ansswers */ +#define KBC_TIMEOUT_IN_MS 400 + +// 60h/64h Command Interface +#define KBD_DATA 0x60 +#define KBD_COMMAND 0x64 +#define KBD_STATUS 0x64 +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) + +#define EC_KBD_SMI_EVENT 0xCD +#define EC_KBD_CMD_UNMUTE 0xE8 +#define EC_KBD_CMD_MUTE 0xE9 + +u8 ec_kbc_read_ob(void); +void ec_kbc_write_cmd(u8 cmd); +void ec_kbc_write_ib(u8 data); + +// 62h/66h Command Interface +#define EC_DATA 0x62 +#define EC_SC 0x66 // Status & Control Register +#define SMI_EVT (1 << 6) // 1: SMI event was triggered +#define SCI_EVT (1 << 5) // 1: SCI event was triggered + +// EC Commands (defined in ec_function_spec v3.12) +#define RD_EC 0x80 +#define WR_EC 0x81 +#define QR_EC 0x84 + +#define EC_CMD_EXIT_BOOT_BLOCK 0x85 +#define EC_CMD_NOTIFY_ACPI_ENTER 0x86 +#define EC_CMD_NOTIFY_ACPI_EXIT 0x87 +#define EC_CMD_WARM_RESET 0x8C + +// ECRAM Offsets +#define EC_PERIPH_CNTL_3 0x0D +#define EC_USB_S3_EN 0x26 +#define EC_PERIPH_STAT_3 0x35 +#define EC_THERM_0 0x78 +#define EC_WAKE_SRC_ENABLE 0xBF +#define EC_FW_VER 0xE8 // 2 Bytes +#define EC_IF_MIN_VER 0xEB +#define EC_STATUS_REG 0xEC +#define EC_IF_MAJ_VER 0xEF +#define EC_MBAT_STATUS 0x0138 + + +// EC 0.83b added status bits: +// BIT0=EC in RO mode +// BIT1=Recovery Key Sequence Detected +#define EC_IN_RO_MODE 0x1 +#define EC_IN_RECOVERY_MODE 0x3 + +// EC 0.86a added enable bit: +#define EC_LID_WAKE_ENABLE 0x4 + +u8 ec_read_ob(void); +void ec_write_cmd(u8 cmd); +void ec_write_ib(u8 data); + +u8 ec_read(u16 addr); +void ec_write(u16 addr, u8 data); +u8 ec_it8987e_get_event(void); +void ec_it8987e_enable_wake_events(void); + +#endif /* _EC_HP_IT8987E_EC_H */ diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig new file mode 100644 index 0000000..00542d7 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig @@ -0,0 +1,59 @@ +config BOARD_HP_SPECTRE_AE000 + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_KABYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform does not have any way to see POST codes + +if BOARD_HP_SPECTRE_AE000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "HP" + +config MAINBOARD_FAMILY + string + default "HP Spectre x360" + +config MAINBOARD_PART_NUMBER + string + default "13t-ae000" + +config MAINBOARD_DIR + string + default "hp/hp_spectre_x360_13_convertible" + +config DEVICETREE + string + default "devicetree.cb" + +config FMDFILE + string + default "" + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,0406" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name new file mode 100644 index 0000000..9f089a5 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_SPECTRE_AE000 + bool "Spectre x360 13t-ae000" diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl new file mode 100644 index 0000000..489bdcd --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (ADP1) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If ((_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + Local0 = _SB_.PCI0.LPCB.EC0.SW2S + } + Else + { + Local0 = 1 + } + + Return (Local0) + } + + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* _SB_ */ + } +} + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D") /* Lid Device */) // _HID: Hardware ID + Method (_LID, 0, NotSerialized) // _LID: Lid Status + { + If ((_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((_SB_.PCI0.LPCB.EC0.ECLS == 1)) + { + Local0 = 0 + } + Else + { + Local0 = 1 + } + } + Else + { + Local0 = 1 + } + + /* _SB_.PCI0.LPCB.EC0.ULID (1) */ + Return (Local0) + } +} + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl new file mode 100644 index 0000000..94ce92c --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl @@ -0,0 +1,252 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +Device (BAT0) +{ + Name (FRST, 1) + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (PBIF, Package (0x0D) + { + 1, + 0xFFFFFFFF, + 0xFFFFFFFF, + 1, + 0xFFFFFFFF, + 0xFA, + 0x96, + 0x0A, + 0x19, + "BAT0", + " ", + " ", + " " + }) + Name (PBST, Package (0x04) + { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x2710 + }) + Name (BAST, 0) + Name (B1ST, 0x0F) + Name (B1WT, 0) + Name (FABL, 0xFFFFFFFF) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (_SB_.PCI0.LPCB.EC0.MBTS) + { + B1ST = 0x1F + } + Else + { + B1ST = 0x0F + } + } + Else + { + B1ST = 0x0F + } + + Return (B1ST) /* _SB_.BAT0.B1ST */ + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If ((_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (_SB_.PCI0.LPCB.EC0.MBTS) + { + UPBI () + } + Else + { + IVBI () + } + } + Else + { + IVBI () + } + + Return (PBIF) /* _SB_.BAT0.PBIF */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If ((_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (_SB_.PCI0.LPCB.EC0.MBTS) + { + UPBS () + } + Else + { + IVBS () + } + } + Else + { + IVBS () + } + + Return (PBST) /* _SB_.BAT0.PBST */ + } + + Method (UPBI, 0, NotSerialized) + { + Local5 = _SB_.PCI0.LPCB.EC0.BFCC /* _SB_.PCI0.LPCB.EC0_.BFCC */ + If ((Local5 && !(Local5 & 0x8000))) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + PBIF [1] = Local5 + PBIF [0x02] = Local5 + Local2 = (Local5 / 0x64) + Local2 += 1 + If ((_SB_.PCI0.LPCB.EC0.BADC < 0x0C80)) + { + Local4 = (Local2 * 0x0E) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x09) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0B) + } + ElseIf ((SMA4 == 1)) + { + Local4 = (Local2 * 0x0A) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x05) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x08) + } + Else + { + Local4 = (Local2 * 0x0C) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x07) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0A) + } + + FABL = (Local4 + 0x02) + } + + Local0 = _SB_.PCI0.LPCB.EC0.BVLB /* _SB_.PCI0.LPCB.EC0_.BVLB */ + Local1 = _SB_.PCI0.LPCB.EC0.BVHB /* _SB_.PCI0.LPCB.EC0_.BVHB */ + Local1 <<= 0x08 + Local0 |= Local1 + PBIF [0x04] = Local0 + Sleep (0x32) + PBIF [0x0B] = "LION" + PBIF [0x09] = "Primary" + UPUM () + PBIF [0] = 1 + } + + Method (UPUM, 0, NotSerialized) + { + Local0 = Buffer (0x0A) + { + /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00 // .. + } + Local6 = Buffer (0x05) + { + 0x36, 0x35, 0x35, 0x33, 0x35 // 65535 + } + Local7 = Buffer (0x05) + { + 0x31, 0x32, 0x33, 0x32, 0x31 // 12321 + } + PBIF [0x0C] = "HP" + } + + Method (UPBS, 0, NotSerialized) + { + If ((BRTM == 1)) + { + Local0 = _SB_.PCI0.LPCB.EC0.MCUR /* _SB_.PCI0.LPCB.EC0_.MCUR */ + If ((Local0 & 0x8000)) + { + If ((Local0 == 0xFFFF)) + { + PBST [1] = 0xFFFFFFFF + } + Else + { + Local1 = ~Local0 + Local1++ + Local3 = (Local1 & 0xFFFF) + PBST [1] = Local3 + } + } + Else + { + PBST [1] = Local0 + } + } + Else + { + PBST [1] = 0xFFFFFFFF + } + + Local5 = _SB_.PCI0.LPCB.EC0.MBRM /* _SB_.PCI0.LPCB.EC0_.MBRM */ + If (!(Local5 & 0x8000)) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + If ((Local5 != DerefOf (PBST [0x02]))) + { + PBST [0x02] = Local5 + } + } + + If ((!_SB_.PCI0.LPCB.EC0.SW2S && (_SB_.PCI0.LPCB.EC0.BACR == 1))) + { + PBST [0x02] = FABL /* _SB_.BAT0.FABL */ + } + + PBST [0x03] = _SB_.PCI0.LPCB.EC0.MBCV /* _SB_.PCI0.LPCB.EC0_.MBCV */ + PBST [0] = _SB_.PCI0.LPCB.EC0.MBST /* _SB_.PCI0.LPCB.EC0_.MBST */ + } + + Method (IVBI, 0, NotSerialized) + { + PBIF [1] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = "Bad" + PBIF [0x0A] = "Bad" + PBIF [0x0B] = "Bad" + PBIF [0x0C] = "Bad" + } + + Method (IVBS, 0, NotSerialized) + { + PBST [0] = 0 + PBST [1] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl new file mode 100644 index 0000000..a417560 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl @@ -0,0 +1,393 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_GPE, 0x17) + Name (PHOT, 1) + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + OperationRegion (ERAM, EmbeddedControl, 0, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + SMPR, 8, + SMST, 8, + SMAD, 8, + SMCM, 8, + SMD0, 256, + BCNT, 8, + SMAA, 8, + Offset (0x40), + SW2S, 1, + , 2, + ACCC, 1, + TRPM, 1, + Offset (0x41), + W7OS, 1, + QWOS, 1, + , 1, + SUSE, 1, + RFLG, 1, + Offset (0x43), + , 1, + , 1, + ACPS, 1, + ACKY, 1, + GFXT, 1, + Offset (0x44), + , 7, + DSMB, 1, + Offset (0x47), + TNT2, 8, + TNT3, 8, + Offset (0x4C), + STRM, 8, + Offset (0x4E), + LIDE, 1, + Offset (0x4F), + ACID, 8, + , 2, + PTHM, 1, + , 1, + BSEV, 1, + DPTL, 1, + Offset (0x52), + ECLS, 1, + Offset (0x55), + EC45, 8, + Offset (0x58), + RTMP, 8, + TNT1, 8, + Offset (0x5F), + , 1, + Offset (0x61), + SHPM, 8, + Offset (0x67), + , 1, + , 1, + GC6R, 1, + IGC6, 1, + , 2, + PVSE, 1, + PVSS, 1, + , 3, + PLGS, 1, + , 3, + TPDF, 1, + , 4, + BCTF, 1, + BMNF, 1, + BTVD, 1, + BF10, 1, + Offset (0x6C), + GWKR, 8, + Offset (0x70), + BADC, 16, + BFCC, 16, + BVLB, 8, + BVHB, 8, + BDVO, 8, + Offset (0x7F), + ECTB, 1, + Offset (0x82), + MBST, 8, + MCUR, 16, + MBRM, 16, + MBCV, 16, + Offset (0x8B), + LEDM, 3, + Offset (0x8D), + , 5, + MBFC, 1, + Offset (0x92), + SPSV, 8, + Offset (0x94), + GSSU, 1, + GSMS, 1, + Offset (0x95), + MMST, 4, + DMST, 4, + Offset (0xA0), + QBHK, 8, + Offset (0xA2), + QBBB, 8, + Offset (0xA4), + MBTS, 1, + , 6, + BACR, 1, + Offset (0xA6), + MBDC, 8, + Offset (0xA8), + ENWD, 1, + TMPR, 1, + Offset (0xAA), + , 1, + SMSZ, 1, + , 5, + RCDS, 1, + Offset (0xAD), + SADP, 8, + Offset (0xB2), + RPM1, 8, + RPM2, 8, + Offset (0xBA), + CLOW, 8, + CMAX, 8, + Offset (0xC1), + DPPC, 8, + Offset (0xC6), + , 1, + CVTS, 1, + Offset (0xCE), + NVDX, 8, + ECDX, 8, + EBPL, 1, + Offset (0xD2), + , 7, + DLYE, 1, + Offset (0xD4), + PSHD, 8, + PSLD, 8, + DBPL, 8, + STSP, 8, + Offset (0xDA), + PSIN, 8, + PSKB, 1, + PSTP, 1, + , 1, + PWOL, 1, + RTCE, 1, + Offset (0xE0), + DLYT, 8, + DLY2, 8, + Offset (0xE6), + SFHK, 8, + Offset (0xE9), + DTMT, 8, + PL12, 8, + ETMT, 8, + Offset (0xF2), + ZPDD, 1, + , 6, + ENPA, 1, + Offset (0xF4), + SFAN, 8, + Offset (0xF9), + , 7, + FTHM, 1 + } + + Name (ECOK, 0) + Name (BATO, 0) + Name (BATN, 0) + Name (BATF, 0xC0) + Name (TMEE, 0) + Name (TMDE, 0) + + Method (BPOL, 1, NotSerialized) + { + DBPL = Arg0 + EBPL = 1 + } + + Method (BPOM, 0, NotSerialized) + { + DBPL = 0 + EBPL = 0 + } + + Method (GBAS, 0, NotSerialized) + { + If ((ECOK == 1)) + { + BATF = 0 + Local0 = MBTS /* _SB_.PCI0.LPCB.EC0_.MBTS */ + Local1 = SW2S /* _SB_.PCI0.LPCB.EC0_.SW2S */ + Local0 <<= 0x06 + Local1 <<= 1 + If (((BATO & 0x40) != Local0)) + { + BATF |= 0x40 + } + + If (((BATO & 0x02) != Local1)) + { + BATF |= 0x02 + } + + BATO = 0 + BATO = (Local0 | Local1) + } + } + + Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + BPOM () + GBAS () + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + Notify (ADP1, 0x80) // Status Change + } + + Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "_Q0D : Switch Display (Fn+F4)" + /*_SB_.PCI0.GFX0.GHDS (0)*/ /*Todo: fixme? where is this guy defined? */ + Sleep (0xC8) + } + + Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + GBAS () + If ((0x40 & BATF)) + { + Notify (BAT0, 0x81) // Information Change + } + + Notify (BAT0, 0x80) // Status Change + If ((0x02 & BATF)) + { + Notify (ADP1, 0x80) // Status Change + PWRS = SW2S /* _SB_.PCI0.LPCB.EC0_.SW2S */ + } + + PNOT () + } + } + + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + BACR = 0 + Notify (BAT0, 0x80) // Status Change + } + } + + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + Notify (BAT0, 0x80) // Status Change + } + + Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local0 = ^^RTC.RTMN /* _SB_.PCI0.LPCB.RTC_.RTMN */ + FromBCD (Local0, Local0) + Local1 = ^^RTC.RTHR /* _SB_.PCI0.LPCB.RTC_.RTHR */ + FromBCD (Local1, Local1) + Local2 = ^^RTC.RTDY /* _SB_.PCI0.LPCB.RTC_.RTDY */ + Local3 = ^^RTC.RTSE /* _SB_.PCI0.LPCB.RTC_.RTSE */ + FromBCD (Local3, Local3) + If ((ECOK == 1)) + { + PSIN = 0xFF + Sleep (1) + PSLD = Local0 + PSHD = Local1 + PSIN = 0x1C + Sleep (1) + PSLD = Local2 + PSHD = Local3 + PSIN = 0x1D + } + } + + Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If ((ENWD == 1)) + { + TMPR = 1 + } + } + } + + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If ((CVTS == 1)) + { + Local0 = 0x03 + Local0 <<= 0x10 + Local0 |= 0x03 + Notify (VBPA, 0xCC) // Hardware-Specific + } + + If ((CVTS == 0)) + { + Local0 = 0x02 + Local0 <<= 0x10 + Local0 |= 0x02 + Notify (VBPA, 0xCD) // Hardware-Specific + } + } + } + + /* _Q80 _Q82 _Q83 thermal zone methods removed */ + + Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == 1)) + { + PHOT = 0x02 + } + } + + Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (B0D4, 0x90) // Device-Specific + } + + Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == 1)) + { + PHOT = 0x03 + } + } + + Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If (LIDE) + { + Debug = "_Q8A : LID Switch Event" + LIDE = 0 + Sleep (0x14) + Notify (LID0, 0x80) // Status Change + } + } + } + +/* TODO: revisit _Q8E _Q8F and wtf is _QE4 for? ? */ + +#include "ac.asl" +#include "battery.asl" +#include "kb.asl" +#include "mainboard.asl" +/*#include "tpm.asl"*/ +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl new file mode 100644 index 0000000..296cdba --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell mparnell@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is _SB.PCI0.LPCB + +Device (PS2K) +{ + Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If ((OSYS >= 0x07DC)) + { + Return ("HPQ8001") + } + Else + { + Return ("PNP0303") + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBWK = Arg0 + } +} + +Device (PS2M) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + Return ("*SYN326A") + } + + Method (_CID, 0, NotSerialized) // _CID: Compatible ID + { + Return (Package (0x03) + { + 0x001E2E4F, + 0x02002E4F, + 0x130FD041 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQ (Edge, ActiveHigh, Exclusive, ) + {12} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + TPWK = Arg0 + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl new file mode 100644 index 0000000..3c7189b --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl @@ -0,0 +1,282 @@ + /* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell mparnell@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (RTC) +{ + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + + OperationRegion (CMS0, SystemCMOS, 0, 0x40) + Field (CMS0, ByteAcc, NoLock, Preserve) + { + RTSE, 8, + RTSA, 8, + RTMN, 8, + RTMA, 8, + RTHR, 8, + RTHA, 8, + RTDY, 8, + RTDE, 8 + } +} + +Scope (_SB.PCI0.LPCB.RTC) +{ + OperationRegion (CMS0, SystemCMOS, 0, 0x40) + Field (CMS0, ByteAcc, NoLock, Preserve) + { + RTSE, 8, + RTSA, 8, + RTMN, 8, + RTMA, 8, + RTHR, 8, + RTHA, 8, + RTDY, 8, + RTDE, 8 + } +} + +Device (VBPA) +{ + Name (_HID, "INT33D6" /* Intel Virtual Buttons Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0F) + } + Else + { + Return (0) + } + } + + Name (VBST, 0) + Method (VBDL, 0, NotSerialized) + { + If ((_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((_SB_.PCI0.LPCB.EC0.CVTS == 0)) + { + VBST = 0x40 + } + Else + { + VBST = 0 + } + } + } + + Method (VGBS, 0, NotSerialized) + { + If ((_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((_SB_.PCI0.LPCB.EC0.CVTS == 0)) + { + VBST = 0x40 + } + Else + { + VBST = 0 + } + } + + Return (VBST) /* _SB_.VBPA.VBST */ + } +} + +Device (CIND) +{ + Name (_HID, "INT33D3" /* Intel GPIO Buttons */) // _HID: Hardware ID + Name (_CID, "PNP0C60" /* Display Sensor Device */) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0B) + } + Else + { + Return (0) + } + } +} + +Device (GFX0) +{ + Name (_ADR, 0x00020000) // _ADR: Address +} + +Device (B0D4) +{ +Method (PCIC, 1, Serialized) + { + If ((ECR1 == One)) + { + If ((Arg0 == PCIG)) + { + Return (One) + } + } + + Return (Zero) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If (PCIC (Arg0)) + { + Return (PCID (Arg0, Arg1, Arg2, Arg3)) + } + + Return (Buffer (1) + { + 0x00 // . + }) + } + + Name (_ADR, 0x00040000) // _ADR: Address +} + +Device (ISP0) +{ + Name (_ADR, 0x00050000) // _ADR: Address +} + +Scope () +{ + Name (PCIG, ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */) + Name (KBWK, 0) + Name (TPWK, 0) + + Field (GNVS, AnyAcc, Lock, Preserve) + { + ECR1, 8 + } + + OperationRegion (EXBU, SystemMemory, 0x2F822018, 0x3008) + Field (EXBU, AnyAcc, Lock, Preserve) + { + AEAX, 32, + AEBX, 32, + AECX, 32, + AEDX, 32, + AREF, 32, + DAB0, 8, + DAB1, 8, + DAB2, 8, + DAB3, 8, + WBUF, 1024, + TJMX, 8, + FNKY, 8, + CAME, 8, + VTDT, 8, + DPMD, 8, + WLVD, 16, + WLDD, 16, + WLSV, 16, + WLSS, 16, + BTVD, 16, + BTDD, 16, + WWVD, 16, + WWDD, 16, + WMVD, 16, + WMDD, 16, + GPVD, 16, + GPDD, 16, + SMA4, 8, + PMEE, 8, + WSD0, 8, + WSD1, 8, + WSD2, 8, + WSD3, 8, + WAR7, 8, + DBCM, 8, + CPUP, 64, + GPUP, 32, + SYSP, 64, + FANP, 32, + BATP, 32, + HDDP, 32, + CPUT, 8, + GPUT, 8, + SYST, 8, + FANT, 8, + BATT, 8, + TTST, 8, + RTCF, 8, + BODD, 8, + BRTM, 8, + NOCD, 8, + PWVD, 16, + PWDD, 16, + PWSV, 16, + PWSS, 16, + Offset (0x400), + SBUF, 2048 + } + + Method (PCID, 4, Serialized) + { + If ((Arg0 == PCIG)) + { + If ((Arg1 >= 0x03)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0x01, 0x03 // .. + }) + } + + If ((Arg2 == 0x08)) + { + Return (One) + } + + If ((Arg2 == 0x09)) + { + Return (Package (0x05) + { + 0xC350, + Ones, + Ones, + 0xC350, + Ones + }) + } + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl new file mode 100644 index 0000000..e912e04 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is _SB.PCI0.LPCB + +Device (SIO) +{ + Name (_HID, EisaId("PNP0A05")) + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif + +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl new file mode 100644 index 0000000..d24d05f --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell mparnell@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (_SB.TPM) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If (TCMF) + { + Return (0x01013469) + } + ElseIf ((TTDP == Zero)) + { + Return (0x310CD041) + } + Else + { + Return ("MSFT0101") + } + } + + Method (_STR, 0, NotSerialized) // _STR: Description String + { + If ((TTDP == Zero)) + { + Return (Unicode ("TPM 1.2 Device")) + } + Else + { + Return (Unicode ("TPM 2.0 Device")) + } + } + + Name (_UID, One) // _UID: Unique ID + Name (CRST, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, // Address Base + 0x00001000, // Address Length + _Y31) + Memory32Fixed (ReadOnly, + 0xFED70000, // Address Base + 0x00001000, // Address Length + _Y32) + }) + Name (CRSD, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y33) + }) + Name (CRSI, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y34) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + If ((AMDT == One)) + { + CreateDWordField (CRST, _SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address + CreateDWordField (CRST, _SB.TPM._Y31._LEN, LTFB) // _LEN: Length + MTFB = TPMB /* \TPMB */ + LTFB = 0x1000 + CreateDWordField (CRST, _SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address + CreateDWordField (CRST, _SB.TPM._Y32._LEN, LTFC) // _LEN: Length + MTFC = TPMC /* \TPMC */ + LTFC = 0x1000 + Return (CRST) /* _SB_.TPM_.CRST */ + } + Else + { + If ((DTPT == One)) + { + CreateDWordField (CRSD, _SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address + CreateDWordField (CRSD, _SB.TPM._Y33._LEN, LTFE) // _LEN: Length + MTFE = 0xFED40000 + LTFE = 0x0880 + Return (CRSD) /* _SB_.TPM_.CRSD */ + } + ElseIf ((TTPF == One)) + { + CreateDWordField (CRSI, _SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address + CreateDWordField (CRSI, _SB.TPM._Y34._LEN, LTFD) // _LEN: Length + MTFD = 0xFED40000 + LTFD = 0x5000 + Return (CRSI) /* _SB_.TPM_.CRSI */ + } + ElseIf ((TTPF == Zero)) + { + CreateDWordField (CRSI, _SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address + MTFF = TPMM /* \TPMM */ + Return (CRSI) /* _SB_.TPM_.CRSI */ + } + + MTFE = Zero + LTFE = Zero + Return (CRSI) /* _SB_.TPM_.CRSI */ + } + + Return (CRSI) /* _SB_.TPM_.CRSI */ + } + + OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000) + Field (TMMB, ByteAcc, Lock, Preserve) + { + Offset (0x04), + LCST, 32, + Offset (0x40), + CREQ, 32, + CSTS, 32, + Offset (0x4C), + SCMD, 32 + } + + OperationRegion (CRBD, SystemMemory, TPMM, 0x48) + Field (CRBD, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + HERR, 32, + Offset (0x40), + HCMD, 32, + HSTS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((TTDP == Zero)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + ElseIf ((TTDP == One)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + + Return (Zero) + } + + Method (STRT, 3, Serialized) + { + OperationRegion (TPMR, SystemMemory, FTPM, 0x1000) + Field (TPMR, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + FERR, 32, + Offset (0x0C), + BEGN, 32 + } + + Name (TIMR, Zero) + If ((ToInteger (Arg0) != Zero)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + TIMR = Zero + If ((AMDT == One)) + { + While (((BEGN == One) && (TIMR < 0x0200))) + { + If ((BEGN == One)) + { + Sleep (One) + TIMR++ + } + } + } + ElseIf ((((HSTS & 0x02) | (HSTS & One) + ) == 0x03)) + { + HCMD = One + } + Else + { + FERR = One + BEGN = Zero + } + + Return (Zero) + } + + } + + Return (One) + } + + Method (CRYF, 3, Serialized) + { + If ((ToInteger (Arg0) != One)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + Name (TPMV, Package (0x02) + { + One, + Package (0x02) + { + One, + 0x20 + } + }) + If ((_STA () == Zero)) + { + Return (Package (0x01) + { + Zero + }) + } + + Return (TPMV) /* _SB_.TPM_.CRYF.TPMV */ + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} + + + +Scope (_SB.TPM) +{ + OperationRegion (TSMI, SystemIO, SMIA, 0x02) + Field (TSMI, WordAcc, NoLock, Preserve) + { + SMI, 16 + } + + OperationRegion (ATNV, SystemMemory, PPIM, PPIL) + Field (ATNV, AnyAcc, NoLock, Preserve) + { + RQST, 32, + RCNT, 32, + ERRO, 32, + FLAG, 32, + MISC, 32, + OPTN, 32, + SRSP, 32 + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + Case (One) + { + If ((PPIV == Zero)) + { + Return ("1.2") + } + Else + { + Return ("1.3") + } + } + Case (0x02) + { + RQST = DerefOf (Arg3 [Zero]) + SRSP = Zero + FLAG = 0x02 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* _SB_.TPM_.SRSP */ + } + Case (0x03) + { + Name (PPI1, Package (0x02) + { + Zero, + Zero + }) + PPI1 [One] = RQST /* _SB_.TPM_.RQST */ + Return (PPI1) /* _SB_.TPM_._DSM.PPI1 */ + } + Case (0x04) + { + Return (TRST) /* \TRST */ + } + Case (0x05) + { + Name (PPI2, Package (0x03) + { + Zero, + Zero, + Zero + }) + SRSP = Zero + FLAG = 0x05 + SMI = OFST /* \OFST */ + PPI2 [One] = RCNT /* _SB_.TPM_.RCNT */ + PPI2 [0x02] = ERRO /* _SB_.TPM_.ERRO */ + Return (PPI2) /* _SB_.TPM_._DSM.PPI2 */ + } + Case (0x06) + { + Return (0x03) + } + Case (0x07) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x07 + OPTN = Zero + If ((RQST == 0x17)) + { + ToInteger (DerefOf (Arg3 [One]), OPTN) /* _SB_.TPM_.OPTN */ + } + + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* _SB_.TPM_.SRSP */ + } + Case (0x08) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x08 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* _SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x09 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* _SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + + If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) + { + Return (CRYF (Arg1, Arg2, Arg3)) + } + + If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4"))) + { + Return (STRT (Arg1, Arg2, Arg3)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Method (TPTS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0x04) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + Case (0x05) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + + } + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt new file mode 100644 index 0000000..62be952 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt @@ -0,0 +1,10 @@ +Vendor name: HP +Board name: Spectre 13t-ae000 +Board serial: DAOX33MBAFO +Board URL: https://support.hp.com/us-en/product/HP-Spectre-13-ae000-x360-Convertible-PC... +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2017 diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb new file mode 100644 index 0000000..2bf6b15 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb @@ -0,0 +1,221 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + +# these are probably very wrong + # Enable EC Port 0x68/0x6C + register "gen1_dec" = "0x00040069" + + # EC range is 0x800-0x9ff + register "gen2_dec" = "0x00fc0901" + + # EC range is 0x1610-0x161F + register "gen3_dec" = "0x0001C1611" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" # do we actually need this with only nvme? + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, + }" + + # Enable Root Ports 5 and 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + + # NVMe for port 9 settings + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "1" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port Left + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # UHD Graphics 620 + device pci 04.0 on end # Thermal Subsystem DSP + device pci 13.0 on end # Intel Sensor Hub + device pci 14.0 on end # USB 3 Controller + device pci 14.2 on end # Thermal Subsystem DSP + device pci 15.0 on end # I2C Controller + device pci 1c.0 on end # PCIe Root Port 1 + device pci 1c.1 on end # PCIe Root Port 2 + device pci 1c.4 on end # PCIe Root Port 5 + device pci 1d.0 on end # PCIe Root Port 9 + device pci 1e.0 off end # UART + device pci 1e.2 off end # SPI + device pci 1f.0 on end # ISA Bridge + device pci 1f.2 on end # Memory Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + end +end diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl new file mode 100644 index 0000000..d36c960 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x01072009 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h new file mode 100644 index 0000000..42a6287 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell mparnell@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* ------- GPIO group GPP_A ------- */ +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x18), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c19), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c1a), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c1b), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c1c), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x1d), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x1e), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x82080102, 0x1f), +/* CLKRUN# */_PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x20), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1021), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1022), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000300, 0x23), +/* ISH_GP6 */_PAD_CFG_STRUCT(GPP_A12, 0x44000b02, 0x24), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x25), +/* GPIO */_PAD_CFG_STRUCT(GPP_A14, 0x44000300, 0x26), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3027), +/* GPIO */_PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x28), +/* GPIO */_PAD_CFG_STRUCT(GPP_A17, 0x44000100, 0x29), +/* ISH_GP0 */_PAD_CFG_STRUCT(GPP_A18, 0x44000700, 0x2a), +/* ISH_GP1 */_PAD_CFG_STRUCT(GPP_A19, 0x44000700, 0x2b), +/* ISH_GP2 */_PAD_CFG_STRUCT(GPP_A20, 0x44000700, 0x2c), +/* ISH_GP3 */_PAD_CFG_STRUCT(GPP_A21, 0x44000700, 0x2d), +/* ISH_GP4 */_PAD_CFG_STRUCT(GPP_A22, 0x44000700, 0x2e), +/* ISH_GP5 */_PAD_CFG_STRUCT(GPP_A23, 0x44000502, 0x3f), +/* ------- GPIO Group GPP_B -------*/ +/* GPIO */_PAD_CFG_STRUCT(GPP_B0, 0x44000300, 0x30), +/* GPIO */_PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x31), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x32), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000300, 0x33), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x34), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x35), +/* GPIO */_PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x36), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x37), +/* GPIO */_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x38), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x39), +/* SRCCLKREQ5# */_PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x3a), +/* GPIO */_PAD_CFG_STRUCT(GPP_B11, 0x44000300, 0x3b), +/* GPIO */_PAD_CFG_STRUCT(GPP_B12, 0x44000300, 0x3c), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x3d), +/* SPKR */_PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x103e), +/* GSPI0_CS# */_PAD_CFG_STRUCT(GPP_B15, 0x44000700, 0x3f), +/* GSPI0_CLK */_PAD_CFG_STRUCT(GPP_B16, 0x84000700, 0x40), +/* GSPI0_MISO */_PAD_CFG_STRUCT(GPP_B17, 0x44000700, 0x41), +/* GSPI0_MOSI */_PAD_CFG_STRUCT(GPP_B18, 0x84000700, 0x42), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x43), +/* GPIO */_PAD_CFG_STRUCT(GPP_B20, 0x44000300, 0x1044), +/* GPIO */_PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x1045), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1046), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000300, 0x47), +/* ------- GPIO Group GPP_C ------- */ +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x48), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1049), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x104a), +/* GPIO */_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x4b), +/* GPIO */_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x4c), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x4d), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x50), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x51), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x52), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x53), +/* GPIO */_PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x54), +/* GPIO */_PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x55), +/* GPIO */_PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x56), +/* GPIO */_PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x57), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x58), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x59), +/* GPIO */_PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x5a), +/* GPIO */_PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x5b), +/* GPIO */_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x5c), +/* GPIO */_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x5d), +/* GPIO */_PAD_CFG_STRUCT(GPP_C22, 0x82880102, 0x105e), +/* GPIO */_PAD_CFG_STRUCT(GPP_C23, 0x80880102, 0x5f), +/* ------- GPIO Group GPP_D ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x60), +/* GPIO */_PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x61), +/* GPIO */_PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x62), +/* GPIO */_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x63), +/* GPIO */_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x64), +/* ISH_I2C0_SDA */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x65), +/* ISH_I2C0_SCL */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x66), +/* ISH_I2C1_SDA */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x67), +/* ISH_I2C1_SCL */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x68), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x82000102, 0x69), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x6a), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x6b), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x6c), +/* GPIO */_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x6d), +/* GPIO */_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x6e), +/* GPIO */_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x6f), +/* GPIO */_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x70), +/* GPIO */_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x71), +/* GPIO */_PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x72), +/* GPIO */_PAD_CFG_STRUCT(GPP_D19, 0x44000300, 0x73), +/* GPIO */_PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x74), +/* GPIO */_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x75), +/* GPIO */_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x76), +/* GPIO */_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x77), +/* ------- GPIO Group GPP_E ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x84000102, 0x18), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x84000102, 0x19), +/* SATAXPCIE2 */_PAD_CFG_STRUCT(GPP_E2, 0x84000500, 0x1a), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x1b), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x84000200, 0x101c), +/* GPIO */_PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x1d), +/* GPIO */_PAD_CFG_STRUCT(GPP_E6, 0x44000300, 0x1e), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x1f), +/* GPIO */_PAD_CFG_STRUCT(GPP_E8, 0x44000300, 0x20), +/* GPIO */_PAD_CFG_STRUCT(GPP_E9, 0x44000300, 0x21), +/* GPIO */_PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x22), +/* GPIO */_PAD_CFG_STRUCT(GPP_E11, 0x80100102, 0x23), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x84000201, 0x24), +/* DDPB_HPD0 */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x25), +/* DDPC_HPD1 */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x26), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880300, 0x27), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000300, 0x28), +/* EDP_HPD */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x29), +/* DDPB_CTRLCLK */_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x2a), +/* DDPB_CTRLDATA */_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x102b), +/* DDPC_CTRLCLK */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x2c), +/* DDPC_CTRLDATA */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x102d), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000300, 0x2e), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x102f), +/* ------- GPIO Group GPD ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x50), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000700, 0x51), +/* GPIO */_PAD_CFG_STRUCT(GPD2, 0x4000200, 0x52), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3053), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x54), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x55), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x56), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x57), +/* GPIO */_PAD_CFG_STRUCT(GPD8, 0x44000300, 0x58), +/* GPIO */_PAD_CFG_STRUCT(GPD9, 0x44000300, 0x59), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x44000700, 0x5a), +/* GPIO */_PAD_CFG_STRUCT(GPD11, 0x44000300, 0x5b), +/* ------- GPIO Group GPP_F ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x30), +/* GPIO */_PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x31), +/* GPIO */_PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x32), +/* GPIO */_PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x33), +/* GPIO */_PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x34), +/* GPIO */_PAD_CFG_STRUCT(GPP_F5, 0x44000300, 0x35), +/* GPIO */_PAD_CFG_STRUCT(GPP_F6, 0x44000300, 0x36), +/* GPIO */_PAD_CFG_STRUCT(GPP_F7, 0x44000300, 0x37), +/* GPIO */_PAD_CFG_STRUCT(GPP_F8, 0x44000100, 0x38), +/* GPIO */_PAD_CFG_STRUCT(GPP_F9, 0x44000100, 0x39), +/* I2C5_SDA */_PAD_CFG_STRUCT(GPP_F10, 0x44000702, 0x3a), +/* I2C5_SCL */_PAD_CFG_STRUCT(GPP_F11, 0x44000702, 0x3b), +/* GPIO */_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x3c), +/* GPIO */_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x3d), +/* GPIO */_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x3e), +/* GPIO */_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x3f), +/* GPIO */_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x40), +/* GPIO */_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x41), +/* GPIO */_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x42), +/* GPIO */_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x43), +/* GPIO */_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x44), +/* GPIO */_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x45), +/* GPIO */_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x46), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000300, 0x47), +/* ------- GPIO Group GPP_G ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x48), +/* GPIO */_PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x49), +/* GPIO */_PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x4a), +/* GPIO */_PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x4b), +/* GPIO */_PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x4c), +/* GPIO */_PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x4d), +/* GPIO */_PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x4e), +/* GPIO */_PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x4f), +}; + +#endif + +#endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c new file mode 100644 index 0000000..c0de990 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki naresh.solanki@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h new file mode 100644 index 0000000..510a9ce --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0295, /* Codec Vendor / Device ID: Realtek */ + 0x103c83b9, /* Subsystem ID */ + 0x0000000d, /* Number of NID entries */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x103c83b9 */ + AZALIA_SUBVENDOR(0x0, 0x103c83b9), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), + + /* Pin Complex (NID 0x13) */ + AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x411111f0), + + /* Pin Complex (NID 0x16) */ + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03a11040), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40600001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x03211020), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c new file mode 100644 index 0000000..faf4090 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 1:
(529 comments)
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/batt... File src/ec/hp/it8987e/acpi/battery.asl:
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https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/ec.a... File src/ec/hp/it8987e/acpi/ec.asl:
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https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 122: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 123: LCST, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 124: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 125: CREQ, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 126: CSTS, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 127: Offset (0x4C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 134: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 135: HERR, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 136: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 137: HCMD, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 170: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 171: FERR, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 172: Offset (0x0C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 236: One, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 239: One, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 266: { trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 276: RQST, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 277: RCNT, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 278: ERRO, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 279: FLAG, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 280: MISC, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 281: OPTN, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 323: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 337: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 338: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/acpi/tpm.... PS1, Line 446: } trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.h File src/ec/hp/it8987e/ec.h:
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.h@3 PS1, Line 3: * trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.h@25 PS1, Line 25: #define EC_IO_HIGH EC_IO + 1 Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.h@26 PS1, Line 26: #define EC_IO_LOW EC_IO + 2 Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.h@27 PS1, Line 27: #define EC_IO_DATA EC_IO + 3 Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.c File src/ec/hp/it8987e/ec.c:
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.c@74 PS1, Line 74: if (!output_buffer_full(KBD_STATUS)) return 0; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.c@80 PS1, Line 80: if (!input_buffer_empty(KBD_STATUS)) return; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.c@86 PS1, Line 86: if (!input_buffer_empty(KBD_STATUS)) return; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.c@97 PS1, Line 97: if (!output_buffer_full(EC_SC)) return 0; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.c@103 PS1, Line 103: if (!input_buffer_empty(EC_SC)) return; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/34946/1/src/ec/hp/it8987e/ec.c@109 PS1, Line 109: if (!input_buffer_empty(EC_SC)) return; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 38: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 28: 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 29: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 30: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 31: 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 32: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 33: 0xFA, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 34: 0x96, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 35: 0x0A, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 36: 0x19, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 37: "BAT0", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 38: " ", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 39: " ", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 44: 0, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 45: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 46: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 31: SMPR, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 32: SMST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 33: SMAD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 34: SMCM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 35: SMD0, 256, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 36: BCNT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 37: SMAA, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 38: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 39: SW2S, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 40: , 2, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 41: ACCC, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 42: TRPM, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 43: Offset (0x41), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 44: W7OS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 45: QWOS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 46: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 47: SUSE, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 48: RFLG, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 49: Offset (0x43), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 50: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 51: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 52: ACPS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 53: ACKY, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 54: GFXT, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 55: Offset (0x44), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 56: , 7, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 57: DSMB, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 58: Offset (0x47), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 59: TNT2, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 60: TNT3, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 61: Offset (0x4C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 62: STRM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 63: Offset (0x4E), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 64: LIDE, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 65: Offset (0x4F), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 66: ACID, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 67: , 2, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 68: PTHM, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 69: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 70: BSEV, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 71: DPTL, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 72: Offset (0x52), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 73: ECLS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 74: Offset (0x55), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 75: EC45, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 76: Offset (0x58), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 77: RTMP, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 78: TNT1, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 79: Offset (0x5F), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 80: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 81: Offset (0x61), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 82: SHPM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 83: Offset (0x67), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 84: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 85: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 86: GC6R, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 87: IGC6, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 88: , 2, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 89: PVSE, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 90: PVSS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 91: , 3, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 92: PLGS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 93: , 3, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 94: TPDF, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 95: , 4, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 96: BCTF, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 97: BMNF, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 98: BTVD, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 99: BF10, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 100: Offset (0x6C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 101: GWKR, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 102: Offset (0x70), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 103: BADC, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 104: BFCC, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 105: BVLB, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 106: BVHB, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 107: BDVO, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 108: Offset (0x7F), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 109: ECTB, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 110: Offset (0x82), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 111: MBST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 112: MCUR, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 113: MBRM, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 114: MBCV, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 115: Offset (0x8B), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 116: LEDM, 3, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 117: Offset (0x8D), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 118: , 5, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 119: MBFC, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 120: Offset (0x92), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 121: SPSV, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 122: Offset (0x94), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 123: GSSU, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 124: GSMS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 125: Offset (0x95), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 126: MMST, 4, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 127: DMST, 4, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 128: Offset (0xA0), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 129: QBHK, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 130: Offset (0xA2), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 131: QBBB, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 152: CLOW, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 153: CMAX, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 154: Offset (0xC1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 155: DPPC, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 156: Offset (0xC6), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 157: , 1, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 160: NVDX, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 167: PSHD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 168: PSLD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 169: DBPL, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 170: STSP, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 179: DLYT, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 182: SFHK, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 186: ETMT, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 188: ZPDD, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 189: , 6, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 192: SFAN, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 348: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 386: /* TODO: revisit _Q8E _Q8F and wtf is _QE4 for? ? */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl:
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl:
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 37: RTSE, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 39: RTMN, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 40: RTMA, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 41: RTHR, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 55: RTMN, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 56: RTMA, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 57: RTHR, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 58: RTHA, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 59: RTDY, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 176: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 181: trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 189: AREF, 32, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 194: WBUF, 1024, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 195: TJMX, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 196: FNKY, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 197: CAME, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 198: VTDT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 199: DPMD, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 204: BTVD, 16, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 211: GPDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 212: SMA4, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 213: PMEE, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 214: WSD0, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 217: WSD3, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 218: WAR7, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 219: DBCM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 220: CPUP, 64, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 221: GPUP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 222: SYSP, 64, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 223: FANP, 32, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 225: HDDP, 32, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 231: TTST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 232: RTCF, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 233: BODD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 234: BRTM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 235: NOCD, 8, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 237: PWDD, 16, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 240: Offset (0x400), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 243: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 267: 0xC350, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 268: Ones, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 270: 0xC350, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl:
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 123: LCST, 32, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 125: CREQ, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 126: CSTS, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 127: Offset (0x4C), trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 135: HERR, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 136: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 137: HCMD, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 170: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 171: FERR, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 172: Offset (0x0C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 236: One, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 239: One, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 266: { trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 276: RQST, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 277: RCNT, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 278: ERRO, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 279: FLAG, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 280: MISC, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 281: OPTN, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 323: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 337: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 338: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 446: } trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 45: register "EnableSata" = "0" # do we actually need this with only nvme? trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 168: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 219: device pci 1f.4 on end # SMBus trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 34: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/1/src/mainboard/hp/spectre_x3... PS1, Line 64: trailing whitespace
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#2).
Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/ec/hp/it8987e/Kconfig A src/ec/hp/it8987e/Makefile.inc A src/ec/hp/it8987e/acpi/ac.asl A src/ec/hp/it8987e/acpi/battery.asl A src/ec/hp/it8987e/acpi/ec.asl A src/ec/hp/it8987e/acpi/kb.asl A src/ec/hp/it8987e/acpi/superio.asl A src/ec/hp/it8987e/acpi/tpm.asl A src/ec/hp/it8987e/chip.h A src/ec/hp/it8987e/ec.c A src/ec/hp/it8987e/ec.h A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 31 files changed, 5,065 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/2
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34946/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34946/2//COMMIT_MSG@7 PS2, Line 7: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port Please create a seperate patch for the embedded controller and rebase the mainboard patch on it.
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#3).
Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,567 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/3
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#4).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,567 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/4
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 5:
Patch Set 2:
(1 comment)
Done, however I may need some assistance cleaning them up.
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#6).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- M src/mainboard/hp/spectre_x360_13t_ae000/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/6
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#7).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,565 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 7:
(299 comments)
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 37: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 28: 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 29: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 30: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 31: 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 32: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 33: 0xFA, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 34: 0x96, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 35: 0x0A, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 36: 0x19, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 37: "BAT0", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 38: " ", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 39: " ", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 44: 0, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 45: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 46: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 31: SMPR, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 32: SMST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 33: SMAD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 34: SMCM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 35: SMD0, 256, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 36: BCNT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 37: SMAA, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 38: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 39: SW2S, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 40: , 2, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 41: ACCC, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 42: TRPM, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 43: Offset (0x41), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 44: W7OS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 45: QWOS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 46: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 47: SUSE, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 48: RFLG, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 49: Offset (0x43), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 50: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 51: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 52: ACPS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 53: ACKY, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 54: GFXT, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 55: Offset (0x44), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 56: , 7, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 57: DSMB, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 58: Offset (0x47), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 59: TNT2, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 60: TNT3, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 61: Offset (0x4C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 62: STRM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 63: Offset (0x4E), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 64: LIDE, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 65: Offset (0x4F), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 66: ACID, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 67: , 2, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 68: PTHM, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 69: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 70: BSEV, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 71: DPTL, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 72: Offset (0x52), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 73: ECLS, 1, trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 386: /* TODO: revisit _Q8E _Q8F and wtf is _QE4 for? ? */ trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl:
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https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 196: FNKY, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 197: CAME, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 198: VTDT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 199: DPMD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 200: WLVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 201: WLDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 202: WLSV, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 203: WLSS, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 204: BTVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 205: BTDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 206: WWVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 207: WWDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 208: WMVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 209: WMDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 210: GPVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 211: GPDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 212: SMA4, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 213: PMEE, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 214: WSD0, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 215: WSD1, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 216: WSD2, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 217: WSD3, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 218: WAR7, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 219: DBCM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 220: CPUP, 64, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 221: GPUP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 222: SYSP, 64, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 223: FANP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 224: BATP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 225: HDDP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 226: CPUT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 227: GPUT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 228: SYST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 229: FANT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 230: BATT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 231: TTST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 232: RTCF, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 233: BODD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 234: BRTM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 235: NOCD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 236: PWVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 237: PWDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 238: PWSV, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 239: PWSS, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 240: Offset (0x400), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 243: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 267: 0xC350, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 268: Ones, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 269: Ones, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 270: 0xC350, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl:
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 122: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 123: LCST, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 124: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 125: CREQ, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 126: CSTS, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 127: Offset (0x4C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 134: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 135: HERR, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 136: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 137: HCMD, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 170: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 171: FERR, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 172: Offset (0x0C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 236: One, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 239: One, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 266: { trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 276: RQST, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 277: RCNT, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 278: ERRO, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 279: FLAG, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 280: MISC, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 281: OPTN, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 323: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 337: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 338: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 446: } trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 45: register "EnableSata" = "0" # do we actually need this with only nvme? trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 168: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 219: device pci 1f.4 on end # SMBus trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 34: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/7/src/mainboard/hp/spectre_x3... PS7, Line 64: trailing whitespace
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#8).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,566 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 8:
(299 comments)
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 37: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 28: 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 29: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 30: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 31: 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 32: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 33: 0xFA, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 34: 0x96, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 35: 0x0A, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 36: 0x19, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 37: "BAT0", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 38: " ", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 39: " ", trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 44: 0, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 45: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 46: 0xFFFFFFFF, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 31: SMPR, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 32: SMST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 33: SMAD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 34: SMCM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 35: SMD0, 256, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 36: BCNT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 37: SMAA, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 38: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 39: SW2S, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 40: , 2, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 41: ACCC, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 42: TRPM, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 43: Offset (0x41), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 44: W7OS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 45: QWOS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 46: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 47: SUSE, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 48: RFLG, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 49: Offset (0x43), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 50: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 51: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 52: ACPS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 53: ACKY, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 54: GFXT, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 55: Offset (0x44), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 56: , 7, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 57: DSMB, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 58: Offset (0x47), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 59: TNT2, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 60: TNT3, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 61: Offset (0x4C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 62: STRM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 63: Offset (0x4E), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 64: LIDE, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 65: Offset (0x4F), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 66: ACID, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 67: , 2, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 68: PTHM, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 69: , 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 70: BSEV, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 71: DPTL, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 72: Offset (0x52), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 73: ECLS, 1, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 74: Offset (0x55), trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 386: /* TODO: revisit _Q8E _Q8F and wtf is _QE4 for? ? */ trailing whitespace
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https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 199: DPMD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 200: WLVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 201: WLDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 202: WLSV, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 203: WLSS, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 204: BTVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 205: BTDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 206: WWVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 207: WWDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 208: WMVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 209: WMDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 210: GPVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 211: GPDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 212: SMA4, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 213: PMEE, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 214: WSD0, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 215: WSD1, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 216: WSD2, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 217: WSD3, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 218: WAR7, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 219: DBCM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 220: CPUP, 64, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 221: GPUP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 222: SYSP, 64, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 223: FANP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 224: BATP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 225: HDDP, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 226: CPUT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 227: GPUT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 228: SYST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 229: FANT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 230: BATT, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 231: TTST, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 232: RTCF, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 233: BODD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 234: BRTM, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 235: NOCD, 8, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 236: PWVD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 237: PWDD, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 238: PWSV, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 239: PWSS, 16, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 240: Offset (0x400), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 243: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 267: 0xC350, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 268: Ones, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 269: Ones, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 270: 0xC350, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl:
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 122: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 123: LCST, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 124: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 125: CREQ, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 126: CSTS, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 127: Offset (0x4C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 134: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 135: HERR, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 136: Offset (0x40), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 137: HCMD, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 170: Offset (0x04), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 171: FERR, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 172: Offset (0x0C), trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 236: One, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 239: One, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 266: { trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 276: RQST, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 277: RCNT, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 278: ERRO, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 279: FLAG, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 280: MISC, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 281: OPTN, 32, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 323: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 337: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 338: Zero, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 446: } trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 45: register "EnableSata" = "0" # do we actually need this with only nvme? trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 168: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 219: device pci 1f.4 on end # SMBus trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 34: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/8/src/mainboard/hp/spectre_x3... PS8, Line 64: trailing whitespace
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 8:
Patch Set 2:
(1 comment)
Done...hopefully nothing too egregious otherwise, other than the fact it doesn't boot yet.
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#9).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,566 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/9
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34946/9/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/9/src/mainboard/hp/spectre_x3... PS9, Line 2: config BOARD_HP_SPECTRE_AE000 config BOARD_SPECIFIC_OPTIONS
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#10).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,566 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/10
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 32: default "hp/hp_spectre_x360_13_convertible" Has to match the path in the filesystem
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 34: config DEVICETREE : string : default "devicetree.cb" Not needed
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 38: config FMDFILE : string : default "" Same
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt:
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 3: Board serial: DAOX33MBAFO I think this is board specific and should be removed.
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 43: Remove empty line
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/gpio.h:
PS10: Please get everything aligned and use a style like this:
/* GPIO_PIN */ _PAD_CFG_STRUCT(..., ..., ...)
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#11).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,729 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/11
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#12).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,729 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/12
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#13).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,721 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/13
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 13:
(13 comments)
Patch Set 10:
(3 comments)
I think I've taken care of all your comments so far.
https://review.coreboot.org/c/coreboot/+/34946/9/src/mainboard/hp/spectre_x3... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/9/src/mainboard/hp/spectre_x3... PS9, Line 2: config BOARD_HP_SPECTRE_AE000
config BOARD_SPECIFIC_OPTIONS
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 32: default "hp/hp_spectre_x360_13_convertible"
Has to match the path in the filesystem
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 32: default "hp/hp_spectre_x360_13_convertible"
Has to match the path in the filesystem
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 32: default "hp/hp_spectre_x360_13_convertible"
Has to match the path in the filesystem
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 34: config DEVICETREE : string : default "devicetree.cb"
Not needed
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 34: config DEVICETREE : string : default "devicetree.cb"
Not needed
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 34: config DEVICETREE : string : default "devicetree.cb"
Not needed
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 38: config FMDFILE : string : default ""
Same
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 38: config FMDFILE : string : default ""
Same
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 38: config FMDFILE : string : default ""
Same
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt:
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 3: Board serial: DAOX33MBAFO
I think this is board specific and should be removed.
This is the model number, I was tired, I'll correct the label.
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... PS10, Line 43:
Remove empty line
Done
https://review.coreboot.org/c/coreboot/+/34946/10/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/gpio.h:
PS10:
Please get everything aligned and use a style like this: […]
Ack
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 13:
(11 comments)
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 2: config BOARD_SPECIFIC_OPTIONS Add `def_bool y` after this line, otherwise these options won't be selected.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 9: select MAINBOARD_USES_FSP2_0 Not needed, since it is selected by the SOC.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 12: select NO_POST # This platform does not have any way to see POST codes Sure, the log file. Remove this and add the following options below.
config POST_IO bool default n
config POST_DEVICE bool default n
config CONSOLE_POST bool default y
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl:
PS13: Empty this file since the IASL compiler complains too much while building and at the moment we don't need them. Can be added later again.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl:
PS13: Same.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl:
PS13: Same.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl:
PS13: Same.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl:
PS13: Same.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl:
PS13: Same.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl:
PS13: Same.
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 49: dev = SA_DEV_ROOT; SA_DEVFN_ROOT
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 13:
(17 comments)
Patch Set 13:
(11 comments)
I've commented out the asl files, so I don't have to find and revert it later...everything else should be addressed. I haven't test built this yet though...
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 2: config BOARD_SPECIFIC_OPTIONS
Add `def_bool y` after this line, otherwise these options won't be selected.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 2: config BOARD_SPECIFIC_OPTIONS
Add `def_bool y` after this line, otherwise these options won't be selected.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 2: config BOARD_SPECIFIC_OPTIONS
Add `def_bool y` after this line, otherwise these options won't be selected.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 9: select MAINBOARD_USES_FSP2_0
Not needed, since it is selected by the SOC.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 9: select MAINBOARD_USES_FSP2_0
Not needed, since it is selected by the SOC.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 9: select MAINBOARD_USES_FSP2_0
Not needed, since it is selected by the SOC.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 12: select NO_POST # This platform does not have any way to see POST codes
Sure, the log file. Remove this and add the following options below. […]
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 12: select NO_POST # This platform does not have any way to see POST codes
Sure, the log file. Remove this and add the following options below. […]
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 12: select NO_POST # This platform does not have any way to see POST codes
Sure, the log file. Remove this and add the following options below. […]
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl:
PS13:
Empty this file since the IASL compiler complains too much while building and at the moment we don't […]
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl:
PS13:
Same.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl:
PS13:
Same.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl:
PS13:
Same.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl:
PS13:
Same.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl:
PS13:
Same.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl:
PS13:
Same.
Done
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34946/13/src/mainboard/hp/spectre_x... PS13, Line 49: dev = SA_DEV_ROOT;
SA_DEVFN_ROOT
Done
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#14).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 2,740 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/14
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34946/14/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/14/src/mainboard/hp/spectre_x... PS14, Line 13: config POST_IO trailing whitespace
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#15).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 1,001 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/15
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34946/15/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/15/src/mainboard/hp/spectre_x... PS15, Line 13: config POST_IO trailing whitespace
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#16).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Note: EC firmware needs injected at 0x200000. In factory image, it is from 0x200000 to 0x21FFFF
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 1,001 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/16
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#17).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 1,001 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/17
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#18).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 1,048 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/18
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#19).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 1,048 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/19
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#20).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 20 files changed, 1,047 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/20
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 20:
After doing a test flash with the seemingly requisite injection of the EC firmware at 0x200000, the machine powers on, then reboots as if the EC is reflashing itself, and then does the usual caps lock blink code errors.
I did build with logging to flash enabled, and while the two images from before and after the flash differ, it appears the CONSOLE region doesn't exist for some reason.
Here is my build, and the failure image whose signature changed after boot:
https://mega.nz/#!NRMChYzK!pdmgz79dR32B0eRe086hc3rcRiwyzSg2Wihixm1mLnI
I can provide my config if you don't want to extract it from the image itself...but I'm stuck.
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#22).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/memory.c A src/mainboard/hp/spectre_x360_13t_ae000/memory.h A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 24 files changed, 1,216 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/22
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 22:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34946/22/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/Kconfig:
https://review.coreboot.org/c/coreboot/+/34946/22/src/mainboard/hp/spectre_x... PS22, Line 20: config POST_IO trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/22/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/romstage.c:
https://review.coreboot.org/c/coreboot/+/34946/22/src/mainboard/hp/spectre_x... PS22, Line 15: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/22/src/mainboard/hp/spectre_x... PS22, Line 15: please, no spaces at the start of a line
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#23).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/memory.c A src/mainboard/hp/spectre_x360_13t_ae000/memory.h A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 24 files changed, 1,216 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/23
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#24).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/memory.c A src/mainboard/hp/spectre_x360_13t_ae000/memory.h A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 24 files changed, 1,214 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/24
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 24:
With the help of hellsenberg we appear to now be past ram init, however the machine still stops before we get anywhere, with the EC complaining about it.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 24:
(4 comments)
Some suggestions so that you can understand what romstage looks like better
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/memory.h:
PS24: This isn't needed as you don't use variants
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/memory.c:
PS24: This can be inside romstage.c
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/romstage.c:
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... PS24, Line 53: memory_params once you move the memory data into this file, this struct can be removed. Uninitialized fields are memset'd to zero on line 58, btw.
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... PS24, Line 75: mem_cfg->MemorySpdPtr10 = 0; Always run this for now, as bringing up one channel at a time is easier.
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 24:
Patch Set 24:
(4 comments)
Some suggestions so that you can understand what romstage looks like better
I have not yet addressed these items, however I also can't recall the line of thought I was working on with hellsenberg in IRC, in regard to why I've not gotten it booting yet...
I'm still new to this kind of thing so suggestions are welcome.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34946/24//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34946/24//COMMIT_MSG@9 PS24, Line 9: Signed-off-by: Matt Parnell mparnell@gmail.com Please move this right below the Change-Id line.
Hello Angel Pons, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#25).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Signed-off-by: Matt Parnell mparnell@gmail.com --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/memory.c A src/mainboard/hp/spectre_x360_13t_ae000/memory.h A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 24 files changed, 1,214 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/25
Hello Angel Pons, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#26).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Signed-off-by: Matt Parnell mparnell@gmail.com --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 22 files changed, 1,137 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/26
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 26:
(10 comments)
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/romstage.c:
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 27: /* Do you really want me to make a header for this? trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 41: /* stock image around 0x007445A0 and 0x007A2C80 and 0x007BA120 trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 42: * around 0x007BA120 is probably where we have maps for different trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 84: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 86: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 87: memcpy(&mem_cfg->RcompResistor, rcomp_resistor, trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 89: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 93: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 98: trailing whitespace
https://review.coreboot.org/c/coreboot/+/34946/26/src/mainboard/hp/spectre_x... PS26, Line 103: trailing whitespace
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 26:
(5 comments)
Patch Set 24:
(1 comment)
These concerns should all be addressed, once I make jenkins happy with my whitespace.
https://review.coreboot.org/c/coreboot/+/34946/24//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34946/24//COMMIT_MSG@9 PS24, Line 9: Signed-off-by: Matt Parnell mparnell@gmail.com
Please move this right below the Change-Id line.
Ack
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/memory.h:
PS24:
This isn't needed as you don't use variants
Cleaned it up.
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/memory.c:
PS24:
This can be inside romstage. […]
Done
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/romstage.c:
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... PS24, Line 53: memory_params
once you move the memory data into this file, this struct can be removed. […]
Done
https://review.coreboot.org/c/coreboot/+/34946/24/src/mainboard/hp/spectre_x... PS24, Line 75: mem_cfg->MemorySpdPtr10 = 0;
Always run this for now, as bringing up one channel at a time is easier.
Good to know, thank you.
Hello Angel Pons, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#27).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Signed-off-by: Matt Parnell mparnell@gmail.com --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 22 files changed, 1,137 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/27
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34946/27/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/romstage.c:
https://review.coreboot.org/c/coreboot/+/34946/27/src/mainboard/hp/spectre_x... PS27, Line 87: memcpy(&mem_cfg->RcompResistor, rcomp_resistor, trailing whitespace
Hello Angel Pons, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#28).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Signed-off-by: Matt Parnell mparnell@gmail.com --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 22 files changed, 1,141 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/28
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 28:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34946/28/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/romstage.c:
https://review.coreboot.org/c/coreboot/+/34946/28/src/mainboard/hp/spectre_x... PS28, Line 79: udelay(10000); long udelay - prefer mdelay; see arch/arm/include/asm/delay.h
https://review.coreboot.org/c/coreboot/+/34946/28/src/mainboard/hp/spectre_x... PS28, Line 91: memcpy(&mem_cfg->RcompResistor, rcomp_resistor, trailing whitespace
Hello Angel Pons, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#29).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Signed-off-by: Matt Parnell mparnell@gmail.com --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 22 files changed, 1,141 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/29
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 29:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34946/29/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/romstage.c:
https://review.coreboot.org/c/coreboot/+/34946/29/src/mainboard/hp/spectre_x... PS29, Line 79: udelay(10000); long udelay - prefer mdelay; see arch/arm/include/asm/delay.h
Hello Angel Pons, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#30).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Signed-off-by: Matt Parnell mparnell@gmail.com --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 22 files changed, 1,131 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/30
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Patch Set 30:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34946/30/src/mainboard/hp/spectre_x... File src/mainboard/hp/spectre_x360_13t_ae000/romstage.c:
https://review.coreboot.org/c/coreboot/+/34946/30/src/mainboard/hp/spectre_x... PS30, Line 55: udelay(10000); long udelay - prefer mdelay; see arch/arm/include/asm/delay.h
https://review.coreboot.org/c/coreboot/+/34946/30/src/mainboard/hp/spectre_x... PS30, Line 77: trailing whitespace
Hello Angel Pons, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34946
to look at the new patch set (#31).
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Signed-off-by: Matt Parnell mparnell@gmail.com --- A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c A src/mainboard/hp/spectre_x360_13t_ae000/spd/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex 22 files changed, 1,131 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/31
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34946?usp=email )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
Felix Singer has restored this change. ( https://review.coreboot.org/c/coreboot/+/34946?usp=email )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Restored
Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34946?usp=email )
Change subject: WIP: add src/mainboard/hp/spectre_x360_13t_ae000 port ......................................................................
Abandoned
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
-
Felix Singer (Code Review)
-
Martin L Roth (Code Review)
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Matt Parnell (Code Review)
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Paul Menzel (Code Review)