coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/cnvi: Deref BTRK as it might not exist
by Sean Rhodes (Code Review) 28 Feb '25

28 Feb '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86450?usp=email ) Change subject: soc/intel/cnvi: Deref BTRK as it might not exist ...................................................................... soc/intel/cnvi: Deref BTRK as it might not exist Check for the existence of BTRK method before attempting to call it, as coreboot doesn't enforce its creation. Change-Id: Ibb0dace635c6a014ce65ae3d1c96a92ff991ce5b Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86450 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 16 insertions(+), 10 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index e0a9566..f082197 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -129,11 +129,13 @@ * If (((PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR) & CNVI_ABORT_REQUEST) == Zero)) * { * Local2 = Zero - * If ((\_SB.PCI0.GBTR() == One)) - * { - * \_SB.PCI0.BTRK (Zero) - * Sleep (105) - * Local2 = One + * If (CondRefOf (\_SB.PCI0.GBTR)) { + * If ((\_SB.PCI0.GBTR() == One)) + * { + * \_SB.PCI0.BTRK (Zero) + * Sleep (105) + * Local2 = One + * } * } * PCRO (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR, CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE) * Sleep (10) @@ -233,14 +235,18 @@ acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); { acpigen_write_store_int_to_op(0, LOCAL2_OP); - acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.GBTR", 1); + acpigen_write_if_cond_ref_of("\\_SB.PCI0.GBTR"); { - acpigen_emit_namestring("\\_SB.PCI0.BTRK"); - acpigen_emit_byte(0); + acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.GBTR", 1); + { + acpigen_emit_namestring("\\_SB.PCI0.BTRK"); + acpigen_emit_byte(0); - acpigen_write_sleep(105); + acpigen_write_sleep(105); - acpigen_write_store_ops(1, LOCAL2_OP); + acpigen_write_store_ops(1, LOCAL2_OP); + } + acpigen_pop_len(); } acpigen_pop_len(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86450?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb0dace635c6a014ce65ae3d1c96a92ff991ce5b Gerrit-Change-Number: 86450 Gerrit-PatchSet: 15 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/intel/common: Add support for WiFi SW RF Kill on CNVi
by Sean Rhodes (Code Review) 28 Feb '25

28 Feb '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86403?usp=email ) Change subject: soc/intel/common: Add support for WiFi SW RF Kill on CNVi ...................................................................... soc/intel/common: Add support for WiFi SW RF Kill on CNVi Hook CNVC and CNVS Methods into the power resource for the CNVi which is provided via the `wifi/generic` driver to allow for WiFi SW RF Kill (low power mode) support. Add corresponding _PS3 and _PS0 Methods, change the power resource to S0 from S5, and rename the power resource from WRST to CNVP for better relevance. Test=boot `starlabs/starlite_adl`, disconnect wireless and verify with inteltool that the WIFI_RF_KILL GPIO is asserted. Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86403 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 98 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index a4263af..e0a9566 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -92,17 +92,30 @@ acpigen_write_name_integer("RSTT", 0); /* - * PowerResource(WRST, 5, 0) + * PowerResource(CNVP, 0, 0) * { * Method(_STA) * { - * Return (0x01) + * If (CondRefOf (\_SB.PCI0.CNVS)) { + * Local0 = \_SB.PCI0.CNVS() + * Return (Local0) + * } + * Else + * { + * Return (0x01) + * } * } * Method(_ON, 0) * { + * If (CondRefOf (\_SB.PCI0.CNVC)) { + * \_SB.PCI0.CNVS(1) + * } * } * Method(_OFF, 0) * { + * If (CondRefOf (\_SB.PCI0.CNVC)) { + * \_SB.PCI0.CNVS(0) + * } * } * Method(_RST, 0, NotSerialized) * { @@ -150,18 +163,46 @@ * } * */ - acpigen_write_power_res("WRST", 5, 0, NULL, 0); + acpigen_write_power_res("CNVP", 0, 0, NULL, 0); { acpigen_write_method("_STA", 0); { - acpigen_write_return_integer(1); + acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVS"); + { + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.PCI0.CNVS"); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_write_return_op(LOCAL0_OP); + } + acpigen_write_else(); + { + acpigen_write_return_integer(1); + } + acpigen_pop_len(); } acpigen_pop_len(); acpigen_write_method("_ON", 0); + { + acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC"); + { + acpigen_emit_namestring("\\_SB.PCI0.CNVC"); + acpigen_emit_byte(1); + } + acpigen_pop_len(); + } acpigen_pop_len(); acpigen_write_method("_OFF", 0); + { + acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC"); + { + acpigen_emit_namestring("\\_SB.PCI0.CNVC"); + acpigen_emit_byte(0); + } + acpigen_pop_len(); + } acpigen_pop_len(); acpigen_write_method("_RST", 0); @@ -266,13 +307,64 @@ /* * Name (_PRR, Package (0x01) * { - * WRST + * CNVP * }) */ acpigen_write_name("_PRR"); { acpigen_write_package(1); - acpigen_emit_namestring("WRST"); + acpigen_emit_namestring("CNVP"); + } + acpigen_pop_len(); + +/* + * Name (_PR0, Package (0x01) + * { + * CNVP + * }) + */ + acpigen_write_name("_PR0"); + { + acpigen_write_package(1); + acpigen_emit_namestring("CNVP"); + } + acpigen_pop_len(); + +/* + * Method (_PS0, 0, NotSerialized) + * { + * If (CondRefOf (\_SB.PCI0.CNVC)) { + * \_SB.PCI0.CNVS(1) + * } + * } + */ + acpigen_write_method("_PS0", 0); + { + acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC"); + { + acpigen_emit_namestring("\\_SB.PCI0.CNVC"); + acpigen_emit_byte(1); + } + acpigen_pop_len(); + } + acpigen_pop_len(); + +/* + * Method (_PS3, 0, NotSerialized) + * { + * If (CondRefOf (\_SB.PCI0.CNVC)) { + * \_SB.PCI0.CNVS(0) + * } + * } + */ + acpigen_write_method("_PS3", 0); + { + acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC"); + { + acpigen_emit_namestring("\\_SB.PCI0.CNVC"); + acpigen_emit_byte(0); + } + acpigen_pop_len(); } acpigen_pop_len(); @@ -306,21 +398,6 @@ acpigen_pop_len(); /* - * Method (_PS0, 0, Serialized) - * { - * } - * - * Method (_PS3, 0, Serialized) - * { - * } - */ - acpigen_write_method_serialized("_PS0", 0); - acpigen_pop_len(); - - acpigen_write_method_serialized("_PS3", 0); - acpigen_pop_len(); - -/* * Method (CFLR, 0, NotSerialized) * { * If (WFLR == One) -- To view, visit https://review.coreboot.org/c/coreboot/+/86403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Gerrit-Change-Number: 86403 Gerrit-PatchSet: 31 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: drivers/wifi/generic: Add Methods to control CNVi enable GPIO
by Sean Rhodes (Code Review) 28 Feb '25

28 Feb '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86402?usp=email ) Change subject: drivers/wifi/generic: Add Methods to control CNVi enable GPIO ...................................................................... drivers/wifi/generic: Add Methods to control CNVi enable GPIO Add two new methods, CNVS and CNVC, that can check and control the enable GPIO for a CNVi module. These will be used by the common code for WiFi SW RF Kill (Low Power Mode). Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86402 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/chip.h 2 files changed, 70 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 7820987..8cab106 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -1181,6 +1181,60 @@ return wifi_acpi_name; } +#if CONFIG(SOC_INTEL_COMMON_BLOCK_CNVI) +static void write_cnvi_control(const struct acpi_gpio *gpio) +{ + + acpigen_write_scope("\\_SB.PCI0"); + +/* + * CNVi Status + * + * Method (CNVS, 0) + * { + * Local0 = \_SB.PCI0.GTXS (gpio) + * Return (Local0) + * } + */ + acpigen_write_method("CNVS", 0); + { + acpigen_get_tx_gpio(gpio); + acpigen_write_return_op(LOCAL0_OP); + } + acpigen_pop_len(); +/* + * CNVi Control + * + * Method (CNVC, 1, NotSerialized) + * { + * If ((Arg0 == One)) + * { + * \_SB.PCI0.STXS (gpio) + * } + * Else + * { + * \_SB.PCI0.CTXS (gpio) + * } + * } + */ + acpigen_write_method("CNVC", 1); + { + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + { + acpigen_enable_tx_gpio(gpio); + } + acpigen_write_else(); + { + acpigen_disable_tx_gpio(gpio); + } + acpigen_pop_len(); + } + acpigen_pop_len(); + + acpigen_write_scope_end(); +} +#endif + void wifi_cnvi_fill_ssdt(const struct device *dev) { const char *path; @@ -1192,4 +1246,10 @@ return; wifi_ssdt_write_properties(dev, path); + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_CNVI) + const struct drivers_wifi_generic_config *config = dev->chip_info; + if (config->cnvi_enable_gpio.pin_count) + write_cnvi_control(&config->cnvi_enable_gpio); +#endif } diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h index 302dd14..f6a68e2 100644 --- a/src/drivers/wifi/generic/chip.h +++ b/src/drivers/wifi/generic/chip.h @@ -3,6 +3,8 @@ #ifndef _WIFI_GENERIC_H_ #define _WIFI_GENERIC_H_ +#include <acpi/acpi_device.h> + /** * struct drivers_wifi_generic_config - Data structure to contain generic wifi config * @wake: Wake pin for ACPI _PRW @@ -20,6 +22,14 @@ */ bool enable_cnvi_ddr_rfim; +#if CONFIG(SOC_INTEL_COMMON_BLOCK_CNVI) + /* + * Enable GPIO for CNVi that will be used for WiFi SW RF Kill (Low + * Power Mode). + */ + struct acpi_gpio cnvi_enable_gpio; +#endif + /* Pointer to the Bluetooth companion device */ DEVTREE_CONST struct device *bluetooth_companion; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/86402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Gerrit-Change-Number: 86402 Gerrit-PatchSet: 26 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Set the MMIO Size to 3GiB
by Sean Rhodes (Code Review) 28 Feb '25

28 Feb '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86623?usp=email ) Change subject: mb/starlabs/starbook/mtl: Set the MMIO Size to 3GiB ...................................................................... mb/starlabs/starbook/mtl: Set the MMIO Size to 3GiB This is required when using 96GB of memory. Change-Id: I3a2a3e737eeb9282a4edf09eb0a24019ceeb016e Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86623 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/mtl/romstage.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c index 7d9b9ae..addcae5 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c @@ -44,4 +44,5 @@ mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8); mupd->FspmConfig.PchHdaSubSystemIds = 0x70381e50; + mupd->FspmConfig.MmioSize = 0xb00; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/86623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a2a3e737eeb9282a4edf09eb0a24019ceeb016e Gerrit-Change-Number: 86623 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Move IOE Bar
by Sean Rhodes (Code Review) 28 Feb '25

28 Feb '25

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86309?usp=email ) Change subject: soc/intel/meteorlake: Move IOE Bar ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/86309?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie29618739d98f0d0c3995a60377083036f23ff18 Gerrit-Change-Number: 86309 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: Kconfig: Place XIP components and FIT at high flash addresses
by Shuo Liu (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Andrey Petrov, Angel Pons, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Ronak Kanabar, Tim Chu, Yu-Ping Wu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email ) Change subject: Kconfig: Place XIP components and FIT at high flash addresses ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86570/comment/78c9bde8_52794f41?us… : PS8, Line 9: CACHE_ROM_SIZE > This makes no sense. […] Sorry, I need to further clarify. Cache as RAM is composed of 2 parts, code and data, which share the total amount of footprint budget. Code part - CodeRegionBase/Length - 16MiB here (UEFI uses 5MiB). Data part - CONFIG_DCACHE_RAM_BASE/CONFIG_DCACHE_RAM_SIZE - ~2MiB. -- To view, visit https://review.coreboot.org/c/coreboot/+/86570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8eb469fdcd18d01652979f28049fe1ea3b59311c Gerrit-Change-Number: 86570 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 07:35:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Xeon ICX-SP support
by Patrick Rudolph (Code Review) 28 Feb '25

28 Feb '25

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85845?usp=email ) Change subject: soc/intel/xeon_sp: Add Xeon ICX-SP support ...................................................................... Abandoned FSP is too broken -- To view, visit https://review.coreboot.org/c/coreboot/+/85845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bb74c0db2c91c87bf623c079f89fd139780160b Gerrit-Change-Number: 85845 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: MAINTAINERS: Drop myself from Xeon-SP
by Patrick Rudolph (Code Review) 28 Feb '25

28 Feb '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86641?usp=email ) Change subject: MAINTAINERS: Drop myself from Xeon-SP ...................................................................... MAINTAINERS: Drop myself from Xeon-SP It's too broken to be maintained. Change-Id: I2c6492f4e37b21bdc2b8d413fb30beaf16403345 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M MAINTAINERS 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/86641/1 diff --git a/MAINTAINERS b/MAINTAINERS index 2ed4e22..8a2b21f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -964,7 +964,6 @@ M: Tim Chu <Tim.Chu(a)quantatw.com> M: Christian Walter <christian.walter(a)9elements.com> M: Shuo Liu <shuo.liu(a)intel.com> -M: Patrick Rudolph <patrick.rudolph(a)9elements.com> M: Lean Sheng Tan <sheng.tan(a)9elements.com> S: Supported F: src/soc/intel/xeon_sp/ -- To view, visit https://review.coreboot.org/c/coreboot/+/86641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c6492f4e37b21bdc2b8d413fb30beaf16403345 Gerrit-Change-Number: 86641 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: Kconfig: Place XIP components and FIT at high flash addresses
by Patrick Rudolph (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Andrey Petrov, Angel Pons, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Ronak Kanabar, Shuo Liu, Tim Chu, Yu-Ping Wu. Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email ) Change subject: Kconfig: Place XIP components and FIT at high flash addresses ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86570/comment/8043fbc9_b75ae6ce?us… : PS8, Line 9: CACHE_ROM_SIZE > GNR is not allowed to use more than 16MiB of cache as RAM, which is conceptually a total amount of 1 […] This makes no sense. I always thought CodeRegionBase/CodeRegionLength would set up a variable MTRR to cache the MMAP SPI flash area. My understanding was that it that CAR is used to set up a separate NEM area. I was wrong all the time... -- To view, visit https://review.coreboot.org/c/coreboot/+/86570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8eb469fdcd18d01652979f28049fe1ea3b59311c Gerrit-Change-Number: 86570 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 07:17:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: Kconfig: Place XIP components and FIT at high flash addresses
by Shuo Liu (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Andrey Petrov, Angel Pons, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Patrick Rudolph, Ronak Kanabar, Tim Chu, Yu-Ping Wu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email ) Change subject: Kconfig: Place XIP components and FIT at high flash addresses ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86570/comment/c2932b70_bad03261?us… : PS8, Line 9: CACHE_ROM_SIZE > Still unclear how CAR has an influence on the cache setup. […] GNR is not allowed to use more than 16MiB of cache as RAM, which is conceptually a total amount of 16MiB cache footprint to be used. For GNR, the cache as RAM is setup by FSP-T as a single continuous range, as below, .FsptCoreUpd = { .MicrocodeRegionBase = 0, .MicrocodeRegionLength = 0, .CodeRegionBase = (UINT64)CACHE_ROM_BASE, .CodeRegionLength = (UINT64)CACHE_ROM_SIZE, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/86570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8eb469fdcd18d01652979f28049fe1ea3b59311c Gerrit-Change-Number: 86570 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 07:03:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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