coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[XS] Change in coreboot[main]: soc/intel/cmn/block/smbus: Keep TCO WDT timeout flag if ACPI_WDAT_WDT=y
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Filip Brozovic, Intel coreboot Reviewers, Paul Menzel. Matt DeVillier has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/84875?usp=email ) Change subject: soc/intel/cmn/block/smbus: Keep TCO WDT timeout flag if ACPI_WDAT_WDT=y ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84875?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d35a8f8bcbcc3aaaadcc936fab028641dfd6e2c Gerrit-Change-Number: 84875 Gerrit-PatchSet: 4 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 22:49:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/intel/cmn/acpi: exclude TPM area range if CRB TPM driver is enabled
by Filip Brozovic (Code Review) 28 Feb '25

28 Feb '25

Filip Brozovic has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84874?usp=email ) Change subject: soc/intel/cmn/acpi: exclude TPM area range if CRB TPM driver is enabled ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16f173ebacbd00b5fea26d2136c9c56ba025f55c Gerrit-Change-Number: 84874 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: [WIP] soc/amd/glinda/Kconfig: Remove TODOs
by Maximilian Brune (Code Review) 28 Feb '25

28 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86672?usp=email ) Change subject: [WIP] soc/amd/glinda/Kconfig: Remove TODOs ...................................................................... [WIP] soc/amd/glinda/Kconfig: Remove TODOs Remove TODOs after verifying they still all apply. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I44bb058a2f3a41bf440261dd840b506829b70fc1 --- M src/soc/amd/glinda/Kconfig 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/86672/1 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 70bdb69..9f64ee7 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -29,7 +29,7 @@ select RTC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACP_GEN2 # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_CPPC # TODO: Check if this is still correct @@ -37,9 +37,9 @@ select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_MADT - select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_APOB + select SOC_AMD_COMMON_BLOCK_APOB_HASH select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH select SOC_AMD_COMMON_BLOCK_DATA_FABRIC @@ -51,29 +51,29 @@ select SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_SPL select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM + select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC - select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/86672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44bb058a2f3a41bf440261dd840b506829b70fc1 Gerrit-Change-Number: 86672 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[M] Change in coreboot[main]: soc/amd/cezanne/acpi: Add ACP MSG0 method
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86466?usp=email ) Change subject: soc/amd/cezanne/acpi: Add ACP MSG0 method ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Gerrit-Change-Number: 86466 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 21:00:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/amd/cezanne/acpi: Add ACP MSG0 method
by Felix Held (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86466?usp=email ) Change subject: soc/amd/cezanne/acpi: Add ACP MSG0 method ...................................................................... Patch Set 4: (1 comment) Patchset: PS1: > not tested yet tested and works as expected -- To view, visit https://review.coreboot.org/c/coreboot/+/86466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Gerrit-Change-Number: 86466 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 20:57:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[S] Change in coreboot[main]: soc/amd/cezanne: Add ACPI opregion to root complex
by Felix Held (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier. Felix Held has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/77682?usp=email ) Change subject: soc/amd/cezanne: Add ACPI opregion to root complex ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/77682/comment/73224e35_50d711a1?us… : PS6, Line 63: Add ACPI device, opregion to host bridge needed for Windows ACP driver. : * : * This provides a mailbox interface for the ACP drivers to notify the PSP : * that the DSP firmware has been loaded, so that the PSP can validate : * the firmware and set the qualifier bit to enable running it. > is this comment still valid? or should we make it more generic? that should probably be reworked a bit. also i'll have to see if CB:86652 should be squashed into it, but still waiting on some test results on that one. i'll try to do the development in upstream, but the testing is done on some out of tree mainboard and right now i need to move there fast, so haven't gotten around to improve the comments and possibly commit messages -- To view, visit https://review.coreboot.org/c/coreboot/+/77682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443 Gerrit-Change-Number: 77682 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 20:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

[S] Change in coreboot[main]: Documentation/lib/rmodules.md: Update simple binary explanation
by Maximilian Brune (Code Review) 28 Feb '25

28 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86656?usp=email ) Change subject: Documentation/lib/rmodules.md: Update simple binary explanation ...................................................................... Documentation/lib/rmodules.md: Update simple binary explanation Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I9cf21b4258758b18f0d3c9316c9aa32cc0d9c44f --- M Documentation/lib/rmodules.md 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/86656/1 diff --git a/Documentation/lib/rmodules.md b/Documentation/lib/rmodules.md index 8a707b8..3ac25a7 100644 --- a/Documentation/lib/rmodules.md +++ b/Documentation/lib/rmodules.md @@ -35,8 +35,24 @@ 1. coreboot stages (postcar, ramstage) 2. simple binaries (smm, smmstub, sipi\_vector) -They are actually handled the same by the build system and only differ -in the fact, that they are either coreboot stages or they are not. +They are handled differently in a 1 important fact. The simple binaries +are compiled into rmodules the same as coreboot stages are, but the +simple bianries are always directly linked to a stage. +Since rmodules are ELF files as well, we can easily link them to the +stages in which we need them (usually postcar or ramstage). +So they are not so much as seperate modules anymore, but still retain +the abillity to accept rmodule\_parameters. +Since the simple binaries are usually very small, linking them directly +into the stage (e.g. ramstage or postcar) avoids having to fetch them +from CBFS and running all that code to fetch a few hundred bytes of +code. So the build system handles them as follows: +1. create rmodule (which is an ELF file) from source files +2. removing all the ELF headers and sections that are not loadable using +`objcopy -O binary` +3. from this, create an object file, which usually has the self invented +.manual file extension, which can be linked to the appropriate stage. +4. add the generated .manual file as "source" file to the stage we want +to link it to. In the end the ELF files will have three different ELF sections, which are all created by the rmodtool. -- To view, visit https://review.coreboot.org/c/coreboot/+/86656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9cf21b4258758b18f0d3c9316c9aa32cc0d9c44f Gerrit-Change-Number: 86656 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Wonkyu Kim (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Zhixing Ma. Wonkyu Kim has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84564?usp=email ) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 28 Feb 2025 20:50:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: drivers/efi/capsules: check for overflows of capsule sizes
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84541?usp=email ) Change subject: drivers/efi/capsules: check for overflows of capsule sizes ...................................................................... drivers/efi/capsules: check for overflows of capsule sizes As was pointed out in comments on CB:83422 [0], the code lacks overflow checks: - when computing size of capsules in a single capsule block - when computing size of capsules in all capsule blocks If an overflow is triggered, the code might allocate a capsule buffer smaller than the data that's going to be written to it leading to overwriting memory after the buffer. [0]: https://review.coreboot.org/c/coreboot/+/83422 Change-Id: I43d17d77197fc2cbd721d47941101551603c352a Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84541 Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/efi/capsules.c 1 file changed, 15 insertions(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Krystian Hebel: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/efi/capsules.c b/src/drivers/efi/capsules.c index e674e33..38178c6 100644 --- a/src/drivers/efi/capsules.c +++ b/src/drivers/efi/capsules.c @@ -344,7 +344,15 @@ goto error; } - data_size += ALIGN_UP(capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT); + uint64_t capsule_size = + ALIGN_UP((uint64_t)capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT); + if (data_size + capsule_size < data_size) { /* overflow detection */ + printk(BIOS_ERR, + "capsules: capsules block size is too large (%#llx + %#llx) for uint64.\n", + data_size, capsule_size); + goto error; + } + data_size += capsule_size; uint32_t size_left = capsule_hdr->CapsuleImageSize; while (size_left != 0) { @@ -384,6 +392,12 @@ } /* Increase the size only on successful parsing of the capsule block. */ + if (*total_data_size + data_size < *total_data_size) { /* overflow detection */ + printk(BIOS_ERR, + "capsules: total capsule's size is too large (%#llx + %#llx) for uint64.\n", + *total_data_size, data_size); + goto error; + } *total_data_size += data_size; return block; -- To view, visit https://review.coreboot.org/c/coreboot/+/84541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43d17d77197fc2cbd721d47941101551603c352a Gerrit-Change-Number: 84541 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/hp/pro_3x00_series: Remove unused ACPI brightness control
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85847?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/hp/pro_3x00_series: Remove unused ACPI brightness control ...................................................................... mb/hp/pro_3x00_series: Remove unused ACPI brightness control These lines are not needed because this mainboard does not have an integrated display to control. Tested on HP Pro 3400 Series. Change-Id: Id39cd18713cc596eb2c92e028dad480fe7de8ef2 Signed-off-by: Vesek <venda.straka(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85847 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/hp/pro_3x00_series/dsdt.asl 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/hp/pro_3x00_series/dsdt.asl b/src/mainboard/hp/pro_3x00_series/dsdt.asl index cee4939..9b86d2a 100644 --- a/src/mainboard/hp/pro_3x00_series/dsdt.asl +++ b/src/mainboard/hp/pro_3x00_series/dsdt.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #include <acpi/acpi.h> DefinitionBlock( @@ -23,7 +21,6 @@ Device (\_SB.PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85847?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id39cd18713cc596eb2c92e028dad480fe7de8ef2 Gerrit-Change-Number: 85847 Gerrit-PatchSet: 6 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025