coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: Doc/mb/hp: Rename pro_3500_series to pro_3x00 series
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85846?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Doc/mb/hp: Rename pro_3500_series to pro_3x00 series ...................................................................... Doc/mb/hp: Rename pro_3500_series to pro_3x00 series The pro_3500_series was converted to a variant to include the Pro 3400, so rename the corresponding documentation. Change-Id: I5977f223d6f004a801e163397d1c97febd7ee1d4 Signed-off-by: Vesek <venda.straka(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85846 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- R Documentation/mainboard/hp/pro_3x00_series.md R Documentation/mainboard/hp/pro_3x00_series_flash.avif R Documentation/mainboard/hp/pro_3x00_series_jumper.avif M Documentation/mainboard/index.md 4 files changed, 3 insertions(+), 3 deletions(-) Approvals: Angel Pons: Looks good to me, approved Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/mainboard/hp/pro_3500_series.md b/Documentation/mainboard/hp/pro_3x00_series.md similarity index 97% rename from Documentation/mainboard/hp/pro_3500_series.md rename to Documentation/mainboard/hp/pro_3x00_series.md index 3280066..a92c4f5 100644 --- a/Documentation/mainboard/hp/pro_3500_series.md +++ b/Documentation/mainboard/hp/pro_3x00_series.md @@ -71,7 +71,7 @@ from the OS. **Position of FDO jumper (E2) close to the F_USB3** -![FDO jumper position](pro_3500_series_jumper.avif) +![FDO jumper position](pro_3x00_series_jumper.avif) ### External programming @@ -83,7 +83,7 @@ until cleanly power cycled. **Position of SOIC-8 flash and pin-header near ATX power connector** -![Flash position](pro_3500_series_flash.avif) +![Flash position](pro_3x00_series_flash.avif) ## Technology diff --git a/Documentation/mainboard/hp/pro_3500_series_flash.avif b/Documentation/mainboard/hp/pro_3x00_series_flash.avif similarity index 100% rename from Documentation/mainboard/hp/pro_3500_series_flash.avif rename to Documentation/mainboard/hp/pro_3x00_series_flash.avif Binary files differ diff --git a/Documentation/mainboard/hp/pro_3500_series_jumper.avif b/Documentation/mainboard/hp/pro_3x00_series_jumper.avif similarity index 100% rename from Documentation/mainboard/hp/pro_3500_series_jumper.avif rename to Documentation/mainboard/hp/pro_3x00_series_jumper.avif Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 177abff..f2be295 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -139,7 +139,7 @@ Compaq 8200 Elite SFF <hp/compaq_8200_sff.md> Compaq 8300 Elite SFF <hp/compaq_8300_sff.md> Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md> -Pro 3x00 Series <hp/pro_3500_series.md> +Pro 3x00 Series <hp/pro_3x00_series.md> Z220 Workstation SFF <hp/z220_sff.md> ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5977f223d6f004a801e163397d1c97febd7ee1d4 Gerrit-Change-Number: 85846 Gerrit-PatchSet: 6 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/hp: Add Pro 3400
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85825?usp=email ) Change subject: mb/hp: Add Pro 3400 ...................................................................... mb/hp: Add Pro 3400 Based on autoport and HP Pro 3500. As part of this change renamed 3500 to 3x00 and added this as it's variant. It's an almost identical board to the 3500 but has a smaller flash. Other differences between boards were identified by autoport. They may or may not important but were included anyway. Tested on HP Pro 3400, behaves exactly as 3500 described in the docs. Changes were not significant enough to require retesting on 3500. Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387 Signed-off-by: Vesek <venda.straka(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85825 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/mainboard/hp/pro_3500_series.md M Documentation/mainboard/index.md D src/mainboard/hp/pro_3500_series/Kconfig A src/mainboard/hp/pro_3x00_series/Kconfig R src/mainboard/hp/pro_3x00_series/Kconfig.name R src/mainboard/hp/pro_3x00_series/Makefile.mk R src/mainboard/hp/pro_3x00_series/acpi/ec.asl R src/mainboard/hp/pro_3x00_series/acpi/platform.asl R src/mainboard/hp/pro_3x00_series/acpi/superio.asl R src/mainboard/hp/pro_3x00_series/acpi_tables.c A src/mainboard/hp/pro_3x00_series/board_info.txt A src/mainboard/hp/pro_3x00_series/cmos.default A src/mainboard/hp/pro_3x00_series/cmos.layout R src/mainboard/hp/pro_3x00_series/common_defines.h R src/mainboard/hp/pro_3x00_series/devicetree.cb R src/mainboard/hp/pro_3x00_series/dsdt.asl R src/mainboard/hp/pro_3x00_series/early_init.c R src/mainboard/hp/pro_3x00_series/gma-mainboard.ads R src/mainboard/hp/pro_3x00_series/hda_verb.c R src/mainboard/hp/pro_3x00_series/led.c R src/mainboard/hp/pro_3x00_series/led.h R src/mainboard/hp/pro_3x00_series/mainboard.c R src/mainboard/hp/pro_3x00_series/smihandler.c C src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt A src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/data.vbt A src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c A src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb R src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/board_info.txt R src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/data.vbt R src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/gpio.c A src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb 31 files changed, 421 insertions(+), 96 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/mainboard/hp/pro_3500_series.md b/Documentation/mainboard/hp/pro_3500_series.md index 881bf37..3280066 100644 --- a/Documentation/mainboard/hp/pro_3500_series.md +++ b/Documentation/mainboard/hp/pro_3500_series.md @@ -1,43 +1,53 @@ -# HP Pro 3500 Series +# HP Pro 3x00 Series -This page describes how to run coreboot on the [Pro 3500 Series] -desktop from [HP]. +This page describes how to run coreboot on the [Pro 3400 Series] and [Pro 3500 Series] +desktops from [HP]. ## State All peripherals should work. Automatic fan control as well as S3 are working. The board was tested to boot Linux and Windows. EHCI debug -is untested. When using MrChromebox edk2 with secure boot build in, the -board will hang on each boot for about 20 seconds before continuing. -With disabled ME, the SuperIO will not get CPU temperatures via PECI and -therefore the automatic fan control will not increase the fan speed. +is untested. With disabled ME, the SuperIO will not get CPU +temperatures via PECI and therefore the automatic fan control +will not increase the fan speed. ## Flashing coreboot ```{eval-rst} -+---------------------+-------------------------+ -| Type | Value | -+=====================+=========================+ -| Socketed flash | No | -+---------------------+-------------------------+ -| Model | W25Q64FVSIG | -+---------------------+-------------------------+ -| Size | 8 MiB | -+---------------------+-------------------------+ -| In circuit flashing | Yes | -+---------------------+-------------------------+ -| Package | SOIC-8 | -+---------------------+-------------------------+ -| Write protection | See below | -+---------------------+-------------------------+ -| Dual BIOS feature | No | -+---------------------+-------------------------+ -| Internal flashing | Yes | -+---------------------+-------------------------+ ++---------------------+-----------------------------------------+ +| Type | Value | ++=====================+=========================================+ +| Socketed flash | No | ++---------------------+-----------------------------------------+ +| Model | W25Q32BVSIG (3400) / W25Q64FVSIG (3500) | ++---------------------+-----------------------------------------+ +| Size | 4 MiB (3400) / 8 MiB (3500) | ++---------------------+-----------------------------------------+ +| In circuit flashing | Yes | ++---------------------+-----------------------------------------+ +| Package | SOIC-8 | ++---------------------+-----------------------------------------+ +| Write protection | See below | ++---------------------+-----------------------------------------+ +| Dual BIOS feature | No | ++---------------------+-----------------------------------------+ +| Internal flashing | Yes | ++---------------------+-----------------------------------------+ ``` ### Flash layout The original layout of the flash should look like this: + +#### Pro 3400 +``` +00000000:00000fff fd +00180000:003fffff bios +00001000:0017ffff me +00fff000:00000fff gbe +00fff000:00000fff pd +``` + +#### Pro 3500 ``` 00000000:00000fff fd 00400000:007fffff bios @@ -48,8 +58,7 @@ ### Internal programming -The SPI flash can be accessed using [flashrom] (although it reports as -"N25Q064..3E", it works fine). +The SPI flash can be accessed using [flashrom]. With a missing FDO jumper, `fd` region is read-only, `bios` region is read-write and `me` region is locked. Vendor firmware will additionally @@ -62,9 +71,7 @@ from the OS. **Position of FDO jumper (E2) close to the F_USB3** -![][pro_3500_jumper] - -[pro_3500_jumper]: pro_3500_series_jumper.avif +![FDO jumper position](pro_3500_series_jumper.avif) ### External programming @@ -76,9 +83,7 @@ until cleanly power cycled. **Position of SOIC-8 flash and pin-header near ATX power connector** -![][pro_3500_flash] - -[pro_3500_flash]: pro_3500_series_flash.avif +![Flash position](pro_3500_series_flash.avif) ## Technology @@ -98,6 +103,7 @@ +------------------+--------------------------------------------------+ ``` -[Pro 3500 Series]: https://support.hp.com/us-en/document/c03364089 +[Pro 3400 Series]: https://support.hp.com/us-en/product/details/hp-pro-3400-microtower-pc/5160… +[Pro 3500 Series]: https://support.hp.com/us-en/product/details/hp-pro-3500-microtower-pc/5270… [HP]: https://www.hp.com/ [flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 518c02a..177abff 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -139,7 +139,7 @@ Compaq 8200 Elite SFF <hp/compaq_8200_sff.md> Compaq 8300 Elite SFF <hp/compaq_8300_sff.md> Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md> -Pro 3500 Series <hp/pro_3500_series.md> +Pro 3x00 Series <hp/pro_3500_series.md> Z220 Workstation SFF <hp/z220_sff.md> ``` diff --git a/src/mainboard/hp/pro_3500_series/Kconfig b/src/mainboard/hp/pro_3500_series/Kconfig deleted file mode 100644 index ab77654..0000000 --- a/src/mainboard/hp/pro_3500_series/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -if BOARD_HP_PRO_3500_SERIES - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_USES_IFD_GBE_REGION - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select NO_UART_ON_SUPERIO - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_BD82X6X - select SUPERIO_ITE_IT8772F - select USE_NATIVE_RAMINIT - -config CBFS_SIZE - default 0x400000 - -config MAINBOARD_DIR - default "hp/pro_3500_series" - -config MAINBOARD_PART_NUMBER - default "Pro 3500 Series" - -config VGA_BIOS_ID - default "8086,0152" - -config DRAM_RESET_GATE_GPIO - default 60 - -config USBDEBUG_HCD_INDEX - default 2 -endif diff --git a/src/mainboard/hp/pro_3x00_series/Kconfig b/src/mainboard/hp/pro_3x00_series/Kconfig new file mode 100644 index 0000000..47f24db --- /dev/null +++ b/src/mainboard/hp/pro_3x00_series/Kconfig @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_HP_PRO_3X00_SERIES_COMMON + def_bool n + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select NO_UART_ON_SUPERIO + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_ITE_IT8772F + select USE_NATIVE_RAMINIT + +config BOARD_HP_PRO_3400_SERIES + select BOARD_HP_PRO_3X00_SERIES_COMMON + select BOARD_ROMSIZE_KB_4096 + +config BOARD_HP_PRO_3500_SERIES + select BOARD_HP_PRO_3X00_SERIES_COMMON + select BOARD_ROMSIZE_KB_8192 + +if BOARD_HP_PRO_3X00_SERIES_COMMON + +config CBFS_SIZE + default 0x200000 if BOARD_ROMSIZE_KB_4096 + default 0x400000 if BOARD_ROMSIZE_KB_8192 + +config MAINBOARD_DIR + default "hp/pro_3x00_series" + +config VARIANT_DIR + default "pro_3400_series" if BOARD_HP_PRO_3400_SERIES + default "pro_3500_series" if BOARD_HP_PRO_3500_SERIES + +config MAINBOARD_PART_NUMBER + default "Pro 3400 Series" if BOARD_HP_PRO_3400_SERIES + default "Pro 3500 Series" if BOARD_HP_PRO_3500_SERIES + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config USBDEBUG_HCD_INDEX + default 2 +endif diff --git a/src/mainboard/hp/pro_3500_series/Kconfig.name b/src/mainboard/hp/pro_3x00_series/Kconfig.name similarity index 64% rename from src/mainboard/hp/pro_3500_series/Kconfig.name rename to src/mainboard/hp/pro_3x00_series/Kconfig.name index fd1222c..fea2e4f 100644 --- a/src/mainboard/hp/pro_3500_series/Kconfig.name +++ b/src/mainboard/hp/pro_3x00_series/Kconfig.name @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later +config BOARD_HP_PRO_3400_SERIES + bool "Pro 3400 Series" + config BOARD_HP_PRO_3500_SERIES bool "Pro 3500 Series" diff --git a/src/mainboard/hp/pro_3500_series/Makefile.mk b/src/mainboard/hp/pro_3x00_series/Makefile.mk similarity index 69% rename from src/mainboard/hp/pro_3500_series/Makefile.mk rename to src/mainboard/hp/pro_3x00_series/Makefile.mk index 6554ed5..bc01687 100644 --- a/src/mainboard/hp/pro_3500_series/Makefile.mk +++ b/src/mainboard/hp/pro_3x00_series/Makefile.mk @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += early_init.c -bootblock-y += gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c bootblock-y += led.c romstage-y += early_init.c -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/pro_3500_series/acpi/ec.asl b/src/mainboard/hp/pro_3x00_series/acpi/ec.asl similarity index 100% rename from src/mainboard/hp/pro_3500_series/acpi/ec.asl rename to src/mainboard/hp/pro_3x00_series/acpi/ec.asl diff --git a/src/mainboard/hp/pro_3500_series/acpi/platform.asl b/src/mainboard/hp/pro_3x00_series/acpi/platform.asl similarity index 100% rename from src/mainboard/hp/pro_3500_series/acpi/platform.asl rename to src/mainboard/hp/pro_3x00_series/acpi/platform.asl diff --git a/src/mainboard/hp/pro_3500_series/acpi/superio.asl b/src/mainboard/hp/pro_3x00_series/acpi/superio.asl similarity index 100% rename from src/mainboard/hp/pro_3500_series/acpi/superio.asl rename to src/mainboard/hp/pro_3x00_series/acpi/superio.asl diff --git a/src/mainboard/hp/pro_3500_series/acpi_tables.c b/src/mainboard/hp/pro_3x00_series/acpi_tables.c similarity index 100% rename from src/mainboard/hp/pro_3500_series/acpi_tables.c rename to src/mainboard/hp/pro_3x00_series/acpi_tables.c diff --git a/src/mainboard/hp/pro_3x00_series/board_info.txt b/src/mainboard/hp/pro_3x00_series/board_info.txt new file mode 100644 index 0000000..7114c27 --- /dev/null +++ b/src/mainboard/hp/pro_3x00_series/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +ROM package: SOIC-8 +ROM socketed: no +Flashrom support: yes +Release year: 2011-2012 diff --git a/src/mainboard/hp/pro_3x00_series/cmos.default b/src/mainboard/hp/pro_3x00_series/cmos.default new file mode 100644 index 0000000..7c313be --- /dev/null +++ b/src/mainboard/hp/pro_3x00_series/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +gfx_uma_size=64M +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI diff --git a/src/mainboard/hp/pro_3x00_series/cmos.layout b/src/mainboard/hp/pro_3x00_series/cmos.layout new file mode 100644 index 0000000..e6dba00 --- /dev/null +++ b/src/mainboard/hp/pro_3x00_series/cmos.layout @@ -0,0 +1,68 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# start-bit length config enum-ID name +0 384 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +412 3 e 7 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +6 0 AHCI +6 1 Compatible + +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/hp/pro_3500_series/common_defines.h b/src/mainboard/hp/pro_3x00_series/common_defines.h similarity index 100% rename from src/mainboard/hp/pro_3500_series/common_defines.h rename to src/mainboard/hp/pro_3x00_series/common_defines.h diff --git a/src/mainboard/hp/pro_3500_series/devicetree.cb b/src/mainboard/hp/pro_3x00_series/devicetree.cb similarity index 90% rename from src/mainboard/hp/pro_3500_series/devicetree.cb rename to src/mainboard/hp/pro_3x00_series/devicetree.cb index 3d9cf61..cf75313 100644 --- a/src/mainboard/hp/pro_3500_series/devicetree.cb +++ b/src/mainboard/hp/pro_3x00_series/devicetree.cb @@ -22,22 +22,6 @@ register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - register "usb_port_config" = "{ - { 1, 6, 0 }, - { 1, 6, 0 }, - { 1, 6, 1 }, - { 1, 9, 1 }, - { 1, 10, 2 }, - { 1, 11, 2 }, - { 1, 6, 3 }, - { 1, 6, 3 }, - { 1, 6, 4 }, - { 1, 12, 4 }, - { 1, 6, 6 }, - { 1, 11, 5 }, - { 1, 6, 5 }, - { 1, 6, 6 }, - }" device ref ehci2 on end device ref hda on end device ref pcie_rp2 on end # MINI_PCIE diff --git a/src/mainboard/hp/pro_3500_series/dsdt.asl b/src/mainboard/hp/pro_3x00_series/dsdt.asl similarity index 99% rename from src/mainboard/hp/pro_3500_series/dsdt.asl rename to src/mainboard/hp/pro_3x00_series/dsdt.asl index cbdf0c6..cee4939 100644 --- a/src/mainboard/hp/pro_3500_series/dsdt.asl +++ b/src/mainboard/hp/pro_3x00_series/dsdt.asl @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - - #include <acpi/acpi.h> DefinitionBlock( diff --git a/src/mainboard/hp/pro_3500_series/early_init.c b/src/mainboard/hp/pro_3x00_series/early_init.c similarity index 100% rename from src/mainboard/hp/pro_3500_series/early_init.c rename to src/mainboard/hp/pro_3x00_series/early_init.c diff --git a/src/mainboard/hp/pro_3500_series/gma-mainboard.ads b/src/mainboard/hp/pro_3x00_series/gma-mainboard.ads similarity index 100% rename from src/mainboard/hp/pro_3500_series/gma-mainboard.ads rename to src/mainboard/hp/pro_3x00_series/gma-mainboard.ads diff --git a/src/mainboard/hp/pro_3500_series/hda_verb.c b/src/mainboard/hp/pro_3x00_series/hda_verb.c similarity index 100% rename from src/mainboard/hp/pro_3500_series/hda_verb.c rename to src/mainboard/hp/pro_3x00_series/hda_verb.c diff --git a/src/mainboard/hp/pro_3500_series/led.c b/src/mainboard/hp/pro_3x00_series/led.c similarity index 100% rename from src/mainboard/hp/pro_3500_series/led.c rename to src/mainboard/hp/pro_3x00_series/led.c diff --git a/src/mainboard/hp/pro_3500_series/led.h b/src/mainboard/hp/pro_3x00_series/led.h similarity index 100% rename from src/mainboard/hp/pro_3500_series/led.h rename to src/mainboard/hp/pro_3x00_series/led.h diff --git a/src/mainboard/hp/pro_3500_series/mainboard.c b/src/mainboard/hp/pro_3x00_series/mainboard.c similarity index 100% rename from src/mainboard/hp/pro_3500_series/mainboard.c rename to src/mainboard/hp/pro_3x00_series/mainboard.c diff --git a/src/mainboard/hp/pro_3500_series/smihandler.c b/src/mainboard/hp/pro_3x00_series/smihandler.c similarity index 100% rename from src/mainboard/hp/pro_3500_series/smihandler.c rename to src/mainboard/hp/pro_3x00_series/smihandler.c diff --git a/src/mainboard/hp/pro_3500_series/board_info.txt b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt similarity index 66% copy from src/mainboard/hp/pro_3500_series/board_info.txt copy to src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt index 1780394..9a9d75d 100644 --- a/src/mainboard/hp/pro_3500_series/board_info.txt +++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt @@ -1,6 +1,5 @@ Category: desktop ROM package: SOIC-8 -ROM protocol: SPI ROM socketed: n Flashrom support: y -Release year: 2012 +Release year: 2011 diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/data.vbt b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/data.vbt new file mode 100644 index 0000000..b7cb35a --- /dev/null +++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/data.vbt Binary files differ diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c new file mode 100644 index 0000000..bac321c --- /dev/null +++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_LOW, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb new file mode 100644 index 0000000..fbbdbf6 --- /dev/null +++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "usb_port_config" = "{ + { 0, 6, -1 }, + { 1, 6, 0 }, + { 1, 6, 0 }, + { 1, 6, 1 }, + { 1, 6, 1 }, + { 1, 6, 2 }, + { 0, 6, -1 }, + { 0, 6, -1 }, + { 1, 12, 5 }, + { 1, 12, 5 }, + { 1, 12, 6 }, + { 1, 12, 6 }, + { 0, 6, -1 }, + { 0, 6, -1 }, + }" + + # Dummy device, sconfig requires at least one device per chip + device ref ehci1 on end + end + end +end diff --git a/src/mainboard/hp/pro_3500_series/board_info.txt b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/board_info.txt similarity index 83% rename from src/mainboard/hp/pro_3500_series/board_info.txt rename to src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/board_info.txt index 1780394..5ddb210 100644 --- a/src/mainboard/hp/pro_3500_series/board_info.txt +++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/board_info.txt @@ -1,6 +1,5 @@ Category: desktop ROM package: SOIC-8 -ROM protocol: SPI ROM socketed: n Flashrom support: y Release year: 2012 diff --git a/src/mainboard/hp/pro_3500_series/data.vbt b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/data.vbt similarity index 100% rename from src/mainboard/hp/pro_3500_series/data.vbt rename to src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/data.vbt Binary files differ diff --git a/src/mainboard/hp/pro_3500_series/gpio.c b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/gpio.c similarity index 100% rename from src/mainboard/hp/pro_3500_series/gpio.c rename to src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/gpio.c diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb new file mode 100644 index 0000000..9e9fa86 --- /dev/null +++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "usb_port_config" = "{ + { 1, 6, 0 }, + { 1, 6, 0 }, + { 1, 6, 1 }, + { 1, 9, 1 }, + { 1, 10, 2 }, + { 1, 11, 2 }, + { 1, 6, 3 }, + { 1, 6, 3 }, + { 1, 6, 4 }, + { 1, 12, 4 }, + { 1, 6, 6 }, + { 1, 11, 5 }, + { 1, 6, 5 }, + { 1, 6, 6 }, + }" + + # Dummy device, sconfig requires at least one device per chip + device ref ehci1 on end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/85825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387 Gerrit-Change-Number: 85825 Gerrit-PatchSet: 13 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86593?usp=email ) Change subject: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence ...................................................................... mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence Move SSD enable/reset pins to romstage to have more time for initialization. BUG=b:398070426 BRANCH=None TEST=Build francka and do EC reset to check the SSD boots to OS successfully Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640 Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86593 Reviewed-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/francka/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Ian Feng: Looks good to me, approved Dtrain Hsu: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c index 6265b16..f2868fc 100644 --- a/src/mainboard/google/fatcat/variants/francka/gpio.c +++ b/src/mainboard/google/fatcat/variants/francka/gpio.c @@ -416,6 +416,8 @@ /* Pad configuration in romstage */ static const struct pad_config romstage_gpio_table[] = { + /* GPP_B16: SOC_SSD2_EN */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPP_C00: SOC_SMBCLK */ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* GPP_C01: SOC_SMBDATA */ @@ -424,6 +426,8 @@ PAD_CFG_GPO(GPP_H03, 0, DEEP), /* GPP_H17: FP_RST_1V8_OD# */ PAD_CFG_GPO(GPP_H17, 0, DEEP), + /* GPP_E03: SOC_SSD2_RST# */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/86593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640 Gerrit-Change-Number: 86593 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/amd/common: Support sbin ucode files
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68122?usp=email ) Change subject: soc/amd/common: Support sbin ucode files ...................................................................... soc/amd/common: Support sbin ucode files Recent PI releases have been distributing the ucode patch files as sbin files instead of bin files. The sbin uses a 256 byte amd_fw_header to wrap the bin file. Offset 0x14 of the header is the size field. The can be extracted with od to get the size of the ucode bin file. The bin file can then be extracted with dd and placed in the build directory for inclusion as a cbfs file. In the case where both an sbin and bin ucode file are present, the bin file will be added and a note will print at the start of the build about the sbin file being skipped. TEST=builds with only bin, only sbin, non-matching bin and sbin, matching bin and sbin files Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/68122 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/Makefile.mk M src/soc/amd/common/block/cpu/Makefile.mk 2 files changed, 45 insertions(+), 13 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk index 626260f..a030687 100644 --- a/src/soc/amd/common/Makefile.mk +++ b/src/soc/amd/common/Makefile.mk @@ -38,8 +38,6 @@ DEP_FILES = $(patsubst %,$(FIRMWARE_LOCATION)/%, $(AMDFW_CFG_IN_FW_LOC)) \ $(AMDFW_CFG_WITH_PATH) -amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*U?odePatch*.bin) - ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) $(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h cp $< $@ diff --git a/src/soc/amd/common/block/cpu/Makefile.mk b/src/soc/amd/common/block/cpu/Makefile.mk index 1c4331c..ea40801 100644 --- a/src/soc/amd/common/block/cpu/Makefile.mk +++ b/src/soc/amd/common/block/cpu/Makefile.mk @@ -9,18 +9,52 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y) -define add-ucode-as-cbfs -$(if $(value cpu_microcode_$(2).bin-file),$(info File1: $(cpu_microcode_$(2).bin-file)) $(info File2: $(1)) $(error Error: The cbfs filename "cpu_microcode_$(2).bin" is used for both above files. Check your microcode patches for duplicates.)) -cbfs-files-y += cpu_microcode_$(2).bin -cpu_microcode_$(2).bin-file := $(1) -cpu_microcode_$(2).bin-type := microcode -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) -cpu_microcode_$(2).bin-align := 64 -else -cpu_microcode_$(2).bin-align := 16 +define add-ucode-as-cbfs + +# check for duplicate microcode files. Same sbin and bin ucode is allowed here though, because mendocino has a duplicate. +ifeq ($(cpu_microcode_$(2).bin-file), $(obj)/cpu_microcode_$(2).$(3)) + $$(info Tried to add ucode: $(1)) + $$(error Error: The cbfs filename "cpu_microcode_$(2).bin" is already used. Check your microcode patches for duplicates.) endif + +# offset 0x14 contains the size of the unwrapped ucode file +# .sbin files contain a 256 wrapper around the usual microcode file +$(obj)/cpu_microcode_$(2).$(3): $(1) + echo $$< "->" $$@ + if [ $(3) = "bin" ]; then \ + cp $$< $$@; \ + elif [ $(3) = "sbin" ]; then \ + size=$$$$(od --endian little --address-radix n --read-bytes 4 --skip-bytes 0x14 --format u4 $$<); \ + dd status=none ibs=1 skip=256 count=$$$$((size)) if=$$< of=$$@; \ + fi + +# if there is both a sbin and bin microcode only include the bin one to keep the old behaviour +ifeq ($(cpu_microcode_$(2).bin-file),) + cbfs-files-y += cpu_microcode_$(2).bin + cpu_microcode_$(2).bin-file := $(obj)/cpu_microcode_$(2).$(3) + cpu_microcode_$(2).bin-type := microcode + + ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) + cpu_microcode_$(2).bin-align := 64 + else + cpu_microcode_$(2).bin-align := 16 + endif +endif + endef -$(foreach ucode,$(amd_microcode_bins),$(eval $(call add-ucode-as-cbfs,$(ucode),$(shell hexdump -n 2 -s 0x18 -e '"%x"' $(ucode))))) -endif +amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*U?odePatch*.bin) +amd_microcode_sbins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.sbin) + +# Function to grab bytes from a file and format them as desired +# $(call extract-bytes,filename,bytes-to-read,offset-to-bytes,output-format) +extract-bytes = $(shell echo $(shell od --endian little --address-radix n --read-bytes $(2) --skip-bytes $(3) --format $(4) $(1))) + +$(foreach ucode, $(amd_microcode_bins), \ + $(eval $(call add-ucode-as-cbfs,$(ucode),$(call extract-bytes,$(ucode),2,0x18,x2),bin))) + +$(foreach ucode, $(amd_microcode_sbins), \ + $(eval $(call add-ucode-as-cbfs,$(ucode),$(call extract-bytes,$(ucode),2,0x118,x2),sbin))) + +endif #ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/68122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae Gerrit-Change-Number: 68122 Gerrit-PatchSet: 11 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/emulation/qemu-riscv: Add support for 512 harts
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81083?usp=email ) Change subject: mb/emulation/qemu-riscv: Add support for 512 harts ...................................................................... mb/emulation/qemu-riscv: Add support for 512 harts QEMU has a maximum of 512 of emulated harts supported. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I149c8d8a43733c8ba3e02a84b0a3606d98f8b2c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81083 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-by: Carlos López <carlos.lopezr4096(a)gmail.com> --- M src/commonlib/Makefile.mk M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.mk M src/mainboard/emulation/qemu-riscv/memlayout.ld A src/mainboard/emulation/qemu-riscv/smp.c 5 files changed, 36 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved Carlos López: Looks good to me, but someone else must approve Alicja Michalska: Looks good to me, but someone else must approve diff --git a/src/commonlib/Makefile.mk b/src/commonlib/Makefile.mk index a274d5f..91648c5 100644 --- a/src/commonlib/Makefile.mk +++ b/src/commonlib/Makefile.mk @@ -32,6 +32,7 @@ endif ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c +bootblock-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c romstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 9b5a6f0..286e684 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -26,6 +26,7 @@ select FLATTENED_DEVICE_TREE select MISSING_BOARD_RESET select DRIVERS_UART_8250MEM + select RISCV_GET_HART_COUNT_AT_RUNTIME select RISCV_HAS_OPENSBI select ARCH_RISCV_S select ARCH_RISCV_U @@ -35,6 +36,7 @@ select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV select RISCV_USE_ARCH_TIMER + select FLATTENED_DEVICE_TREE config MEMLAYOUT_LD_FILE string @@ -48,7 +50,7 @@ config MAX_CPUS int - default 1 + default 512 # QEMUs current limit for the virt target config RISCV_ARCH string diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk index bed0f80..0f240aa 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.mk +++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk @@ -4,12 +4,14 @@ bootblock-y += uart.c bootblock-y += rom_media.c bootblock-y += clint.c +bootblock-y += smp.c romstage-y += cbmem.c romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c romstage-y += clint.c +romstage-y += smp.c ramstage-y += mainboard.c ramstage-y += uart.c @@ -17,5 +19,6 @@ ramstage-y += clint.c ramstage-y += cbmem.c ramstage-y += chip.c +ramstage-y += smp.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 9c16496..9a52ec2 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -16,5 +16,5 @@ PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M, 8K) FMAP_CACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K, 2K) CBFS_MCACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K, 10K) - STACK(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K + 10K, 4M) + STACK(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K + 10K, 4K * CONFIG_MAX_CPUS) } diff --git a/src/mainboard/emulation/qemu-riscv/smp.c b/src/mainboard/emulation/qemu-riscv/smp.c new file mode 100644 index 0000000..b6dce47 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/smp.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mcall.h> +#include <arch/smp/smp.h> +#include <commonlib/device_tree.h> +#include <console/console.h> + +unsigned int smp_get_hart_count(void) +{ + if (!fdt_is_valid(HLS()->fdt)) + goto error; + + uint32_t cpus_offset = fdt_find_node_by_path(HLS()->fdt, "/cpus", NULL, NULL); + if (!cpus_offset) + goto error; + + static u32 harts[CONFIG_MAX_CPUS]; // too big for the stack + size_t count_harts = fdt_find_subnodes_by_prefix(HLS()->fdt, cpus_offset, "cpu@", + NULL, NULL, harts, CONFIG_MAX_CPUS); + if (!count_harts) + goto error; + + printk(BIOS_DEBUG, "found %zu harts in devicetree\n", count_harts); + return count_harts; +error: + printk(BIOS_ERR, "%s: Failed to read devicetree to get number of harts\n", __func__); + return 1; // Return single hart on failure to keep booting +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I149c8d8a43733c8ba3e02a84b0a3606d98f8b2c1 Gerrit-Change-Number: 81083 Gerrit-PatchSet: 9 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>

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[XS] Change in coreboot[main]: mb/trulo: Add host event EC_HOST_EVENT_BODY_DETECT_CHANGE
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86615?usp=email ) Change subject: mb/trulo: Add host event EC_HOST_EVENT_BODY_DETECT_CHANGE ...................................................................... mb/trulo: Add host event EC_HOST_EVENT_BODY_DETECT_CHANGE Add host event EC_HOST_EVENT_BODY_DETECT_CHANGE for trulo. BRANCH=firmware-trulo-15217.771.B BUG=b:394177292 TEST=bodydetectmode on|off, verify host event is received Change-Id: Ifac0460e0e8feb33ad0085d250928adb593bb8ca Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86615 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h index 3d2fc5a..5bf2995 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h @@ -22,7 +22,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BODY_DETECT_CHANGE)) #define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) -- To view, visit https://review.coreboot.org/c/coreboot/+/86615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifac0460e0e8feb33ad0085d250928adb593bb8ca Gerrit-Change-Number: 86615 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86514?usp=email ) Change subject: mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization ...................................................................... mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization The previous approach would increase the delay time by 50 ms. So move WWAN power sequence to GPIO control to reduce boot time caused by WWAN initialization. Additionally, add a 150ms delay to T0_OFF_MS before powering off the WWAN. This ensures that the WWAN Power OFF Sequence operates correctly during a reboot. BUG=b:383212261 BRANCH=firmware-trulo-15217.771.B TEST=Confirm the measured WWAN power sequence Change-Id: Ie01019eca7eaa4bbb34dd80aeb65b9b6b08587fd Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86514 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/uldrenite/gpio.c M src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h M src/mainboard/google/brya/variants/uldrenite/variant.c M src/mainboard/google/brya/wwan_power.asl 4 files changed, 10 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c index 3e11b48..e8355d3 100644 --- a/src/mainboard/google/brya/variants/uldrenite/gpio.c +++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c @@ -232,9 +232,9 @@ /* F11 : NC */ PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : NC ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_F12, 0, DEEP), + PAD_CFG_GPO(GPP_F12, 1, DEEP), /* F13 : NC ==> PLTRST_WWAN# */ - PAD_CFG_GPO(GPP_F13, 0, DEEP), + PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : NC */ PAD_NC(GPP_F14, NONE), /* F15 : NC */ @@ -303,7 +303,7 @@ /* H22 : NC */ PAD_NC(GPP_H22, NONE), /* H23 : LTE_PWR_OFF_EN */ - PAD_CFG_GPO(GPP_H23, 0, DEEP), + PAD_CFG_GPO(GPP_H23, 1, DEEP), /* R0 : HDA_BCLK ==> HDA_BIT_CLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), @@ -435,7 +435,7 @@ /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H23 : LTE_PWR_OFF_EN */ - PAD_CFG_GPO(GPP_H23, 0, DEEP), + PAD_CFG_GPO(GPP_H23, 1, DEEP), }; /* Fill romstage gpio configuration */ @@ -445,6 +445,8 @@ PAD_CFG_GPO(GPP_E17, 1, DEEP), /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* F12 : NC ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h index 612ea2a..e752456 100644 --- a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h @@ -10,5 +10,6 @@ #define WWAN_PERST GPP_F13 #define T1_OFF_MS 20 #define T2_OFF_MS 10 +#define T0_OFF_MS 150 #endif diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index 3620c3a..4217996 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -7,27 +7,11 @@ #include <fw_config.h> #include <sar.h> -#define RW350R_RST_DELAY_MS 20 -#define RW350R_PERST_DELAY_MS 30 - const char *get_wifi_sar_cbfs_filename(void) { return "wifi_sar_0.hex"; } -static const struct pad_config rw350r_en_pad[] = { - /* H23 : LTE_PWR_OFF_EN */ - PAD_CFG_GPO(GPP_H23, 1, DEEP), -}; -static const struct pad_config rw350r_rst_pad[] = { - /* F12 : WWAN_RST_L */ - PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), -}; -static const struct pad_config rw350r_perst_pad[] = { - /* F13 : PLTRST_WWAN# */ - PAD_CFG_GPO(GPP_F13, 1, DEEP), -}; - static const struct pad_config touchscreen_disable_pads[] = { /* A21 : TCHSCR_REPORT_EN */ PAD_NC(GPP_A21, NONE), @@ -68,22 +52,6 @@ } } -void variant_init(void) -{ - if (fw_config_probe(FW_CONFIG(DB_CELLULAR, CELLULAR_ABSENT))) - return; - /* - * RW350R power on seuqence: - * De-assert WWAN_EN -> 20ms -> de-assert WWAN_RST -> 30ms -> - * de-assert WWAN_PERST - */ - gpio_configure_pads(rw350r_en_pad, ARRAY_SIZE(rw350r_en_pad)); - mdelay(RW350R_RST_DELAY_MS); - gpio_configure_pads(rw350r_rst_pad, ARRAY_SIZE(rw350r_rst_pad)); - mdelay(RW350R_PERST_DELAY_MS); - gpio_configure_pads(rw350r_perst_pad, ARRAY_SIZE(rw350r_perst_pad)); -} - void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) { diff --git a/src/mainboard/google/brya/wwan_power.asl b/src/mainboard/google/brya/wwan_power.asl index f19a5ef..4f9b788 100644 --- a/src/mainboard/google/brya/wwan_power.asl +++ b/src/mainboard/google/brya/wwan_power.asl @@ -11,4 +11,7 @@ \_SB.PCI0.CTXS(WWAN_RST); Sleep(T2_OFF_MS) \_SB.PCI0.CTXS(WWAN_FCPO); +#if CONFIG(BOARD_GOOGLE_ULDRENITE) + Sleep(T0_OFF_MS) +#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/86514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie01019eca7eaa4bbb34dd80aeb65b9b6b08587fd Gerrit-Change-Number: 86514 Gerrit-PatchSet: 9 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: device/dram/ddr5: Add 7500 MT/s support
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86543?usp=email ) Change subject: device/dram/ddr5: Add 7500 MT/s support ...................................................................... device/dram/ddr5: Add 7500 MT/s support Before I got the following error: [ERROR] DDR5 speed of 3750 MHz is out of range tested: glinda based mainboard Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86543 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Reviewed-by: Marvin Drees <marvin.drees(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/device/dram/ddr5.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marvin Drees: Looks good to me, but someone else must approve Andy Ebrahiem: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Naresh Solanki: Looks good to me, approved Alicja Michalska: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/device/dram/ddr5.c b/src/device/dram/ddr5.c index b546abf..90b67f8 100644 --- a/src/device/dram/ddr5.c +++ b/src/device/dram/ddr5.c @@ -21,6 +21,7 @@ DDR5_5500, DDR5_6000, DDR5_6400, + DDR5_7500, }; struct ddr5_speed_attr { @@ -108,6 +109,11 @@ .max_clock_mhz = 3200, .reported_mts = 6400 }, + [DDR5_7500] = { + .min_clock_mhz = 3201, + .max_clock_mhz = 3750, + .reported_mts = 7500 + }, }; /** -- To view, visit https://review.coreboot.org/c/coreboot/+/86543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d Gerrit-Change-Number: 86543 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86414?usp=email ) Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode ...................................................................... soc/intel/common/gpio: Add macro for interrupt GPI with driver mode Adds PAD_CFG_GPI_APIC_DRIVER macros to configure interrupt pad with driver mode. This is needed when a PAD is configured as an interrupt such that the corresponding GPI_IS status bit can be updated by the host controller hardware. BUG=none TEST=Check a GPIO pad that is used as interrupt via GpioInt in the ACPI device _CRS method and check the interrupt has been assigned in /proc/interrupts. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86414 Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Kyoung Il Kim: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index f0ff08c..bcf8e73 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -436,6 +436,14 @@ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) +/* General purpose input, routed to APIC, HostOwn */ +#define PAD_CFG_GPI_APIC_DRIVER(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxDRxE) | \ + PAD_CFG_OWN_GPIO(DRIVER)) + /* General purpose input with lock, routed to APIC */ #define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, lock_action) \ _PAD_CFG_STRUCT_LOCK(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/86414?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 Gerrit-Change-Number: 86414 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/amd/glinda/cpu: Update smbios parameters
by Maximilian Brune (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Naresh Solanki. Maximilian Brune has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85637?usp=email ) Change subject: soc/amd/glinda/cpu: Update smbios parameters ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85637/comment/4dc8abaf_b575568b?us… : PS3, Line 9: Update smbios parameters for cache type, operation mode & error : correction type. > could you add the source of your information? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8eaa54c9a0086f4d397a7ddb01009acfd3f1aee Gerrit-Change-Number: 85637 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 18:05:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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coreboot-gerrit February 2025