coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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2886 discussions

[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Don't reconfigure GPIOs in ramstage
by Matt DeVillier (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86650?usp=email ) Change subject: mb/starlabs/starbook/mtl: Don't reconfigure GPIOs in ramstage ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86650/comment/55e7b024_d66b8db4?us… : PS1, Line 9: GPP_H08 and GPP_H09 are configured in the bootblock, so remove the : configuration in ramstage. is there any benefit to not doing so? -- To view, visit https://review.coreboot.org/c/coreboot/+/86650?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b813370cf259fb1ca138dd1922c16f801b40cc4 Gerrit-Change-Number: 86650 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 28 Feb 2025 13:47:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/geralt: Tuning CSOT_PNA957QT1_1 panel VSP/VSN voltage for Ciri
by Yidi Lin (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/86640?usp=email ) Change subject: mb/google/geralt: Tuning CSOT_PNA957QT1_1 panel VSP/VSN voltage for Ciri ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86640/comment/2fa82e45_cc28fd00?us… : PS2, Line 7: Tuning CSOT_PNA957QT1_1 panel VSP/VSN voltage for Ciri Adjust VSP/VSN voltage for CSOT_PNA957QT1_1 panel https://review.coreboot.org/c/coreboot/+/86640/comment/cc1633ed_76309e78?us… : PS2, Line 16: Geralt geralt -- To view, visit https://review.coreboot.org/c/coreboot/+/86640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b69303317f5ef47818f4a6a0c851bf650285e51 Gerrit-Change-Number: 86640 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 13:11:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Adjust thermal trip point parameters
by Yidi Lin (Code Review) 28 Feb '25

28 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86552?usp=email ) Change subject: soc/mediatek/mt8196: Adjust thermal trip point parameters ...................................................................... soc/mediatek/mt8196: Adjust thermal trip point parameters Adjust thermal trip point parameters so the thermal can trigger the interrupt at the expected trip point. BRANCH=rauru BUG=b:389026545 TEST=Boot up and check temperature in coreboot log: [INFO ] [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523) [INFO ] [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715) [INFO ] [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717) [INFO ] [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350) [INFO ] [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593) [INFO ] [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251) Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f Reviewed-on: https://review.coreboot.org/c/coreboot/+/86552 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/include/soc/thermal_internal.h 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h index b584117..55c300d 100644 --- a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h +++ b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h @@ -171,8 +171,8 @@ #define AP_RST_SET (INFRACFG_AO_SEC_BASE + 0xf30) #define AP_RST_CLR (INFRACFG_AO_SEC_BASE + 0xf34) -#define LVTS_COF_T_SLP_GLD 358830 -#define LVTS_COF_COUNT_R_GLD 34389 +#define LVTS_COF_T_SLP_GLD 391460 +#define LVTS_COF_COUNT_R_GLD 34412 #define LVTS_COF_T_CONST_OFS 0 #define DEFAULT_EFUSE_GOLDEN_TEMP 60 -- To view, visit https://review.coreboot.org/c/coreboot/+/86552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f Gerrit-Change-Number: 86552 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Don't reconfigure GPIOs in ramstage
by Sean Rhodes (Code Review) 28 Feb '25

28 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86650?usp=email ) Change subject: mb/starlabs/starbook/mtl: Don't reconfigure GPIOs in ramstage ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86650?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b813370cf259fb1ca138dd1922c16f801b40cc4 Gerrit-Change-Number: 86650 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 28 Feb 2025 12:34:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Bill XIE (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > I implemented the additional logic Nicholas suggested. Let's give it a try. PCIEX1_2 remains not working as before, and system may still fail when starting Linux kernel. The corresponding autoport dump (including cbmem log) is at https://send.aslaets.be/download/402f5bfae3beadc7/#d9DEdMRT8qEnPkaUwXQsoQ , downloadable 10 times in 10 days. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 12:20:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD
by Naresh Solanki (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/86643?usp=email ) Change subject: soc/amd/common/uart: Configure UART PAD ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > the root cause seems to be an fsp bug, so i'd say that that one should be fixed instead Agree. But since we are already initiazing uart in coreboot, thought having the pins configured here should be fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/86643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Gerrit-Change-Number: 86643 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 11:55:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/brya/nova: Enable RTD3 for SSD
by Pranava Y N (Code Review) 28 Feb '25

28 Feb '25

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86649?usp=email ) Change subject: mb/google/brya/nova: Enable RTD3 for SSD ...................................................................... mb/google/brya/nova: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on nova and verify that the device suspends to S0ix. Change-Id: Icb36285d0a12dcb098282b08ef794256af67b019 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/nova/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/86649/1 diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index c8bfc31..a615fdd 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -185,6 +185,13 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref cnvi_wifi on chip drivers/wifi/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/86649?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb36285d0a12dcb098282b08ef794256af67b019 Gerrit-Change-Number: 86649 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya/lisbon: Enable RTD3 for SSD
by Subrata Banik (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N. Subrata Banik has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/86645?usp=email ) Change subject: mb/google/brya/lisbon: Enable RTD3 for SSD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0 Gerrit-Change-Number: 86645 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 11:42:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya/gladios: Enable RTD3 for SSD
by Pranava Y N (Code Review) 28 Feb '25

28 Feb '25

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86648?usp=email ) Change subject: mb/google/brya/gladios: Enable RTD3 for SSD ...................................................................... mb/google/brya/gladios: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on gladios and verify that the device suspends to S0ix. Change-Id: I329e3a99e2e5c7cf4a51d7d8606987f5277d4584 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/gladios/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/86648/1 diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb index 4c3ffff..6c3eaf9 100644 --- a/src/mainboard/google/brya/variants/gladios/overridetree.cb +++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb @@ -149,6 +149,13 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_NVME end #NVMe device ref tbt_pcie_rp0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/86648?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I329e3a99e2e5c7cf4a51d7d8606987f5277d4584 Gerrit-Change-Number: 86648 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya/gaelin: Enable RTD3 for SSD
by Pranava Y N (Code Review) 28 Feb '25

28 Feb '25

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86647?usp=email ) Change subject: mb/google/brya/gaelin: Enable RTD3 for SSD ...................................................................... mb/google/brya/gaelin: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on gaelin and verify that the device suspends to S0ix. Change-Id: I4a3f4fbddae3806f548705e9a492379c0b38a415 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/gaelin/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/86647/1 diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index af4ff61..014be97 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -70,6 +70,13 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tcss_xhci on chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/86647?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a3f4fbddae3806f548705e9a492379c0b38a415 Gerrit-Change-Number: 86647 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

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coreboot-gerrit February 2025