coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD
by Naresh Solanki (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/86643?usp=email ) Change subject: soc/amd/common/uart: Configure UART PAD ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/uart/uart.c: https://review.coreboot.org/c/coreboot/+/86643/comment/62ab4e6a_fe707b74?us… : PS1, Line 83: unsigned int idx; : size_t num_ctrlrs; : const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); > I'd put this in the if-block Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Gerrit-Change-Number: 86643 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 10:23:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD
by Naresh Solanki (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki. Hello Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86643?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons Change subject: soc/amd/common/uart: Configure UART PAD ...................................................................... soc/amd/common/uart: Configure UART PAD On Glinda SoC, UART0 pins like CTS & RTS are also shared with UART1. During FSP Silicon init, UART1 pins gets reconfigured to UART0 CTS & RTS when initializing it. This leads IOMUX configuration mismatch for UART1 leading to UART1 non-functional. To address this, configure UART controller pad when enabling it post silicon init. Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/common/block/uart/uart.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86643/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Gerrit-Change-Number: 86643 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD
by Angel Pons (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/86643?usp=email ) Change subject: soc/amd/common/uart: Configure UART PAD ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Gerrit-Change-Number: 86643 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 10:16:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD
by Angel Pons (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/86643?usp=email ) Change subject: soc/amd/common/uart: Configure UART PAD ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/uart/uart.c: https://review.coreboot.org/c/coreboot/+/86643/comment/603d215a_8832e68b?us… : PS1, Line 83: unsigned int idx; : size_t num_ctrlrs; : const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); I'd put this in the if-block -- To view, visit https://review.coreboot.org/c/coreboot/+/86643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Gerrit-Change-Number: 86643 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 10:16:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD
by Naresh Solanki (Code Review) 28 Feb '25

28 Feb '25

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86643?usp=email ) Change subject: soc/amd/common/uart: Configure UART PAD ...................................................................... soc/amd/common/uart: Configure UART PAD On Glinda SoC, UART0 pins like CTS & RTS are also shared with UART1. During FSP Silicon init, UART1 pins gets reconfigured to UART0 CTS & RTS when initializing it. This leads IOMUX configuration mismatch for UART1 leading to UART1 non-functional. To address this, configure UART controller pad when enabling it post silicon init. Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/common/block/uart/uart.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86643/1 diff --git a/src/soc/amd/common/block/uart/uart.c b/src/soc/amd/common/block/uart/uart.c index ca678fd..4e70b23 100644 --- a/src/soc/amd/common/block/uart/uart.c +++ b/src/soc/amd/common/block/uart/uart.c @@ -80,6 +80,9 @@ static void uart_enable(struct device *dev) { unsigned int dev_id; + unsigned int idx; + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); if (get_uart_aoac_device(dev->path.mmio.addr, &dev_id) == CB_ERR) { printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); @@ -89,6 +92,8 @@ if (dev->enabled) { power_on_aoac_device(dev_id); wait_for_aoac_enabled(dev_id); + if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) + set_uart_config(idx); } else { power_off_aoac_device(dev_id); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Gerrit-Change-Number: 86643 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com>

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Andy Ebrahiem (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Felix Held, Jérémy Compostella, Naresh Solanki. Andy Ebrahiem has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 10:00:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Naresh Solanki (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune, Patrick Rudolph, Paul Menzel. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... Patch Set 5: (3 comments) File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/475f2713_19412fc9?us… : PS5, Line 24: uint32_t leaf = DETERMINISTIC_CACHE_PARAMETERS_CPUID_AMD; : uint8_t level = 3; : : struct cpuid_result cache_info_res = cpuid_ext(leaf, level); : : info->type = CPUID_CACHE_TYPE(cache_info_res); : info->level = CPUID_CACHE_LEVEL(cache_info_res); : info->num_ways = CPUID_CACHE_WAYS_OF_ASSOC(cache_info_res) + 1; : info->num_sets = CPUID_CACHE_NO_OF_SETS(cache_info_res) + 1; : info->line_size = CPUID_CACHE_COHER_LINE(cache_info_res) + 1; : info->physical_partitions = CPUID_CACHE_PHYS_LINE(cache_info_res) + 1; : info->num_cores_shared = CPUID_CACHE_SHARING_CACHE(cache_info_res) + 1; : info->fully_associative = CPUID_CACHE_FULL_ASSOC(cache_info_res); : info->size = get_cache_size(info); > 1. yes its possible to deduplicate it. […] Required duplication is done. https://review.coreboot.org/c/coreboot/+/85640/comment/cbd99178_9cc9aaa7?us… : PS5, Line 52: if (!info) : return false; > Acknowledged Acknowledged https://review.coreboot.org/c/coreboot/+/85640/comment/8d7478ce_121a26aa?us… : PS5, Line 70: :: > Acknowledged Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 09:53:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Naresh Solanki (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune, Naresh Solanki. Hello Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85638?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... arch/x86/cpu: Add helper function to compute cache Consider special requirements for computing cache size in certain SoCs, such as `soc/amd/glinda`. Use the helper function to implement SoC-specific logic for computing cache size. Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 2 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85638/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Naresh Solanki (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune, Patrick Rudolph, Paul Menzel. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85640?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper Glinda SoC has separate caches for Classic and Dense cores, uniquely identified using a cache ID computed from the core index. Ensure `soc_fill_cpu_cache_info` computes the L3 cache size while considering the cache ID, enabling accurate cache size calculation. Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/glinda/cpu.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85640/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 6 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: vc/intel/fsp/ptl: Update header files from 3015_00 to 3071_00
by Name of user not set (Code Review) 28 Feb '25

28 Feb '25

srinivas.kulkarni(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86642?usp=email ) Change subject: vc/intel/fsp/ptl: Update header files from 3015_00 to 3071_00 ...................................................................... vc/intel/fsp/ptl: Update header files from 3015_00 to 3071_00 Update header files for FSP for Panther Lake platform to version 3071_00, with the previous version being 3015_00. Changes includes: FSPM: - Offset changes - Added UPD's - TXDQSDCC, WeaklockEn, RxDqsDelayCompEn FSPS: - Reserved bit changes BUG=b:396535191 TEST=Able to build Google/fatcat. Change-Id: I9657eb2b6db1b05adc721b3ef2cf8661642d91e8 Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h 2 files changed, 911 insertions(+), 873 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/86642/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h index 82a790e..55dc43c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h @@ -662,703 +662,715 @@ **/ UINT8 SpdProfileSelected; -/** Offset 0x0211 +/** Offset 0x0211 - RxVref Per-Bit Training + Enable/Disable RxVref Per-Bit Training + $EN_DIS **/ UINT8 RXVREFPERBIT; -/** Offset 0x0212 - Reserved +/** Offset 0x0212 - TXDQS DCC Training + Enables/Disable TXDQS DCC Training + $EN_DIS +**/ + UINT8 TXDQSDCC; + +/** Offset 0x0213 - Reserved **/ UINT8 Reserved12; -/** Offset 0x0213 - Ch Hash Override +/** Offset 0x0214 - Ch Hash Override Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode $EN_DIS **/ UINT8 ChHashOverride; -/** Offset 0x0214 - Reserved +/** Offset 0x0215 - Reserved **/ UINT8 Reserved13[2]; -/** Offset 0x0216 - DQS Rise/Fall +/** Offset 0x0217 - DQS Rise/Fall Enables/Disable DQS Rise/Fall $EN_DIS **/ UINT8 RDDQSODTT; -/** Offset 0x0217 - Reserved +/** Offset 0x0218 - Reserved **/ UINT8 Reserved14[2]; -/** Offset 0x0219 - Functional Duty Cycle Correction for DDR5 CLK +/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 CLK Enable/Disable Functional Duty Cycle Correction for DDR5 CLK 0:Disable, 1:Enable **/ UINT8 FUNCDCCCLK; -/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 DQS +/** Offset 0x021B - Functional Duty Cycle Correction for DDR5 DQS Enable/Disable Functional Duty Cycle Correction for DDR5 DQS 0:Disable, 1:Enable **/ UINT8 FUNCDCCDQS; -/** Offset 0x021B +/** Offset 0x021C **/ UINT8 FUNCDCCWCK; -/** Offset 0x021C - Duty Cycle Correction for LP5 DCA +/** Offset 0x021D - Duty Cycle Correction for LP5 DCA Enable/Disable Duty Cycle Correction for LP5 DCA $EN_DIS **/ UINT8 DCCLP5WCKDCA; -/** Offset 0x021D - DQ/DQS Swizzle Training +/** Offset 0x021E - DQ/DQS Swizzle Training Enable/Disable DQ/DQS Swizzle Training $EN_DIS **/ UINT8 DQDQSSWZ; -/** Offset 0x021E - Reserved +/** Offset 0x021F - Reserved **/ UINT8 Reserved15; -/** Offset 0x021F - Functional Duty Cycle Correction for Data DQ +/** Offset 0x0220 - Functional Duty Cycle Correction for Data DQ Enable/Disable Functional Duty Cycle Correction for Data DQ 0:Disable, 1:Enable **/ UINT8 FUNCDCCDQ; -/** Offset 0x0220 - Reserved +/** Offset 0x0221 - Reserved **/ UINT8 Reserved16[5]; -/** Offset 0x0225 - Unmatched Rx Calibration +/** Offset 0x0226 - Unmatched Rx Calibration Enable/Disable Rx Unmatched Calibration $EN_DIS **/ UINT8 RXUNMATCHEDCAL; -/** Offset 0x0226 - Hard Post Package Repair +/** Offset 0x0227 - Hard Post Package Repair Enables/Disable Hard Post Package Repair $EN_DIS **/ UINT8 PPR; -/** Offset 0x0227 - Reserved +/** Offset 0x0228 - Reserved **/ UINT8 Reserved17; -/** Offset 0x0228 - PPR Run Once +/** Offset 0x0229 - PPR Run Once When Eanble, PPR will run only once and then is disabled at next training cycle $EN_DIS **/ UINT8 PprRunOnce; -/** Offset 0x0229 - PPR Run During Fastboot +/** Offset 0x022A - PPR Run During Fastboot When Eanble, PPR will run during fastboot $EN_DIS **/ UINT8 PprRunAtFastboot; -/** Offset 0x022A - PPR Repair Type +/** Offset 0x022B - PPR Repair Type PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair **/ UINT8 PprRepairType; -/** Offset 0x022B - PPR Error Injection +/** Offset 0x022C - PPR Error Injection When Eanble, PPR will inject bad rows during testing $EN_DIS **/ UINT8 PprErrorInjection; -/** Offset 0x022C - PPR Repair Controller +/** Offset 0x022D - PPR Repair Controller PPR repair controller: User chooses to force repair specifc address **/ UINT8 PprRepairController; -/** Offset 0x022D - PPR Repair Channel +/** Offset 0x022E - PPR Repair Channel PPR repair Channel: User chooses to force repair specifc address **/ UINT8 PprRepairChannel; -/** Offset 0x022E - PPR Repair Dimm +/** Offset 0x022F - PPR Repair Dimm PPR repair Dimm: User chooses to force repair specifc address **/ UINT8 PprRepairDimm; -/** Offset 0x022F - PPR Repair Rank +/** Offset 0x0230 - PPR Repair Rank PPR repair Rank: User chooses to force repair specifc address **/ UINT8 PprRepairRank; -/** Offset 0x0230 - PPR Repair Row +/** Offset 0x0231 - Reserved +**/ + UINT8 Reserved18[3]; + +/** Offset 0x0234 - PPR Repair Row PPR repair Row: User chooses to force repair specifc address **/ UINT32 PprRepairRow; -/** Offset 0x0234 - Reserved +/** Offset 0x0238 - Reserved **/ - UINT8 Reserved18[8]; + UINT8 Reserved19[8]; -/** Offset 0x023C - PPR Repair BankGroup +/** Offset 0x0240 - PPR Repair BankGroup PPR repair BankGroup: User chooses to force repair specifc address **/ UINT8 PprRepairBankGroup; -/** Offset 0x023D - LVR Auto Trim +/** Offset 0x0241 - LVR Auto Trim Enable/disable LVR Auto Trim $EN_DIS **/ UINT8 LVRAUTOTRIM; -/** Offset 0x023E - Compensation Optimization +/** Offset 0x0242 - Compensation Optimization Enable/Disable Compensation Optimization $EN_DIS **/ UINT8 OPTIMIZECOMP; -/** Offset 0x023F - Write DQ/DQS Retraining +/** Offset 0x0243 - Write DQ/DQS Retraining Enable/Disable Write DQ/DQS Retraining $EN_DIS **/ UINT8 WRTRETRAIN; -/** Offset 0x0240 - Reserved +/** Offset 0x0244 - Reserved **/ - UINT8 Reserved19[3]; + UINT8 Reserved20[3]; -/** Offset 0x0243 - RDDQODTT +/** Offset 0x0247 - RDDQODTT Enable/disable Read DQ ODT Training $EN_DIS **/ UINT8 RDDQODTT; -/** Offset 0x0244 - RDCTLET +/** Offset 0x0248 - RDCTLET Enable/disable Read CTLE Training $EN_DIS **/ UINT8 RDCTLET; -/** Offset 0x0245 - RxVref Pre EMPHASIS Training +/** Offset 0x0249 - RxVref Pre EMPHASIS Training Enable/Disable Pre EMPHASIS Training $EN_DIS **/ UINT8 EMPHASIS; -/** Offset 0x0246 - RX DQS VOC Centring Training +/** Offset 0x024A - RX DQS VOC Centring Training Enable/Disable RX DQS VOC Centring Training $EN_DIS **/ UINT8 RXDQSVOCC; -/** Offset 0x0247 - NMode +/** Offset 0x024B - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N **/ UINT8 NModeSupport; -/** Offset 0x0248 - LPDDR ODT RttWr +/** Offset 0x024C - LPDDR ODT RttWr Initial RttWr for LP4/5 in Ohms. 0x0 - Auto **/ UINT8 LpddrRttWr; -/** Offset 0x0249 - Retrain on Fast flow Failure +/** Offset 0x024D - Retrain on Fast flow Failure Restart MRC in Cold mode if SW MemTest fails during Fast flow. $EN_DIS **/ UINT8 RetrainOnFastFail; -/** Offset 0x024A - LPDDR ODT RttCa +/** Offset 0x024E - LPDDR ODT RttCa Initial RttCa for LP4/5 in Ohms. 0x0 - Auto **/ UINT8 LpddrRttCa; -/** Offset 0x024B - DIMM DFE Training +/** Offset 0x024F - DIMM DFE Training Enable/Disable DIMM DFE Training $EN_DIS **/ UINT8 WRTDIMMDFE; -/** Offset 0x024C - DDR5 ODT Timing Config +/** Offset 0x0250 - DDR5 ODT Timing Config Enable/Disable DDR5 ODT TIMING CONFIG $EN_DIS **/ UINT8 DDR5ODTTIMING; -/** Offset 0x024D - HobBufferSize +/** Offset 0x0251 - HobBufferSize Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size). 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value **/ UINT8 HobBufferSize; -/** Offset 0x024E - Early Command Training +/** Offset 0x0252 - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x024F - SenseAmp Offset Training +/** Offset 0x0253 - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS **/ UINT8 SOT; -/** Offset 0x0250 - Early ReadMPR Timing Centering 2D +/** Offset 0x0254 - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $EN_DIS **/ UINT8 ERDMPRTC2D; -/** Offset 0x0251 - Read MPR Training +/** Offset 0x0255 - Read MPR Training Enables/Disable Read MPR Training $EN_DIS **/ UINT8 RDMPRT; -/** Offset 0x0252 - Receive Enable Training +/** Offset 0x0256 - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS **/ UINT8 RCVET; -/** Offset 0x0253 - Jedec Write Leveling +/** Offset 0x0257 - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS **/ UINT8 JWRL; -/** Offset 0x0254 - Early Write Time Centering 2D +/** Offset 0x0258 - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS **/ UINT8 EWRTC2D; -/** Offset 0x0255 - Early Read Time Centering 2D +/** Offset 0x0259 - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS **/ UINT8 ERDTC2D; -/** Offset 0x0256 - Unmatched Write Time Centering 1D +/** Offset 0x025A - Unmatched Write Time Centering 1D Enable/Disable Unmatched Write Time Centering 1D $EN_DIS **/ UINT8 UNMATCHEDWRTC1D; -/** Offset 0x0257 - Write Timing Centering 1D +/** Offset 0x025B - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS **/ UINT8 WRTC1D; -/** Offset 0x0258 - Write Voltage Centering 1D +/** Offset 0x025C - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS **/ UINT8 WRVC1D; -/** Offset 0x0259 - Read Timing Centering 1D +/** Offset 0x025D - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS **/ UINT8 RDTC1D; -/** Offset 0x025A - Dimm ODT Training +/** Offset 0x025E - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS **/ UINT8 DIMMODTT; -/** Offset 0x025B - DIMM RON Training +/** Offset 0x025F - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS **/ UINT8 DIMMRONT; -/** Offset 0x025C - Write Drive Strength/Equalization 2D +/** Offset 0x0260 - Write Drive Strength/Equalization 2D Enables/Disable Write Drive Strength/Equalization 2D $EN_DIS **/ UINT8 WRDSEQT; -/** Offset 0x025D - Read Equalization Training +/** Offset 0x0261 - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS **/ UINT8 RDEQT; -/** Offset 0x025E - Write Timing Centering 2D +/** Offset 0x0262 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS **/ UINT8 WRTC2D; -/** Offset 0x025F - Read Timing Centering 2D +/** Offset 0x0263 - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS **/ UINT8 RDTC2D; -/** Offset 0x0260 - Write Voltage Centering 2D +/** Offset 0x0264 - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS **/ UINT8 WRVC2D; -/** Offset 0x0261 - Read Voltage Centering 2D +/** Offset 0x0265 - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS **/ UINT8 RDVC2D; -/** Offset 0x0262 - Command Voltage Centering +/** Offset 0x0266 - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS **/ UINT8 CMDVC; -/** Offset 0x0263 - Late Command Training +/** Offset 0x0267 - Late Command Training Enables/Disable Late Command Training $EN_DIS **/ UINT8 LCT; -/** Offset 0x0264 - Round Trip Latency Training +/** Offset 0x0268 - Round Trip Latency Training Enables/Disable Round Trip Latency Training $EN_DIS **/ UINT8 RTL; -/** Offset 0x0265 - Turn Around Timing Training +/** Offset 0x0269 - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS **/ UINT8 TAT; -/** Offset 0x0266 - Reserved +/** Offset 0x026A - Reserved **/ - UINT8 Reserved20; + UINT8 Reserved21; -/** Offset 0x0267 - DIMM SPD Alias Test +/** Offset 0x026B - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS **/ UINT8 ALIASCHK; -/** Offset 0x0268 - Receive Enable Centering 1D +/** Offset 0x026C - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D $EN_DIS **/ UINT8 RCVENC1D; -/** Offset 0x0269 - Retrain Margin Check +/** Offset 0x026D - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS **/ UINT8 RMC; -/** Offset 0x026A - ECC Support +/** Offset 0x026E - ECC Support Enables/Disable ECC Support $EN_DIS **/ UINT8 EccSupport; -/** Offset 0x026B - Reserved +/** Offset 0x026F - Reserved **/ - UINT8 Reserved21[2]; + UINT8 Reserved22[2]; -/** Offset 0x026D - Ibecc +/** Offset 0x0271 - Ibecc In-Band ECC Support $EN_DIS **/ UINT8 Ibecc; -/** Offset 0x026E - IbeccParity +/** Offset 0x0272 - IbeccParity In-Band ECC Parity Control $EN_DIS **/ UINT8 IbeccParity; -/** Offset 0x026F - Reserved +/** Offset 0x0273 - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved23; -/** Offset 0x0270 - IbeccOperationMode +/** Offset 0x0274 - IbeccOperationMode In-Band ECC Operation Mode 0:Protect base on address range, 1: Non-protected, 2: All protected **/ UINT8 IbeccOperationMode; -/** Offset 0x0271 - IbeccProtectedRegionEnable +/** Offset 0x0275 - IbeccProtectedRegionEnable In-Band ECC Protected Region Enable $EN_DIS **/ UINT8 IbeccProtectedRegionEnable[8]; -/** Offset 0x0279 - Reserved +/** Offset 0x027D - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved24; -/** Offset 0x027A - IbeccProtectedRegionBases +/** Offset 0x027E - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance **/ UINT16 IbeccProtectedRegionBase[8]; -/** Offset 0x028A - IbeccProtectedRegionMasks +/** Offset 0x028E - IbeccProtectedRegionMasks IBECC Protected Region Masks **/ UINT16 IbeccProtectedRegionMask[8]; -/** Offset 0x029A - Memory Remap +/** Offset 0x029E - Memory Remap Enables/Disable Memory Remap $EN_DIS **/ UINT8 RemapEnable; -/** Offset 0x029B - Rank Interleave support +/** Offset 0x029F - Rank Interleave support Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time. $EN_DIS **/ UINT8 RankInterleave; -/** Offset 0x029C - Enhanced Interleave support +/** Offset 0x02A0 - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS **/ UINT8 EnhancedInterleave; -/** Offset 0x029D - Ch Hash Support +/** Offset 0x02A1 - Ch Hash Support Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode $EN_DIS **/ UINT8 ChHashEnable; -/** Offset 0x029E - DDR PowerDown and idle counter +/** Offset 0x02A2 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ UINT8 EnablePwrDn; -/** Offset 0x029F - DDR PowerDown and idle counter +/** Offset 0x02A3 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ UINT8 EnablePwrDnLpddr; -/** Offset 0x02A0 - SelfRefresh Enable +/** Offset 0x02A4 - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS **/ UINT8 SrefCfgEna; -/** Offset 0x02A1 - Throttler CKEMin Defeature +/** Offset 0x02A5 - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) $EN_DIS **/ UINT8 ThrtCkeMinDefeatLpddr; -/** Offset 0x02A2 - Throttler CKEMin Defeature +/** Offset 0x02A6 - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS **/ UINT8 ThrtCkeMinDefeat; -/** Offset 0x02A3 - Exit On Failure (MRC) +/** Offset 0x02A7 - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS **/ UINT8 ExitOnFailure; -/** Offset 0x02A4 - Reserved +/** Offset 0x02A8 - Reserved **/ - UINT8 Reserved24[2]; + UINT8 Reserved25[2]; -/** Offset 0x02A6 - Read Voltage Centering 1D +/** Offset 0x02AA - Read Voltage Centering 1D Enable/Disable Read Voltage Centering 1D $EN_DIS **/ UINT8 RDVC1D; -/** Offset 0x02A7 - TxDqTCO Comp Training +/** Offset 0x02AB - TxDqTCO Comp Training Enable/Disable TxDqTCO Comp Training $EN_DIS **/ UINT8 TXTCO; -/** Offset 0x02A8 - ClkTCO Comp Training +/** Offset 0x02AC - ClkTCO Comp Training Enable/Disable ClkTCO Comp Training $EN_DIS **/ UINT8 CLKTCO; -/** Offset 0x02A9 - CMD Slew Rate Training +/** Offset 0x02AD - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS **/ UINT8 CMDSR; -/** Offset 0x02AA - CMD Drive Strength and Tx Equalization +/** Offset 0x02AE - CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equalization $EN_DIS **/ UINT8 CMDDSEQ; -/** Offset 0x02AB - DIMM CA ODT Training +/** Offset 0x02AF - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training $EN_DIS **/ UINT8 DIMMODTCA; -/** Offset 0x02AC - Read Vref Decap Training* +/** Offset 0x02B0 - Read Vref Decap Training* Enable/Disable Read Vref Decap Training* $EN_DIS **/ UINT8 RDVREFDC; -/** Offset 0x02AD - Rank Margin Tool Per Bit +/** Offset 0x02B1 - Rank Margin Tool Per Bit Enable/Disable Rank Margin Tool Per Bit $EN_DIS **/ UINT8 RMTBIT; -/** Offset 0x02AE - Ref PI Calibration +/** Offset 0x02B2 - Ref PI Calibration Enable/Disable Ref PI Calibration $EN_DIS **/ UINT8 REFPI; -/** Offset 0x02AF - VccClk FF Offset Correction +/** Offset 0x02B3 - VccClk FF Offset Correction Enable/Disable VccClk FF Offset Correction 0:Disable, 1:Enable **/ UINT8 VCCCLKFF; -/** Offset 0x02B0 - Data PI Linearity Calibration +/** Offset 0x02B4 - Data PI Linearity Calibration Enable/Disable {Data PI Linearity Calibration $EN_DIS **/ UINT8 DATAPILIN; -/** Offset 0x02B1 - Ddr5 Rx Cross-Talk Cancellation +/** Offset 0x02B5 - Ddr5 Rx Cross-Talk Cancellation Enable/Disable {Ddr5 Rx Cross-Talk Cancellation $EN_DIS **/ UINT8 DDR5XTALK; -/** Offset 0x02B2 - Retrain On Working Channel +/** Offset 0x02B6 - Retrain On Working Channel Enables/Disable Retrain On Working Channel feature $EN_DIS **/ UINT8 RetrainToWorkingChannel; -/** Offset 0x02B3 - Row Press +/** Offset 0x02B7 - Row Press Enables/Disable Row Press feature $EN_DIS **/ UINT8 RowPressEn; -/** Offset 0x02B4 - Reserved +/** Offset 0x02B8 - Reserved **/ - UINT8 Reserved25; + UINT8 Reserved26; -/** Offset 0x02B5 - DDR5 MR7 WICA support +/** Offset 0x02B9 - DDR5 MR7 WICA support Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment $EN_DIS **/ UINT8 IsDdr5MR7WicaSupported; -/** Offset 0x02B6 - Ch Hash Interleaved Bit +/** Offset 0x02BA - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 **/ UINT8 ChHashInterleaveBit; -/** Offset 0x02B7 - Reserved +/** Offset 0x02BB - Reserved **/ - UINT8 Reserved26; + UINT8 Reserved27; -/** Offset 0x02B8 - Ch Hash Mask +/** Offset 0x02BC - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC **/ UINT16 ChHashMask; -/** Offset 0x02BA - Reserved +/** Offset 0x02BE - Reserved **/ - UINT8 Reserved27; + UINT8 Reserved28; -/** Offset 0x02BB - Throttler CKEMin Timer +/** Offset 0x02BF - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Dfault is 0x00 **/ UINT8 ThrtCkeMinTmr; -/** Offset 0x02BC - Allow Opp Ref Below Write Threhold +/** Offset 0x02C0 - Allow Opp Ref Below Write Threhold Allow opportunistic refreshes while we don't exit power down. $EN_DIS **/ UINT8 AllowOppRefBelowWriteThrehold; -/** Offset 0x02BD - Write Threshold +/** Offset 0x02C1 - Write Threshold Number of writes that can be accumulated while CKE is low before CKE is asserted. **/ UINT8 WriteThreshold; -/** Offset 0x02BE - MC_REFRESH_RATE +/** Offset 0x02C2 - MC_REFRESH_RATE Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh **/ UINT8 McRefreshRate; -/** Offset 0x02BF - Refresh Watermarks +/** Offset 0x02C3 - Refresh Watermarks Refresh Watermarks: 0-Low, 1-High (default) 0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default) **/ UINT8 RefreshWm; -/** Offset 0x02C0 - User Manual Threshold +/** Offset 0x02C4 - User Manual Threshold Disabled: Predefined threshold will be used.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserThresholdEnable; -/** Offset 0x02C1 - User Manual Budget +/** Offset 0x02C5 - User Manual Budget Disabled: Configuration of memories will defined the Budget value.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserBudgetEnable; -/** Offset 0x02C2 - Power Down Mode +/** Offset 0x02C6 - Power Down Mode This option controls command bus tristating during idle periods 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto **/ UINT8 PowerDownMode; -/** Offset 0x02C3 - Pwr Down Idle Timer +/** Offset 0x02C7 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo **/ UINT8 PwdwnIdleCounter; -/** Offset 0x02C4 - Page Close Idle Timeout +/** Offset 0x02C8 - Page Close Idle Timeout This option controls Page Close Idle Timeout 0:Enabled, 1:Disabled **/ UINT8 DisPgCloseIdleTimeout; -/** Offset 0x02C5 - Bitmask of ranks that have CA bus terminated +/** Offset 0x02C9 - Bitmask of ranks that have CA bus terminated LPDDR5: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating **/ UINT8 CmdRanksTerminated; -/** Offset 0x02C6 - MRC Safe Mode Override +/** Offset 0x02CA - MRC Safe Mode Override SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3] Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4] @@ -1366,380 +1378,380 @@ **/ UINT8 SafeModeOverride; -/** Offset 0x02C7 - Reserved +/** Offset 0x02CB - Reserved **/ - UINT8 Reserved28[5]; + UINT8 Reserved29[5]; -/** Offset 0x02CC - DDR Phy Safe Mode Support +/** Offset 0x02D0 - DDR Phy Safe Mode Support DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]: Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]: PLL Operation, DdrSafeMode[6]: Safe ODT **/ UINT32 DdrSafeMode; -/** Offset 0x02D0 - Mc Safe Mode Support - McSafeMode[0]: Clk Gate / BGF, McSafeMode[1]: CKE Pdwn, McSafeMode[2]: Tristate, - McSafeMode[3]: PHY Power States / Clock Spine, McSafeMode[4]: Same Rank TA, McSafeMode[5]: - Different Rank TA, McSafeMode[6]: MR4_Period / ZQCAL_Period McSafeMode[7]: LP5 - Wck Mode, SafeMode[8]: Self Refresh, McSafeMode[9]: WR/RD Retraining, McSafeMode[10]: - Power Saving +/** Offset 0x02D4 - Mc Safe Mode Support + McSafeMode[0]: Reserved, McSafeMode[1]: OppSR **/ UINT8 McSafeMode; -/** Offset 0x02D1 - Ask MRC to clear memory content +/** Offset 0x02D5 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. $EN_DIS **/ UINT8 CleanMemory; -/** Offset 0x02D2 - Reserved +/** Offset 0x02D6 - Reserved **/ - UINT8 Reserved29[8]; + UINT8 Reserved30[8]; -/** Offset 0x02DA - RMTLoopCount +/** Offset 0x02DE - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO **/ UINT8 RMTLoopCount; -/** Offset 0x02DB - DdrOneDpc +/** Offset 0x02DF - DdrOneDpc DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, or on both (default) 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled **/ UINT8 DdrOneDpc; -/** Offset 0x02DC - Vddq Voltage Override +/** Offset 0x02E0 - Vddq Voltage Override # is multiple of 1mV where 0 means Auto. **/ UINT16 VddqVoltageOverride; -/** Offset 0x02DE - VccIog Voltage Override +/** Offset 0x02E2 - VccIog Voltage Override # is multiple of 1mV where 0 means Auto. **/ UINT16 VccIogVoltageOverride; -/** Offset 0x02E0 - VccClk Voltage Override +/** Offset 0x02E4 - VccClk Voltage Override # is multiple of 1mV where 0 means Auto. **/ UINT16 VccClkVoltageOverride; -/** Offset 0x02E2 - ThrtCkeMinTmrLpddr +/** Offset 0x02E6 - ThrtCkeMinTmrLpddr Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default **/ UINT8 ThrtCkeMinTmrLpddr; -/** Offset 0x02E3 - Reserved -**/ - UINT8 Reserved30; - -/** Offset 0x02E4 - Margin limit check L2 - Margin limit check L2 threshold: 100=Default -**/ - UINT16 MarginLimitL2; - -/** Offset 0x02E6 - Extended Bank Hashing - Eanble/Disable ExtendedBankHashing - $EN_DIS -**/ - UINT8 ExtendedBankHashing; - /** Offset 0x02E7 - Reserved **/ UINT8 Reserved31; -/** Offset 0x02E8 - LP5 Command Pins Mapping +/** Offset 0x02E8 - Margin limit check L2 + Margin limit check L2 threshold: 100=Default +**/ + UINT16 MarginLimitL2; + +/** Offset 0x02EA - Extended Bank Hashing + Eanble/Disable ExtendedBankHashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; + +/** Offset 0x02EB - Reserved +**/ + UINT8 Reserved32; + +/** Offset 0x02EC - LP5 Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. **/ UINT8 Lp5CccConfig; -/** Offset 0x02E9 - Command Pins Mirrored +/** Offset 0x02ED - Command Pins Mirrored BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. **/ UINT8 CmdMirror; -/** Offset 0x02EA - Time Measure +/** Offset 0x02EE - Time Measure Time Measure: 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 MrcTimeMeasure; -/** Offset 0x02EB - Reserved +/** Offset 0x02EF - Reserved **/ - UINT8 Reserved32[66]; + UINT8 Reserved33[64]; -/** Offset 0x032D - Board Type +/** Offset 0x032F - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server **/ UINT8 UserBd; -/** Offset 0x032E - Spd Address Table +/** Offset 0x0330 - Spd Address Table Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00 **/ UINT8 SpdAddressTable[16]; -/** Offset 0x033E - Enable/Disable MRC TXT dependency +/** Offset 0x0340 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization $EN_DIS **/ UINT8 TxtImplemented; -/** Offset 0x033F - Reserved +/** Offset 0x0341 - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved34; -/** Offset 0x0340 - Skip external display device scanning +/** Offset 0x0342 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x0341 - Generate BIOS Data ACPI Table +/** Offset 0x0343 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it $EN_DIS **/ UINT8 BdatEnable; -/** Offset 0x0342 - BdatTestType +/** Offset 0x0344 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D **/ UINT8 BdatTestType; -/** Offset 0x0343 - Enable PCH HSIO PCIE Rx Set Ctle +/** Offset 0x0345 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. **/ UINT8 PchPcieHsioRxSetCtleEnable[28]; -/** Offset 0x035F - PCH HSIO PCIE Rx Set Ctle Value +/** Offset 0x0361 - PCH HSIO PCIE Rx Set Ctle Value PCH PCIe Gen 3 Set CTLE Value. **/ UINT8 PchPcieHsioRxSetCtle[28]; -/** Offset 0x037B - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override +/** Offset 0x037D - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; -/** Offset 0x0397 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value +/** Offset 0x0399 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; -/** Offset 0x03B3 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override +/** Offset 0x03B5 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; -/** Offset 0x03CF - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value +/** Offset 0x03D1 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; -/** Offset 0x03EB - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override +/** Offset 0x03ED - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; -/** Offset 0x0407 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value +/** Offset 0x0409 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; -/** Offset 0x0423 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x0425 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; -/** Offset 0x043F - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value +/** Offset 0x0441 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen1DeEmph[28]; -/** Offset 0x045B - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override +/** Offset 0x045D - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; -/** Offset 0x0477 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value +/** Offset 0x0479 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; -/** Offset 0x0493 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override +/** Offset 0x0495 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; -/** Offset 0x04AF - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value +/** Offset 0x04B1 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; -/** Offset 0x04CB - HD Audio DMIC Link Clock Select +/** Offset 0x04CD - HD Audio DMIC Link Clock Select Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB 0: Both, 1: ClkA, 2: ClkB **/ UINT8 PchHdaAudioLinkDmicClockSelect[2]; -/** Offset 0x04CD - Enable Intel HD Audio (Azalia) +/** Offset 0x04CF - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller $EN_DIS **/ UINT8 PchHdaEnable; -/** Offset 0x04CE - Universal Audio Architecture compliance for DSP enabled system +/** Offset 0x04D0 - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). $EN_DIS **/ UINT8 PchHdaDspUaaCompliance; -/** Offset 0x04CF - Enable HD Audio Link +/** Offset 0x04D1 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x04D0 - Enable HDA SDI lanes +/** Offset 0x04D2 - Enable HDA SDI lanes Enable/disable HDA SDI lanes. **/ UINT8 PchHdaSdiEnable[2]; -/** Offset 0x04D2 - Enable HD Audio DMIC_N Link +/** Offset 0x04D4 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x04D4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) +/** Offset 0x04D6 - Reserved +**/ + UINT8 Reserved35[2]; + +/** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* **/ UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; -/** Offset 0x04DC - Enable HD Audio DSP +/** Offset 0x04E0 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x04DD - Reserved +/** Offset 0x04E1 - Reserved **/ - UINT8 Reserved34[3]; + UINT8 Reserved36[3]; -/** Offset 0x04E0 - DMIC<N> Data Pin Muxing +/** Offset 0x04E4 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* **/ UINT32 PchHdaAudioLinkDmicDataPinMux[2]; -/** Offset 0x04E8 - Enable HD Audio SSP0 Link +/** Offset 0x04EC - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[7]; -/** Offset 0x04EF - Reserved +/** Offset 0x04F3 - Reserved **/ - UINT8 Reserved35[117]; + UINT8 Reserved37[117]; -/** Offset 0x0564 - Enable HD Audio SoundWire#N Link +/** Offset 0x0568 - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[5]; -/** Offset 0x0569 - iDisp-Link Frequency +/** Offset 0x056D - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x056A - iDisp-Link T-mode +/** Offset 0x056E - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x056B - Reserved +/** Offset 0x056F - Reserved **/ - UINT8 Reserved36[45]; + UINT8 Reserved38[45]; -/** Offset 0x0598 - iDisplay Audio Codec disconnection +/** Offset 0x059C - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x0599 - Reserved +/** Offset 0x059D - Reserved **/ - UINT8 Reserved37[5]; + UINT8 Reserved39[5]; -/** Offset 0x059E - HDA Power/Clock Gating (PGD/CGD) +/** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD) Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE. 0: POR, 1: Force Enable, 2: Force Disable **/ UINT8 PchHdaTestPowerClockGating; -/** Offset 0x059F - Reserved +/** Offset 0x05A3 - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved40; -/** Offset 0x05A0 - Audio Sub System IDs +/** Offset 0x05A4 - Audio Sub System IDs Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. **/ UINT32 PchHdaSubSystemIds; -/** Offset 0x05A4 - Reserved +/** Offset 0x05A8 - Reserved **/ - UINT8 Reserved39; + UINT8 Reserved41; -/** Offset 0x05A5 - PCH LPC Enhance the port 8xh decoding +/** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h. $EN_DIS **/ UINT8 PchLpcEnhancePort8xhDecoding; -/** Offset 0x05A6 - Usage type for ClkSrc +/** Offset 0x05AA - Usage type for ClkSrc 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ UINT8 PcieClkSrcUsage[18]; -/** Offset 0x05B8 - ClkReq-to-ClkSrc mapping +/** Offset 0x05BC - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[18]; -/** Offset 0x05CA - Reserved +/** Offset 0x05CE - Reserved **/ - UINT8 Reserved40[46]; + UINT8 Reserved42[46]; -/** Offset 0x05F8 - Enable PCIE RP Mask +/** Offset 0x05FC - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpEnableMask; -/** Offset 0x05FC - Debug Interfaces +/** Offset 0x0600 - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x05FD - Reserved +/** Offset 0x0601 - Reserved **/ - UINT8 Reserved41[3]; + UINT8 Reserved43[3]; -/** Offset 0x0600 - Serial Io Uart Debug Mmio Base +/** Offset 0x0604 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode = SerialIoUartPci. **/ UINT32 SerialIoUartDebugMmioBase; -/** Offset 0x0604 - PcdSerialDebugLevel +/** Offset 0x0608 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -1748,7 +1760,7 @@ **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0605 - SerialDebugMrcLevel +/** Offset 0x0609 - SerialDebugMrcLevel MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -1757,318 +1769,318 @@ **/ UINT8 SerialDebugMrcLevel; -/** Offset 0x0606 - Serial Io Uart Debug Controller Number +/** Offset 0x060A - Serial Io Uart Debug Controller Number Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x0607 - Serial Io Uart Debug Parity +/** Offset 0x060B - Serial Io Uart Debug Parity Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartDebugParity; -/** Offset 0x0608 - Serial Io Uart Debug BaudRate +/** Offset 0x060C - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 **/ UINT32 SerialIoUartDebugBaudRate; -/** Offset 0x060C - Serial Io Uart Debug Stop Bits +/** Offset 0x0610 - Serial Io Uart Debug Stop Bits Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartDebugStopBits; -/** Offset 0x060D - Serial Io Uart Debug Data Bits +/** Offset 0x0611 - Serial Io Uart Debug Data Bits Set default word length. 0: Default, 5,6,7,8 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS **/ UINT8 SerialIoUartDebugDataBits; -/** Offset 0x060E - IMGU CLKOUT Configuration +/** Offset 0x0612 - IMGU CLKOUT Configuration The configuration of IMGU CLKOUT, 0: Disable;1: Enable. $EN_DIS **/ UINT8 ImguClkOutEn[6]; -/** Offset 0x0614 - Enable/Disable SA IPU +/** Offset 0x0618 - Enable/Disable SA IPU Enable(Default): Enable SA IPU, Disable: Disable SA IPU $EN_DIS **/ UINT8 SaIpuEnable; -/** Offset 0x0615 - Disable and Lock Watch Dog Register +/** Offset 0x0619 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. $EN_DIS **/ UINT8 WdtDisableAndLock; -/** Offset 0x0616 - Reserved +/** Offset 0x061A - Reserved **/ - UINT8 Reserved42[2]; + UINT8 Reserved44[2]; -/** Offset 0x0618 - HECI Timeouts +/** Offset 0x061C - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI $EN_DIS **/ UINT8 HeciTimeouts; -/** Offset 0x0619 - HECI2 Interface Communication +/** Offset 0x061D - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. $EN_DIS **/ UINT8 HeciCommunication2; -/** Offset 0x061A - Check HECI message before send +/** Offset 0x061E - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. $EN_DIS **/ UINT8 DisableMessageCheck; -/** Offset 0x061B - Force ME DID Init Status +/** Offset 0x061F - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS **/ UINT8 DidInitStat; -/** Offset 0x061C - Enable KT device +/** Offset 0x0620 - Enable KT device Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device. $EN_DIS **/ UINT8 KtDeviceEnable; -/** Offset 0x061D - CPU Replaced Polling Disable +/** Offset 0x0621 - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS **/ UINT8 DisableCpuReplacedPolling; -/** Offset 0x061E - Skip CPU replacement check +/** Offset 0x0622 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x061F - Skip MBP HOB +/** Offset 0x0623 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob. $EN_DIS **/ UINT8 SkipMbpHob; -/** Offset 0x0620 - Reserved +/** Offset 0x0624 - Reserved **/ - UINT8 Reserved43[2]; + UINT8 Reserved45[2]; -/** Offset 0x0622 - ISA Serial Base selection +/** Offset 0x0626 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x0623 - PcdSerialDebugBaudRate +/** Offset 0x0627 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. 3:9600, 4:19200, 6:56700, 7:115200 **/ UINT8 PcdSerialDebugBaudRate; -/** Offset 0x0624 - Post Code Output Port +/** Offset 0x0628 - Post Code Output Port This option configures Post Code Output Port **/ UINT16 PostCodeOutputPort; -/** Offset 0x0626 - Reserved +/** Offset 0x062A - Reserved **/ - UINT8 Reserved44[22]; + UINT8 Reserved46[26]; -/** Offset 0x063C - Enable SMBus +/** Offset 0x0644 - Enable SMBus Enable/disable SMBus controller. $EN_DIS **/ UINT8 SmbusEnable; -/** Offset 0x063D - Enable SMBus ARP support +/** Offset 0x0645 - Enable SMBus ARP support Enable SMBus ARP support. $EN_DIS **/ UINT8 SmbusArpEnable; -/** Offset 0x063E - Number of RsvdSmbusAddressTable. +/** Offset 0x0646 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x063F - Reserved +/** Offset 0x0647 - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved47; -/** Offset 0x0640 - SMBUS Base Address +/** Offset 0x0648 - SMBUS Base Address SMBUS Base Address (IO space). **/ UINT16 PchSmbusIoBase; -/** Offset 0x0642 - Enable SMBus Alert Pin +/** Offset 0x064A - Enable SMBus Alert Pin Enable SMBus Alert Pin. $EN_DIS **/ UINT8 PchSmbAlertEnable; -/** Offset 0x0643 - Reserved +/** Offset 0x064B - Reserved **/ - UINT8 Reserved46[13]; + UINT8 Reserved48[13]; -/** Offset 0x0650 - Smbus dynamic power gating +/** Offset 0x0658 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. $EN_DIS **/ UINT8 SmbusDynamicPowerGating; -/** Offset 0x0651 - SMBUS SPD Write Disable +/** Offset 0x0659 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS **/ UINT8 SmbusSpdWriteDisable; -/** Offset 0x0652 - Enable/Disable SA OcSupport +/** Offset 0x065A - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport $EN_DIS **/ UINT8 SaOcSupport; -/** Offset 0x0653 - Reserved +/** Offset 0x065B - Reserved **/ - UINT8 Reserved47[18]; + UINT8 Reserved49[18]; -/** Offset 0x0665 - Over clocking support +/** Offset 0x066D - Over clocking support Over clocking support; 0: Disable; 1: Enable $EN_DIS **/ UINT8 OcSupport; -/** Offset 0x0666 - Reserved +/** Offset 0x066E - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved50; -/** Offset 0x0667 - Realtime Memory Timing +/** Offset 0x066F - Realtime Memory Timing 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE. 0: Disabled, 1: Enabled **/ UINT8 RealtimeMemoryTiming; -/** Offset 0x0668 - core voltage override +/** Offset 0x0670 - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000 **/ UINT16 CoreVoltageOverride; -/** Offset 0x066A - Core Turbo voltage Offset +/** Offset 0x0672 - Core Turbo voltage Offset The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 **/ UINT16 CoreVoltageOffset; -/** Offset 0x066C - Core PLL voltage offset +/** Offset 0x0674 - Core PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 **/ UINT8 CorePllVoltageOffset; -/** Offset 0x066D - AVX2 Ratio Offset +/** Offset 0x0675 - AVX2 Ratio Offset 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. **/ UINT8 Avx2RatioOffset; -/** Offset 0x066E - BCLK Adaptive Voltage Enable +/** Offset 0x0676 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable $EN_DIS **/ UINT8 BclkAdaptiveVoltage; -/** Offset 0x066F - Ring Downbin +/** Offset 0x0677 - Ring Downbin Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable. $EN_DIS **/ UINT8 RingDownBin; -/** Offset 0x0670 - Row Hammer pTRR LFSR0 Mask +/** Offset 0x0678 - Row Hammer pTRR LFSR0 Mask Row Hammer pTRR LFSR0 Mask, 1/2^(value) **/ UINT8 Lfsr0Mask; -/** Offset 0x0671 - Margin Limit Check +/** Offset 0x0679 - Margin Limit Check Margin Limit Check. Choose level of margin check 0:Disable, 1:L1, 2:L2, 3:Both **/ UINT8 MarginLimitCheck; -/** Offset 0x0672 - Row Hammer pTRR LFSR1 Mask +/** Offset 0x067A - Row Hammer pTRR LFSR1 Mask Row Hammer pTRR LFSR1 Mask, 1/2^(value) **/ UINT8 Lfsr1Mask; -/** Offset 0x0673 - Reserved +/** Offset 0x067B - Reserved **/ - UINT8 Reserved49[2]; + UINT8 Reserved51[2]; -/** Offset 0x0675 - TjMax Offset +/** Offset 0x067D - TjMax Offset TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 **/ UINT8 TjMaxOffset; -/** Offset 0x0676 - Reserved +/** Offset 0x067E - Reserved **/ - UINT8 Reserved50[48]; + UINT8 Reserved52[48]; -/** Offset 0x06A6 - Core VF Point Offset +/** Offset 0x06AE - Core VF Point Offset Array used to specifies the Core Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts. **/ UINT16 CoreVfPointOffset[15]; -/** Offset 0x06C4 - Core VF Point Offset Prefix +/** Offset 0x06CC - Core VF Point Offset Prefix Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative. 0:Positive, 1:Negative **/ UINT8 CoreVfPointOffsetPrefix[15]; -/** Offset 0x06D3 - Core VF Point Ratio +/** Offset 0x06DB - Core VF Point Ratio Array for the each selected Core VF Point to display the ration. **/ UINT8 CoreVfPointRatio[15]; -/** Offset 0x06E2 - Reserved +/** Offset 0x06EA - Reserved **/ - UINT8 Reserved51[26]; + UINT8 Reserved53[26]; -/** Offset 0x06FC - Per Core Max Ratio override +/** Offset 0x0704 - Per Core Max Ratio override Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. 0: Disable, 1: enable $EN_DIS **/ UINT8 PerCoreRatioOverride; -/** Offset 0x06FD - Reserved +/** Offset 0x0705 - Reserved **/ - UINT8 Reserved52[25]; + UINT8 Reserved54[25]; -/** Offset 0x0716 - Per Core Current Max Ratio +/** Offset 0x071E - Per Core Current Max Ratio Array for the Per Core Max Ratio **/ UINT8 PerCoreRatio[8]; -/** Offset 0x071E - Reserved +/** Offset 0x0726 - Reserved **/ - UINT8 Reserved53[8]; + UINT8 Reserved55[8]; -/** Offset 0x0726 - Pvd Ratio Threshold for SOC/CPU die +/** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range. As per the die selected, this threshold is applied to SA and MC/CMI PLL @@ -2077,63 +2089,63 @@ **/ UINT8 PvdRatioThreshold; -/** Offset 0x0727 - Reserved +/** Offset 0x072F - Reserved **/ - UINT8 Reserved54[65]; + UINT8 Reserved56[65]; -/** Offset 0x0768 - CPU BCLK OC Frequency +/** Offset 0x0770 - CPU BCLK OC Frequency CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is 40Mhz-1000Mhz. **/ UINT32 CpuBclkOcFrequency; -/** Offset 0x076C - Reserved +/** Offset 0x0774 - Reserved **/ - UINT8 Reserved55[13]; + UINT8 Reserved57[13]; -/** Offset 0x0779 - Avx2 Voltage Guardband Scaling Factor +/** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. **/ UINT8 Avx2VoltageScaleFactor; -/** Offset 0x077A - Ring PLL voltage offset +/** Offset 0x0782 - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 **/ UINT8 RingPllVoltageOffset; -/** Offset 0x077B - Reserved +/** Offset 0x0783 - Reserved **/ - UINT8 Reserved56[5]; + UINT8 Reserved58[5]; -/** Offset 0x0780 - Enable PCH ISH Controller +/** Offset 0x0788 - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller $EN_DIS **/ UINT8 PchIshEnable; -/** Offset 0x0781 - Reserved +/** Offset 0x0789 - Reserved **/ - UINT8 Reserved57; + UINT8 Reserved59; -/** Offset 0x0782 - BiosSize +/** Offset 0x078A - BiosSize The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected Range) so that a BIOS Update Script can be stored in the DPR. **/ UINT16 BiosSize; -/** Offset 0x0784 - BiosGuard +/** Offset 0x078C - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS **/ UINT8 BiosGuard; -/** Offset 0x0785 +/** Offset 0x078D **/ UINT8 BiosGuardToolsInterface; -/** Offset 0x0786 - Txt +/** Offset 0x078E - Txt Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect. 0: Disable, 1: Enable @@ -2141,255 +2153,255 @@ **/ UINT8 Txt; -/** Offset 0x0787 - Skip Stop PBET Timer Enable/Disable +/** Offset 0x078F - Skip Stop PBET Timer Enable/Disable Skip Stop PBET Timer; 0: Disable; 1: Enable $EN_DIS **/ UINT8 SkipStopPbet; -/** Offset 0x0788 - Reserved +/** Offset 0x0790 - Reserved **/ - UINT8 Reserved58[3]; + UINT8 Reserved60[3]; -/** Offset 0x078B - MKTME Key-Id Bits Override Enable +/** Offset 0x0793 - MKTME Key-Id Bits Override Enable Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager (VMM)/hypervisor 0: Disable; 1: Enable. $EN_DIS **/ UINT8 GenerateNewTmeKey; -/** Offset 0x078C - Reserved +/** Offset 0x0794 - Reserved **/ - UINT8 Reserved59[4]; + UINT8 Reserved61[4]; -/** Offset 0x0790 - TME Exclude Base Address +/** Offset 0x0798 - TME Exclude Base Address TME Exclude Base Address. **/ UINT64 TmeExcludeBase; -/** Offset 0x0798 - TME Exclude Size Value +/** Offset 0x07A0 - TME Exclude Size Value TME Exclude Size Value. **/ UINT64 TmeExcludeSize; -/** Offset 0x07A0 - Reserved +/** Offset 0x07A8 - Reserved **/ - UINT8 Reserved60[14]; + UINT8 Reserved62[14]; -/** Offset 0x07AE - BIST on Reset +/** Offset 0x07B6 - BIST on Reset Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 BistOnReset; -/** Offset 0x07AF - Reserved +/** Offset 0x07B7 - Reserved **/ - UINT8 Reserved61; + UINT8 Reserved63; -/** Offset 0x07B0 - Enable or Disable VMX +/** Offset 0x07B8 - Enable or Disable VMX Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x07B1 - Processor Early Power On Configuration FCLK setting +/** Offset 0x07B9 - Processor Early Power On Configuration FCLK setting FCLK frequency can take values of 400MHz, 800MHz and 1GHz. 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved **/ UINT8 FClkFrequency; -/** Offset 0x07B2 - Enable CPU CrashLog +/** Offset 0x07BA - Enable CPU CrashLog Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CpuCrashLogEnable; -/** Offset 0x07B3 - Enable or Disable TME +/** Offset 0x07BB - Enable or Disable TME Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TmeEnable; -/** Offset 0x07B4 - CPU Run Control +/** Offset 0x07BC - CPU Run Control Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: No Change 0:Disabled, 1:Enabled, 2:No Change **/ UINT8 DebugInterfaceEnable; -/** Offset 0x07B5 - CPU Run Control Lock +/** Offset 0x07BD - CPU Run Control Lock Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceLockEnable; -/** Offset 0x07B6 - Enable CPU CrashLog GPRs dump +/** Offset 0x07BE - Enable CPU CrashLog GPRs dump Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only disable Smm GPRs dump 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled **/ UINT8 CrashLogGprs; -/** Offset 0x07B7 - Over clocking Lock +/** Offset 0x07BF - Over clocking Lock Lock Overclocking. 0: Disable; 1: Enable $EN_DIS **/ UINT8 OcLock; -/** Offset 0x07B8 - CPU ratio value +/** Offset 0x07C0 - CPU ratio value This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio set by Hardware (HFM). Valid Range 0 to 63. **/ UINT8 CpuRatio; -/** Offset 0x07B9 - Number of active big cores +/** Offset 0x07C1 - Number of active big cores Number of P-cores to enable in each processor package. Note: Number of P-Cores and E-Cores are looked at together. When both are {0,0 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores **/ UINT8 ActiveCoreCount; -/** Offset 0x07BA - Reserved +/** Offset 0x07C2 - Reserved **/ - UINT8 Reserved62[6]; + UINT8 Reserved64[6]; -/** Offset 0x07C0 - PrmrrSize +/** Offset 0x07C8 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable **/ UINT32 PrmrrSize; -/** Offset 0x07C4 - Tseg Size +/** Offset 0x07CC - Tseg Size Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build 0x0400000:4MB, 0x01000000:16MB **/ UINT32 TsegSize; -/** Offset 0x07C8 - SmmRelocationEnable Enable +/** Offset 0x07D0 - SmmRelocationEnable Enable Enable or Disable SmmRelocationEnable. 0: Disable, 1:Enable $EN_DIS **/ UINT8 SmmRelocationEnable; -/** Offset 0x07C9 - TCC Activation Offset +/** Offset 0x07D1 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts. Default = 0h. **/ UINT8 TccActivationOffset; -/** Offset 0x07CA - Reserved +/** Offset 0x07D2 - Reserved **/ - UINT8 Reserved63[98]; + UINT8 Reserved65[98]; -/** Offset 0x082C - SinitMemorySize +/** Offset 0x0834 - SinitMemorySize Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable **/ UINT32 SinitMemorySize; -/** Offset 0x0830 - TxtDprMemoryBase +/** Offset 0x0838 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable **/ UINT64 TxtDprMemoryBase; -/** Offset 0x0838 - TxtHeapMemorySize +/** Offset 0x0840 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable **/ UINT32 TxtHeapMemorySize; -/** Offset 0x083C - TxtDprMemorySize +/** Offset 0x0844 - TxtDprMemorySize Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize , 1: enable **/ UINT32 TxtDprMemorySize; -/** Offset 0x0840 - TxtLcpPdBase +/** Offset 0x0848 - TxtLcpPdBase Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable **/ UINT64 TxtLcpPdBase; -/** Offset 0x0848 - TxtLcpPdSize +/** Offset 0x0850 - TxtLcpPdSize Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable **/ UINT64 TxtLcpPdSize; -/** Offset 0x0850 - BiosAcmBase +/** Offset 0x0858 - BiosAcmBase Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable **/ UINT64 BiosAcmBase; -/** Offset 0x0858 - BiosAcmSize +/** Offset 0x0860 - BiosAcmSize Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable **/ UINT32 BiosAcmSize; -/** Offset 0x085C - ApStartupBase +/** Offset 0x0864 - ApStartupBase Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable **/ UINT32 ApStartupBase; -/** Offset 0x0860 - TgaSize +/** Offset 0x0868 - TgaSize Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable **/ UINT32 TgaSize; -/** Offset 0x0864 - IsTPMPresence +/** Offset 0x086C - IsTPMPresence IsTPMPresence default values **/ UINT8 IsTPMPresence; -/** Offset 0x0865 - Acoustic Noise Mitigation feature +/** Offset 0x086D - Acoustic Noise Mitigation feature Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x0866 - Reserved +/** Offset 0x086E - Reserved **/ - UINT8 Reserved64[2]; + UINT8 Reserved66[2]; -/** Offset 0x0868 - Platform Power Pmax +/** Offset 0x0870 - Platform Power Pmax PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x086A - Reserved +/** Offset 0x0872 - Reserved **/ - UINT8 Reserved65[12]; + UINT8 Reserved67[12]; -/** Offset 0x0876 - AcLoadline +/** Offset 0x087E - AcLoadline AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. **/ UINT16 AcLoadline[6]; -/** Offset 0x0882 - DcLoadline +/** Offset 0x088A - DcLoadline DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. **/ UINT16 DcLoadline[6]; -/** Offset 0x088E - Reserved +/** Offset 0x0896 - Reserved **/ - UINT8 Reserved66[116]; + UINT8 Reserved68[116]; -/** Offset 0x0902 - Thermal Design Current enable/disable +/** Offset 0x090A - Thermal Design Current enable/disable Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved. **/ UINT8 TdcEnable[6]; -/** Offset 0x0908 - Reserved +/** Offset 0x0910 - Reserved **/ - UINT8 Reserved67[6]; + UINT8 Reserved69[6]; -/** Offset 0x090E - Disable Fast Slew Rate for Deep Package C States for VR domains +/** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are @@ -2398,7 +2410,7 @@ **/ UINT8 FastPkgCRampDisable[6]; -/** Offset 0x0914 - Slew Rate configuration for Deep Package C States for VR domains +/** Offset 0x091C - Slew Rate configuration for Deep Package C States for VR domains Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: @@ -2407,31 +2419,31 @@ **/ UINT8 SlowSlewRate[6]; -/** Offset 0x091A - Reserved +/** Offset 0x0922 - Reserved **/ - UINT8 Reserved68[6]; + UINT8 Reserved70[6]; -/** Offset 0x0920 - Thermal Design Current time window +/** Offset 0x0928 - Thermal Design Current time window Auto = 0 is default. Range is from 1ms to 448s. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved. **/ UINT32 TdcTimeWindow[6]; -/** Offset 0x0938 - Reserved +/** Offset 0x0940 - Reserved **/ - UINT8 Reserved69[8]; + UINT8 Reserved71[8]; -/** Offset 0x0940 - DLVR RFI Enable +/** Offset 0x0948 - DLVR RFI Enable Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DlvrRfiEnable; -/** Offset 0x0941 - Reserved +/** Offset 0x0949 - Reserved **/ - UINT8 Reserved70[13]; + UINT8 Reserved72[13]; -/** Offset 0x094E - VR Fast Vmode ICC Limit support +/** Offset 0x0956 - VR Fast Vmode ICC Limit support Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds to feature disabled (no reactive protection). This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled. @@ -2440,116 +2452,116 @@ **/ UINT16 IccLimit[6]; -/** Offset 0x095A - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. +/** Offset 0x0962 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. Enable/Disable VR FastVmode; 0: Disable; 1: Enable.For all VR by domain 0: Disable, 1: Enable **/ UINT8 EnableFastVmode[6]; -/** Offset 0x0960 - Enable/Disable CEP +/** Offset 0x0968 - Enable/Disable CEP Control for enabling/disabling CEP (Current Excursion Protection). 0: Disable; 1: Enable 0: Disable, 1: Enable **/ UINT8 CepEnable[6]; -/** Offset 0x0966 - Reserved +/** Offset 0x096E - Reserved **/ - UINT8 Reserved71[28]; + UINT8 Reserved73[28]; -/** Offset 0x0982 - PCH Port80 Route +/** Offset 0x098A - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. $EN_DIS **/ UINT8 PchPort80Route; -/** Offset 0x0983 - GPIO Override +/** Offset 0x098B - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use **/ UINT8 GpioOverride; -/** Offset 0x0984 - Reserved +/** Offset 0x098C - Reserved **/ - UINT8 Reserved72[4]; + UINT8 Reserved74[4]; -/** Offset 0x0988 - PMR Size +/** Offset 0x0990 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot **/ UINT32 DmaBufferSize; -/** Offset 0x098C - The policy for VTd driver behavior +/** Offset 0x0994 - The policy for VTd driver behavior BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS **/ UINT8 PreBootDmaMask; -/** Offset 0x098D - State of DMA_CONTROL_GUARANTEE bit in the DMAR table +/** Offset 0x0995 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 DmaControlGuarantee; -/** Offset 0x098E - Disable VT-d +/** Offset 0x0996 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisable; -/** Offset 0x098F - Reserved +/** Offset 0x0997 - Reserved **/ - UINT8 Reserved73; + UINT8 Reserved75; -/** Offset 0x0990 - Base addresses for VT-d function MMIO access +/** Offset 0x0998 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine **/ UINT32 VtdBaseAddress[9]; -/** Offset 0x09B4 - Reserved +/** Offset 0x09BC - Reserved **/ - UINT8 Reserved74[20]; + UINT8 Reserved76[20]; -/** Offset 0x09C8 - MMIO Size +/** Offset 0x09D0 - MMIO Size Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB **/ UINT16 MmioSize; -/** Offset 0x09CA - MMIO size adjustment for AUTO mode +/** Offset 0x09D2 - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size **/ UINT16 MmioSizeAdjustment; -/** Offset 0x09CC - Reserved +/** Offset 0x09D4 - Reserved **/ - UINT8 Reserved75[36]; + UINT8 Reserved77[36]; -/** Offset 0x09F0 - Enable above 4GB MMIO resource support +/** Offset 0x09F8 - Enable above 4GB MMIO resource support Enable/disable above 4GB MMIO resource support $EN_DIS **/ UINT8 EnableAbove4GBMmio; -/** Offset 0x09F1 - Enable/Disable SA CRID +/** Offset 0x09F9 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS **/ UINT8 CridEnable; -/** Offset 0x09F2 - Reserved +/** Offset 0x09FA - Reserved **/ - UINT8 Reserved76[10]; + UINT8 Reserved78[10]; -/** Offset 0x09FC - Enable/Disable CrashLog Device +/** Offset 0x0A04 - Enable/Disable CrashLog Device Enable or Disable CrashLog/Telemetry Device 0- Disable, 1- Enable $EN_DIS **/ UINT32 CpuCrashLogDevice; -/** Offset 0x0A00 - Reserved +/** Offset 0x0A08 - Reserved **/ - UINT8 Reserved77[20]; + UINT8 Reserved79[20]; -/** Offset 0x0A14 - Platform Debug Option +/** Offset 0x0A1C - Platform Debug Option Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n \n Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n @@ -2562,122 +2574,122 @@ **/ UINT8 PlatformDebugOption; -/** Offset 0x0A15 - Reserved +/** Offset 0x0A1D - Reserved **/ - UINT8 Reserved78[14]; + UINT8 Reserved80[14]; -/** Offset 0x0A23 - Program GPIOs for LFP on DDI port-A device +/** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortAConfig; -/** Offset 0x0A24 - Reserved +/** Offset 0x0A2C - Reserved **/ - UINT8 Reserved79[2]; + UINT8 Reserved81[2]; -/** Offset 0x0A26 - Program GPIOs for LFP on DDI port-B device +/** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device 0(Default)=Disabled,1=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortBConfig; -/** Offset 0x0A27 - Enable or disable HPD of DDI port A +/** Offset 0x0A2F - Enable or disable HPD of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortAHpd; -/** Offset 0x0A28 - Enable or disable HPD of DDI port B +/** Offset 0x0A30 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBHpd; -/** Offset 0x0A29 - Enable or disable HPD of DDI port C +/** Offset 0x0A31 - Enable or disable HPD of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCHpd; -/** Offset 0x0A2A - Enable or disable HPD of DDI port 1 +/** Offset 0x0A32 - Enable or disable HPD of DDI port 1 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPort1Hpd; -/** Offset 0x0A2B - Enable or disable HPD of DDI port 2 +/** Offset 0x0A33 - Enable or disable HPD of DDI port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Hpd; -/** Offset 0x0A2C - Enable or disable HPD of DDI port 3 +/** Offset 0x0A34 - Enable or disable HPD of DDI port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Hpd; -/** Offset 0x0A2D - Enable or disable HPD of DDI port 4 +/** Offset 0x0A35 - Enable or disable HPD of DDI port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Hpd; -/** Offset 0x0A2E - Enable or disable DDC of DDI port A +/** Offset 0x0A36 - Enable or disable DDC of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortADdc; -/** Offset 0x0A2F - Enable or disable DDC of DDI port B +/** Offset 0x0A37 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBDdc; -/** Offset 0x0A30 - Enable or disable DDC of DDI port C +/** Offset 0x0A38 - Enable or disable DDC of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCDdc; -/** Offset 0x0A31 - Enable DDC setting of DDI Port 1 +/** Offset 0x0A39 - Enable DDC setting of DDI Port 1 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort1Ddc; -/** Offset 0x0A32 - Enable DDC setting of DDI Port 2 +/** Offset 0x0A3A - Enable DDC setting of DDI Port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Ddc; -/** Offset 0x0A33 - Enable DDC setting of DDI Port 3 +/** Offset 0x0A3B - Enable DDC setting of DDI Port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Ddc; -/** Offset 0x0A34 - Enable DDC setting of DDI Port 4 +/** Offset 0x0A3C - Enable DDC setting of DDI Port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Ddc; -/** Offset 0x0A35 - Reserved +/** Offset 0x0A3D - Reserved **/ - UINT8 Reserved80[3]; + UINT8 Reserved82[3]; -/** Offset 0x0A38 - Temporary MMIO address for GMADR +/** Offset 0x0A40 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1) **/ UINT64 LMemBar; -/** Offset 0x0A40 - Temporary MMIO address for GTTMMADR +/** Offset 0x0A48 - Temporary MMIO address for GTTMMADR The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO @@ -2685,142 +2697,148 @@ **/ UINT64 GttMmAdr; -/** Offset 0x0A48 - Reserved +/** Offset 0x0A50 - Reserved **/ - UINT8 Reserved81[2]; + UINT8 Reserved83[2]; -/** Offset 0x0A4A - Enable/Disable Memory Bandwidth Compression +/** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 MemoryBandwidthCompression; -/** Offset 0x0A4B - Panel Power Enable +/** Offset 0x0A53 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 PanelPowerEnable; -/** Offset 0x0A4C - Selection of the primary display device +/** Offset 0x0A54 - Selection of the primary display device 3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics 3:AUTO, 0:IGFX, 4:HG **/ UINT8 PrimaryDisplay; -/** Offset 0x0A4D - Internal Graphics Data Stolen Memory GSM2 +/** Offset 0x0A55 - Internal Graphics Data Stolen Memory GSM2 Size of memory preallocated for internal graphics GSM2. 0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB, 11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation **/ UINT8 IGpuGsm2Size; -/** Offset 0x0A4E - Reserved +/** Offset 0x0A56 - Reserved **/ - UINT8 Reserved82[2]; + UINT8 Reserved84[2]; -/** Offset 0x0A50 - Intel Graphics VBT (Video BIOS Table) Size +/** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image **/ UINT32 VbtSize; -/** Offset 0x0A54 - Reserved +/** Offset 0x0A5C - Reserved **/ - UINT8 Reserved83[4]; + UINT8 Reserved85[4]; -/** Offset 0x0A58 - Graphics Configuration Ptr +/** Offset 0x0A60 - Graphics Configuration Ptr Points to VBT **/ UINT64 VbtPtr; -/** Offset 0x0A60 - SOL Training Message Pointer +/** Offset 0x0A68 - SOL Training Message Pointer Points to SOL Message String **/ UINT64 VgaMessage; -/** Offset 0x0A68 - Platform LID Status for LFP Displays. +/** Offset 0x0A70 - Platform LID Status for LFP Displays. LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. 0: LidClosed, 1: LidOpen **/ UINT8 LidStatus; -/** Offset 0x0A69 - Control SOL VGA Initialition sequence - Initialise SOL Init - 0x0: NO SOL VGA Init, 0x1: SOL VGA Init +/** Offset 0x0A71 - Control SOL VGA Initialition sequence + Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),, + BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported, + 1: NO VGA Exit) + 0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA **/ UINT8 VgaInitControl; -/** Offset 0x0A6A - TCSS USB HOST (xHCI) Enable +/** Offset 0x0A72 - Reserved +**/ + UINT8 Reserved86[16]; + +/** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below $EN_DIS **/ UINT8 TcssXhciEn; -/** Offset 0x0A6B - Reserved +/** Offset 0x0A83 - Reserved **/ - UINT8 Reserved84[4]; + UINT8 Reserved87[4]; -/** Offset 0x0A6F - TCSS Type C Port 0 +/** Offset 0x0A87 - TCSS Type C Port 0 Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN **/ UINT8 TcssPort0; -/** Offset 0x0A70 - TCSS Type C Port 1 +/** Offset 0x0A88 - TCSS Type C Port 1 Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN **/ UINT8 TcssPort1; -/** Offset 0x0A71 - TCSS Type C Port 2 +/** Offset 0x0A89 - TCSS Type C Port 2 Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN **/ UINT8 TcssPort2; -/** Offset 0x0A72 - TCSS Type C Port 3 +/** Offset 0x0A8A - TCSS Type C Port 3 Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN **/ UINT8 TcssPort3; -/** Offset 0x0A73 - Reserved +/** Offset 0x0A8B - Reserved **/ - UINT8 Reserved85; + UINT8 Reserved88; -/** Offset 0x0A74 - TypeC port GPIO setting +/** Offset 0x0A8C - TypeC port GPIO setting GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake) **/ UINT32 IomTypeCPortPadCfg[12]; -/** Offset 0x0AA4 - TCSS Aux Orientation Override Enable +/** Offset 0x0ABC - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x0AA6 - TCSS HSL Orientation Override Enable +/** Offset 0x0ABE - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x0AA8 - CNVi DDR RFI Mitigation +/** Offset 0x0AC0 - CNVi DDR RFI Mitigation Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviDdrRfim; -/** Offset 0x0AA9 - SOC Trace Hub Mode +/** Offset 0x0AC1 - SOC Trace Hub Mode Enable/Disable SOC TraceHub $EN_DIS **/ UINT8 SocTraceHubMode; -/** Offset 0x0AAA - SOC Trace Hub Memory Region 0 buffer Size +/** Offset 0x0AC2 - SOC Trace Hub Memory Region 0 buffer Size Select size of memory region 0 buffer. Memory allocated by BIOS only applies to ITH tool running on the host. For ITH tool running on the target, choose None/OS, memory shall be allocated by tool. User should be cautious to choose the amount @@ -2831,7 +2849,7 @@ **/ UINT16 SocTraceHubMemReg0Size; -/** Offset 0x0AAC - SOC Trace Hub Memory Region 0 buffer Size +/** Offset 0x0AC4 - SOC Trace Hub Memory Region 0 buffer Size Select size of memory region 1 buffer. Memory allocated by BIOS only applies to ITH tool running on the host. For ITH tool running on the target, choose None/OS, memory shall be allocated by tool. User should be cautious to choose the amount @@ -2842,7 +2860,7 @@ **/ UINT16 SocTraceHubMemReg1Size; -/** Offset 0x0AAE - Internal Graphics Pre-allocated Memory +/** Offset 0x0AC6 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, @@ -2850,175 +2868,195 @@ **/ UINT16 IgdDvmt50PreAlloc; -/** Offset 0x0AB0 - Internal Graphics +/** Offset 0x0AC8 - Internal Graphics Enable/disable internal graphics. $EN_DIS **/ UINT8 InternalGraphics; -/** Offset 0x0AB1 - Reserved +/** Offset 0x0AC9 - Reserved **/ - UINT8 Reserved86[7]; + UINT8 Reserved89; -/** Offset 0x0AB8 - DynamicMemoryBoost +/** Offset 0x0ACA - DLL Weak Lock Support + Enables/Disable DLL Weak Lock Support + $EN_DIS +**/ + UINT8 WeaklockEn; + +/** Offset 0x0ACB - Reserved +**/ + UINT8 Reserved90; + +/** Offset 0x0ACC - Rx DQS Delay Comp Support + Enables/Disable Rx DQS Delay Comp Support + $EN_DIS +**/ + UINT8 RxDqsDelayCompEn; + +/** Offset 0x0ACD - Reserved +**/ + UINT8 Reserved91[7]; + +/** Offset 0x0AD4 - DynamicMemoryBoost Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled. $EN_DIS **/ UINT32 DynamicMemoryBoost; -/** Offset 0x0ABC - RealtimeMemoryFrequency +/** Offset 0x0AD8 - RealtimeMemoryFrequency Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled. $EN_DIS **/ UINT32 RealtimeMemoryFrequency; -/** Offset 0x0AC0 - Reserved +/** Offset 0x0ADC - Reserved **/ - UINT8 Reserved87[9]; + UINT8 Reserved92[9]; -/** Offset 0x0AC9 - Vref Offset +/** Offset 0x0AE5 - Vref Offset Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset 0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6 **/ UINT8 VrefOffset; -/** Offset 0x0ACA - Reserved +/** Offset 0x0AE6 - Reserved **/ - UINT8 Reserved88[2]; + UINT8 Reserved93[2]; -/** Offset 0x0ACC - tRRSG Delta +/** Offset 0x0AE8 - tRRSG Delta Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRRSG; -/** Offset 0x0ACD - tRRDG Delta +/** Offset 0x0AE9 - tRRDG Delta Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRRDG; -/** Offset 0x0ACE - tRRDR Delta +/** Offset 0x0AEA - tRRDR Delta Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRRDR; -/** Offset 0x0ACF - tRRDD Delta +/** Offset 0x0AEB - tRRDD Delta Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRRDD; -/** Offset 0x0AD0 - tWRSG Delta +/** Offset 0x0AEC - tWRSG Delta Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWRSG; -/** Offset 0x0AD1 - tWRDG Delta +/** Offset 0x0AED - tWRDG Delta Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWRDG; -/** Offset 0x0AD2 - tWRDR Delta +/** Offset 0x0AEE - tWRDR Delta Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWRDR; -/** Offset 0x0AD3 - tWRDD Delta +/** Offset 0x0AEF - tWRDD Delta Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWRDD; -/** Offset 0x0AD4 - tWWSG Delta +/** Offset 0x0AF0 - tWWSG Delta Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWWSG; -/** Offset 0x0AD5 - tWWDG Delta +/** Offset 0x0AF1 - tWWDG Delta Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWWDG; -/** Offset 0x0AD6 - tWWDR Delta +/** Offset 0x0AF2 - tWWDR Delta Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWWDR; -/** Offset 0x0AD7 - tWWDD Delta +/** Offset 0x0AF3 - tWWDD Delta Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWWDD; -/** Offset 0x0AD8 - tRWSG Delta +/** Offset 0x0AF4 - tRWSG Delta Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRWSG; -/** Offset 0x0AD9 - tRWDG Delta +/** Offset 0x0AF5 - tRWDG Delta Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRWDG; -/** Offset 0x0ADA - tRWDR Delta +/** Offset 0x0AF6 - tRWDR Delta Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRWDR; -/** Offset 0x0ADB - tRWDD Delta +/** Offset 0x0AF7 - tRWDD Delta Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRWDD; -/** Offset 0x0ADC - Reserved +/** Offset 0x0AF8 - Reserved **/ - UINT8 Reserved89[13]; + UINT8 Reserved94[13]; -/** Offset 0x0AE9 - PPR ForceRepair +/** Offset 0x0B05 - PPR ForceRepair When Eanble, PPR will force repair some rows many times (90) $EN_DIS **/ UINT8 PprForceRepair; -/** Offset 0x0AEA - PPR Repair Bank +/** Offset 0x0B06 - PPR Repair Bank PPR repair Bank: User chooses to force repair specifc address **/ UINT8 PprRepairBank; -/** Offset 0x0AEB - Reserved +/** Offset 0x0B07 - Reserved **/ - UINT8 Reserved90[53]; + UINT8 Reserved95[49]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3037,11 +3075,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0B20 +/** Offset 0x0B38 **/ - UINT8 UnusedUpdSpace0[6]; + UINT8 FspmRsvd3834[6]; -/** Offset 0x0B26 +/** Offset 0x0B3E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h index a6dde65..3dd46ff 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h @@ -408,212 +408,212 @@ /** Offset 0x013D - Reserved **/ - UINT8 Reserved10[4]; + UINT8 Reserved10[5]; -/** Offset 0x0141 - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x0142 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x0142 - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x0143 - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x0143 - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x0144 - Enable or Disable Monitor /MWAIT instructions Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner should not set in MWAIT Loop. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0144 - Enable or Disable initialization of machine check registers +/** Offset 0x0145 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x0145 - Control on Processor Trace output scheme +/** Offset 0x0146 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x0146 - Enable or Disable Processor Trace feature +/** Offset 0x0147 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x0147 - Reserved +/** Offset 0x0148 - Reserved **/ UINT8 Reserved11[3]; -/** Offset 0x014A - UFS enable/disable +/** Offset 0x014B - UFS enable/disable Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller 0 and (0,1) to enable controller 1 $EN_DIS **/ UINT8 UfsEnable[2]; -/** Offset 0x014C - Reserved +/** Offset 0x014D - Reserved **/ - UINT8 Reserved12[2]; + UINT8 Reserved12[4]; -/** Offset 0x014E - Enable/Disable PCIe tunneling for USB4 +/** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4 Enable/Disable PCIe tunneling for USB4, default is enable $EN_DIS **/ UINT8 ITbtPcieTunnelingForUsb4; -/** Offset 0x014F - Reserved +/** Offset 0x0152 - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved13[2]; -/** Offset 0x0150 - ITBTForcePowerOn Timeout value +/** Offset 0x0154 - ITBTForcePowerOn Timeout value ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. 100 = 100 ms. **/ UINT16 ITbtForcePowerOnTimeoutInMs; -/** Offset 0x0152 - ITbtConnectTopology Timeout value +/** Offset 0x0156 - ITbtConnectTopology Timeout value ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms. **/ UINT16 ITbtConnectTopologyTimeoutInMs; -/** Offset 0x0154 - ITBT DMA LTR +/** Offset 0x0158 - ITBT DMA LTR TCSS DMA1, DMA2 LTR value **/ UINT16 ITbtDmaLtr[2]; -/** Offset 0x0158 - ITbt Usb4CmMode value +/** Offset 0x015C - ITbt Usb4CmMode value ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM **/ UINT8 Usb4CmMode; -/** Offset 0x0159 - Reserved +/** Offset 0x015D - Reserved **/ - UINT8 Reserved14[15]; + UINT8 Reserved14[19]; -/** Offset 0x0168 - IEH Mode +/** Offset 0x0170 - IEH Mode Integrated Error Handler Mode, 0: Bypass, 1: Enable 0: Bypass, 1:Enable **/ UINT8 IehMode; -/** Offset 0x0169 - RTC BIOS Interface Lock +/** Offset 0x0171 - RTC BIOS Interface Lock Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. $EN_DIS **/ UINT8 RtcBiosInterfaceLock; -/** Offset 0x016A - RTC Cmos Memory Lock +/** Offset 0x0172 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x016B - AMT Switch +/** Offset 0x0173 - AMT Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS **/ UINT8 AmtEnabled; -/** Offset 0x016C - SOL Switch +/** Offset 0x0174 - SOL Switch Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtSolEnabled; -/** Offset 0x016D - WatchDog Timer Switch +/** Offset 0x0175 - WatchDog Timer Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 WatchDogEnabled; -/** Offset 0x016E - OS Timer +/** Offset 0x0176 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerOs; -/** Offset 0x0170 - BIOS Timer +/** Offset 0x0178 - BIOS Timer 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerBios; -/** Offset 0x0172 - Iax Switch +/** Offset 0x017A - Iax Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable Iax functionality. $EN_DIS **/ UINT8 IaxEnable; -/** Offset 0x0173 - Reserved +/** Offset 0x017B - Reserved **/ UINT8 Reserved15; -/** Offset 0x0174 - ISH GP GPIO Pin Muxing +/** Offset 0x017C - ISH GP GPIO Pin Muxing Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER **/ UINT32 IshGpGpioPinMuxing[12]; -/** Offset 0x01A4 - ISH UART Rx Pin Muxing +/** Offset 0x01AC - ISH UART Rx Pin Muxing Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* **/ UINT32 IshUartRxPinMuxing[3]; -/** Offset 0x01B0 - ISH UART Tx Pin Muxing +/** Offset 0x01B8 - ISH UART Tx Pin Muxing Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* **/ UINT32 IshUartTxPinMuxing[3]; -/** Offset 0x01BC - ISH UART Rts Pin Muxing +/** Offset 0x01C4 - ISH UART Rts Pin Muxing Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. **/ UINT32 IshUartRtsPinMuxing[3]; -/** Offset 0x01C8 - ISH UART Rts Pin Muxing +/** Offset 0x01D0 - ISH UART Rts Pin Muxing Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. **/ UINT32 IshUartCtsPinMuxing[3]; -/** Offset 0x01D4 - ISH I2C SDA Pin Muxing +/** Offset 0x01DC - ISH I2C SDA Pin Muxing Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. **/ UINT32 IshI2cSdaPinMuxing[3]; -/** Offset 0x01E0 - ISH I2C SCL Pin Muxing +/** Offset 0x01E8 - ISH I2C SCL Pin Muxing Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. **/ UINT32 IshI2cSclPinMuxing[3]; -/** Offset 0x01EC - ISH SPI MOSI Pin Muxing +/** Offset 0x01F4 - ISH SPI MOSI Pin Muxing Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. **/ UINT32 IshSpiMosiPinMuxing[2]; -/** Offset 0x01F4 - ISH SPI MISO Pin Muxing +/** Offset 0x01FC - ISH SPI MISO Pin Muxing Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. **/ UINT32 IshSpiMisoPinMuxing[2]; -/** Offset 0x01FC - ISH SPI CLK Pin Muxing +/** Offset 0x0204 - ISH SPI CLK Pin Muxing Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. **/ UINT32 IshSpiClkPinMuxing[2]; -/** Offset 0x0204 - ISH SPI CS#N Pin Muxing +/** Offset 0x020C - ISH SPI CS#N Pin Muxing Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible values. N-SPI number, 0-1. **/ UINT32 IshSpiCsPinMuxing[4]; -/** Offset 0x0214 - ISH GP GPIO Pad termination +/** Offset 0x021C - ISH GP GPIO Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index @@ -621,7 +621,7 @@ **/ UINT8 IshGpGpioPadTermination[12]; -/** Offset 0x0220 - ISH UART Rx Pad termination +/** Offset 0x0228 - ISH UART Rx Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 @@ -629,7 +629,7 @@ **/ UINT8 IshUartRxPadTermination[3]; -/** Offset 0x0223 - ISH UART Tx Pad termination +/** Offset 0x022B - ISH UART Tx Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 @@ -637,7 +637,7 @@ **/ UINT8 IshUartTxPadTermination[3]; -/** Offset 0x0226 - ISH UART Rts Pad termination +/** Offset 0x022E - ISH UART Rts Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 @@ -645,7 +645,7 @@ **/ UINT8 IshUartRtsPadTermination[3]; -/** Offset 0x0229 - ISH UART Rts Pad termination +/** Offset 0x0231 - ISH UART Rts Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 @@ -653,7 +653,7 @@ **/ UINT8 IshUartCtsPadTermination[3]; -/** Offset 0x022C - ISH I2C SDA Pad termination +/** Offset 0x0234 - ISH I2C SDA Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, @@ -661,7 +661,7 @@ **/ UINT8 IshI2cSdaPadTermination[3]; -/** Offset 0x022F - ISH I2C SCL Pad termination +/** Offset 0x0237 - ISH I2C SCL Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, @@ -669,7 +669,7 @@ **/ UINT8 IshI2cSclPadTermination[3]; -/** Offset 0x0232 - ISH SPI MOSI Pad termination +/** Offset 0x023A - ISH SPI MOSI Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 @@ -677,7 +677,7 @@ **/ UINT8 IshSpiMosiPadTermination[2]; -/** Offset 0x0234 - ISH SPI MISO Pad termination +/** Offset 0x023C - ISH SPI MISO Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 @@ -685,7 +685,7 @@ **/ UINT8 IshSpiMisoPadTermination[2]; -/** Offset 0x0236 - ISH SPI CLK Pad termination +/** Offset 0x023E - ISH SPI CLK Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, @@ -693,7 +693,7 @@ **/ UINT8 IshSpiClkPadTermination[2]; -/** Offset 0x0238 - ISH SPI CS#N Pad termination +/** Offset 0x0240 - ISH SPI CS#N Pad termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 @@ -701,68 +701,68 @@ **/ UINT8 IshSpiCsPadTermination[4]; -/** Offset 0x023C - Enable PCH ISH SPI Cs#N pins assigned +/** Offset 0x0244 - Enable PCH ISH SPI Cs#N pins assigned Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs number: 0-1 **/ UINT8 PchIshSpiCsEnable[4]; -/** Offset 0x0240 - Enable PCH ISH SPI Cs0 pins assigned +/** Offset 0x0248 - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiCs0Enable[1]; -/** Offset 0x0241 - Enable PCH ISH SPI pins assigned +/** Offset 0x0249 - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiEnable[1]; -/** Offset 0x0242 - Enable PCH ISH UART pins assigned +/** Offset 0x024A - Enable PCH ISH UART pins assigned Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshUartEnable[2]; -/** Offset 0x0244 - Enable PCH ISH I2C pins assigned +/** Offset 0x024C - Enable PCH ISH I2C pins assigned Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI2cEnable[3]; -/** Offset 0x0247 - Enable PCH ISH GP pins assigned +/** Offset 0x024F - Enable PCH ISH GP pins assigned Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshGpEnable[12]; -/** Offset 0x0253 - PCH ISH PDT Unlock Msg +/** Offset 0x025B - PCH ISH PDT Unlock Msg 0: False; 1: True. $EN_DIS **/ UINT8 PchIshPdtUnlock; -/** Offset 0x0254 - Reserved +/** Offset 0x025C - Reserved **/ UINT8 Reserved16; -/** Offset 0x0255 - End of Post message +/** Offset 0x025D - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x0256 - D0I3 Setting for HECI Disable +/** Offset 0x025E - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x0257 - Mctp Broadcast Cycle +/** Offset 0x025F - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0258 - ME Unconfig on RTC clear +/** Offset 0x0260 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -770,146 +770,146 @@ **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0259 - Reserved +/** Offset 0x0261 - Reserved **/ UINT8 Reserved17[22]; -/** Offset 0x026F - Enable PCH ISH I3C pins assigned +/** Offset 0x0277 - Enable PCH ISH I3C pins assigned Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI3cEnable[2]; -/** Offset 0x0271 - Reserved +/** Offset 0x0279 - Reserved **/ UINT8 Reserved18[3]; -/** Offset 0x0274 - Power button debounce configuration +/** Offset 0x027C - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range **/ UINT32 PmcPowerButtonDebounce; -/** Offset 0x0278 - PCH USB2 PHY Power Gating enable +/** Offset 0x0280 - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS **/ UINT8 PmcUsb2PhySusPgEnable; -/** Offset 0x0279 - VRAlert# Pin +/** Offset 0x0281 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmVrAlert; -/** Offset 0x027A - ModPHY SUS Power Domain Dynamic Gating +/** Offset 0x0282 - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcModPhySusPgEnable; -/** Offset 0x027B - V1p05-PHY supply external FET control +/** Offset 0x0283 - V1p05-PHY supply external FET control Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY supply. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcV1p05PhyExtFetControlEn; -/** Offset 0x027C - V1p05-IS supply external FET control +/** Offset 0x0284 - V1p05-IS supply external FET control Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcV1p05IsExtFetControlEn; -/** Offset 0x027D - PCH Pm PME_B0_S5_DIS +/** Offset 0x0285 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x027E - PCH Pm Wol Enable Override +/** Offset 0x0286 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x027F - PCH Pm WoW lan Enable +/** Offset 0x0287 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x0280 - PCH Pm Slp S3 Min Assert +/** Offset 0x0288 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x0281 - PCH Pm Slp S4 Min Assert +/** Offset 0x0289 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x0282 - PCH Pm Slp Sus Min Assert +/** Offset 0x028A - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x0283 - PCH Pm Slp A Min Assert +/** Offset 0x028B - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x0284 - PCH Pm Slp Strch Sus Up +/** Offset 0x028C - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x0285 - PCH Pm Slp Lan Low Dc +/** Offset 0x028D - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x0286 - PCH Pm Pwr Btn Override Period +/** Offset 0x028E - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x0287 - PCH Pm Disable Native Power Button +/** Offset 0x028F - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x0288 - PCH Pm ME_WAKE_STS +/** Offset 0x0290 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x0289 - PCH Pm WOL_OVR_WK_STS +/** Offset 0x0291 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x028A - PCH Pm Reset Power Cycle Duration +/** Offset 0x0292 - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x028B - PCH Pm Pcie Pll Ssc +/** Offset 0x0293 - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x028C - Enable TCO timer. +/** Offset 0x0294 - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -917,7 +917,7 @@ **/ UINT8 EnableTcoTimer; -/** Offset 0x028D - Enable PS_ON. +/** Offset 0x0295 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -925,1290 +925,1290 @@ **/ UINT8 PsOnEnable; -/** Offset 0x028E - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x0296 - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x028F - OS IDLE Mode Enable +/** Offset 0x0297 - OS IDLE Mode Enable Enable/Disable OS Idle Mode $EN_DIS **/ UINT8 PmcOsIdleEnable; -/** Offset 0x0290 - S0ix Auto-Demotion +/** Offset 0x0298 - S0ix Auto-Demotion Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. $EN_DIS **/ UINT8 PchS0ixAutoDemotion; -/** Offset 0x0291 - Latch Events C10 Exit +/** Offset 0x0299 - Latch Events C10 Exit When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default) $EN_DIS **/ UINT8 PchPmLatchEventsC10Exit; -/** Offset 0x0292 - PCH Energy Reporting +/** Offset 0x029A - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x0293 - Low Power Mode Enable/Disable config mask +/** Offset 0x029B - Low Power Mode Enable/Disable config mask Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. **/ UINT8 PmcLpmS0ixSubStateEnableMask; -/** Offset 0x0294 - Reserved +/** Offset 0x029C - Reserved **/ UINT8 Reserved19; -/** Offset 0x0295 - PMC C10 dynamic threshold dajustment enable +/** Offset 0x029D - PMC C10 dynamic threshold dajustment enable Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs $EN_DIS **/ UINT8 PmcC10DynamicThresholdAdjustment; -/** Offset 0x0296 - Enable LOCKDOWN BIOS LOCK +/** Offset 0x029E - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x0297 - Enable LOCKDOWN SMI +/** Offset 0x029F - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0298 - Enable LOCKDOWN BIOS Interface +/** Offset 0x02A0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0299 - Unlock all GPIO pads +/** Offset 0x02A1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x029A - PCH Flash Protection Ranges Write Enble +/** Offset 0x02A2 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x029F - PCH Flash Protection Ranges Read Enble +/** Offset 0x02A7 - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x02A4 - PCH Protect Range Limit +/** Offset 0x02AC - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x02AE - PCH Protect Range Base +/** Offset 0x02B6 - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x02B8 - PCIe PTM enable/disable +/** Offset 0x02C0 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. **/ UINT8 PciePtm[28]; -/** Offset 0x02D4 - PCH PCIe root port connection type +/** Offset 0x02DC - PCH PCIe root port connection type 0: built-in device, 1:slot **/ UINT8 PcieRpSlotImplemented[28]; -/** Offset 0x02F0 - PCIE RP Access Control Services Extended Capability +/** Offset 0x02F8 - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ UINT8 PcieRpAcsEnabled[28]; -/** Offset 0x030C - PCIE RP Clock Power Management +/** Offset 0x0314 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 PcieRpEnableCpm[28]; -/** Offset 0x0328 - PCIE RP Detect Timeout Ms +/** Offset 0x0330 - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 PcieRpDetectTimeoutMs[24]; -/** Offset 0x0358 - Enable PCIE RP HotPlug +/** Offset 0x0360 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[28]; -/** Offset 0x0374 - Enable PCIE RP Pm Sci +/** Offset 0x037C - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[28]; -/** Offset 0x0390 - Enable PCIE RP Transmitter Half Swing +/** Offset 0x0398 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 PcieRpTransmitterHalfSwing[28]; -/** Offset 0x03AC - Enable PCIE RP Clk Req Detect +/** Offset 0x03B4 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[28]; -/** Offset 0x03C8 - PCIE RP Advanced Error Report +/** Offset 0x03D0 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[28]; -/** Offset 0x03E4 - PCIE RP Unsupported Request Report +/** Offset 0x03EC - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 PcieRpUnsupportedRequestReport[28]; -/** Offset 0x0400 - PCIE RP Fatal Error Report +/** Offset 0x0408 - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 PcieRpFatalErrorReport[28]; -/** Offset 0x041C - PCIE RP No Fatal Error Report +/** Offset 0x0424 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 PcieRpNoFatalErrorReport[28]; -/** Offset 0x0438 - PCIE RP Correctable Error Report +/** Offset 0x0440 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 PcieRpCorrectableErrorReport[28]; -/** Offset 0x0454 - PCIE RP System Error On Fatal Error +/** Offset 0x045C - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnFatalError[28]; -/** Offset 0x0470 - PCIE RP System Error On Non Fatal Error +/** Offset 0x0478 - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnNonFatalError[28]; -/** Offset 0x048C - PCIE RP System Error On Correctable Error +/** Offset 0x0494 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 PcieRpSystemErrorOnCorrectableError[28]; -/** Offset 0x04A8 - PCIE RP Max Payload +/** Offset 0x04B0 - PCIE RP Max Payload Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[28]; -/** Offset 0x04C4 - PCIE RP Pcie Speed +/** Offset 0x04CC - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCIE_SPEED). **/ UINT8 PcieRpPcieSpeed[28]; -/** Offset 0x04E0 - PCIE RP Physical Slot Number +/** Offset 0x04E8 - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 PcieRpPhysicalSlotNumber[28]; -/** Offset 0x04FC - PCIE RP Completion Timeout +/** Offset 0x0504 - PCIE RP Completion Timeout The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. **/ UINT8 PcieRpCompletionTimeout[28]; -/** Offset 0x0518 - PCIE RP Aspm +/** Offset 0x0520 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[28]; -/** Offset 0x0534 - Reserved +/** Offset 0x053C - Reserved **/ UINT8 Reserved20[28]; -/** Offset 0x0550 - PCIE RP L1 Substates +/** Offset 0x0558 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[28]; -/** Offset 0x056C - PCIE RP Ltr Enable +/** Offset 0x0574 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[28]; -/** Offset 0x0588 - PCIE RP Ltr Config Lock +/** Offset 0x0590 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 PcieRpLtrConfigLock[28]; -/** Offset 0x05A4 - PCIE RP override default settings for EQ +/** Offset 0x05AC - PCIE RP override default settings for EQ Choose PCIe EQ method $EN_DIS **/ UINT8 PcieEqOverrideDefault[12]; -/** Offset 0x05B0 - Reserved +/** Offset 0x05B8 - Reserved **/ UINT8 Reserved21[1525]; -/** Offset 0x0BA5 - PCIE RP Enable Peer Memory Write +/** Offset 0x0BAD - PCIE RP Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite[12]; -/** Offset 0x0BB1 - Assertion on Link Down GPIOs +/** Offset 0x0BB9 - Assertion on Link Down GPIOs GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs 0:Disable, 1:Enable **/ UINT8 PcieRpLinkDownGpios[12]; -/** Offset 0x0BBD - PCIE Compliance Test Mode +/** Offset 0x0BC5 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x0BBE - PCIE Rp Function Swap +/** Offset 0x0BC6 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0BBF - Reserved +/** Offset 0x0BC7 - Reserved **/ UINT8 Reserved22[12]; -/** Offset 0x0BCB - PCIe RootPort Power Gating +/** Offset 0x0BD3 - PCIe RootPort Power Gating Describes whether the PCI Express Power Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default). $EN_DIS **/ UINT8 PciePowerGating[12]; -/** Offset 0x0BD7 - Reserved +/** Offset 0x0BDF - Reserved **/ UINT8 Reserved23[49]; -/** Offset 0x0C08 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0C10 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[24]; -/** Offset 0x0C38 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0C40 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[24]; -/** Offset 0x0C68 - PCIE RP Snoop Latency Override Mode +/** Offset 0x0C70 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[28]; -/** Offset 0x0C84 - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0C8C - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[28]; -/** Offset 0x0CA0 - PCIE RP Snoop Latency Override Value +/** Offset 0x0CA8 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[24]; -/** Offset 0x0CD0 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0CD8 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[28]; -/** Offset 0x0CEC - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x0CF4 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28]; -/** Offset 0x0D08 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x0D10 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; -/** Offset 0x0D38 - PCIE RP Slot Power Limit Scale +/** Offset 0x0D40 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[28]; -/** Offset 0x0D54 - PCIE RP Slot Power Limit Value +/** Offset 0x0D5C - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[24]; -/** Offset 0x0D84 - PCIE RP Enable Port8xh Decode +/** Offset 0x0D8C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x0D85 - PCIE Port8xh Decode Port Index +/** Offset 0x0D8D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (1 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x0D86 - Reserved +/** Offset 0x0D8E - Reserved **/ UINT8 Reserved24[114]; -/** Offset 0x0DF8 - SPIn Device Mode +/** Offset 0x0E00 - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:LpssSpiDisabled, 1:LpssSpiPci, 2:LpssSpiHidden **/ UINT8 SerialIoLpssSpiMode[7]; -/** Offset 0x0DFF - Reserved +/** Offset 0x0E07 - Reserved **/ UINT8 Reserved25[85]; -/** Offset 0x0E54 - SPIn Default Chip Select Mode HW/SW +/** Offset 0x0E5C - SPIn Default Chip Select Mode HW/SW Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, SPI1, ... Available options: 0:HW, 1:SW **/ UINT8 SerialIoLpssSpiCsMode[7]; -/** Offset 0x0E5B - SPIn Default Chip Select State Low/High +/** Offset 0x0E63 - SPIn Default Chip Select State Low/High Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High **/ UINT8 SerialIoLpssSpiCsState[7]; -/** Offset 0x0E62 - UARTn Device Mode +/** Offset 0x0E6A - UARTn Device Mode Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartMode[7]; -/** Offset 0x0E69 - Reserved +/** Offset 0x0E71 - Reserved **/ UINT8 Reserved26[3]; -/** Offset 0x0E6C - Default BaudRate for each Serial IO UART +/** Offset 0x0E74 - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 **/ UINT32 SerialIoUartBaudRate[7]; -/** Offset 0x0E88 - Default ParityType for each Serial IO UART +/** Offset 0x0E90 - Default ParityType for each Serial IO UART Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartParity[7]; -/** Offset 0x0E8F - Default DataBits for each Serial IO UART +/** Offset 0x0E97 - Default DataBits for each Serial IO UART Set default word length. 0: Default, 5,6,7,8 **/ UINT8 SerialIoUartDataBits[7]; -/** Offset 0x0E96 - Default StopBits for each Serial IO UART +/** Offset 0x0E9E - Default StopBits for each Serial IO UART Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartStopBits[7]; -/** Offset 0x0E9D - Power Gating mode for each Serial IO UART that works in COM mode +/** Offset 0x0EA5 - Power Gating mode for each Serial IO UART that works in COM mode Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto **/ UINT8 SerialIoUartPowerGating[7]; -/** Offset 0x0EA4 - Enable Dma for each Serial IO UART that supports it +/** Offset 0x0EAC - Enable Dma for each Serial IO UART that supports it Set DMA/PIO mode. 0: Disabled, 1: Enabled **/ UINT8 SerialIoUartDmaEnable[7]; -/** Offset 0x0EAB - Enables UART hardware flow control, CTS and RTS lines +/** Offset 0x0EB3 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. **/ UINT8 SerialIoUartAutoFlow[7]; -/** Offset 0x0EB2 - Reserved +/** Offset 0x0EBA - Reserved **/ UINT8 Reserved27[2]; -/** Offset 0x0EB4 - SerialIoUartRtsPinMuxPolicy +/** Offset 0x0EBC - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values. **/ UINT32 SerialIoUartRtsPinMuxPolicy[7]; -/** Offset 0x0ED0 - SerialIoUartRxPinMuxPolicy +/** Offset 0x0ED8 - SerialIoUartRxPinMuxPolicy Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for possible values. **/ UINT32 SerialIoUartRxPinMuxPolicy[7]; -/** Offset 0x0EEC - SerialIoUartTxPinMuxPolicy +/** Offset 0x0EF4 - SerialIoUartTxPinMuxPolicy Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for possible values. **/ UINT32 SerialIoUartTxPinMuxPolicy[7]; -/** Offset 0x0F08 - Serial IO UART DBG2 table +/** Offset 0x0F10 - Serial IO UART DBG2 table Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable. **/ UINT8 SerialIoUartDbg2[7]; -/** Offset 0x0F0F - Reserved +/** Offset 0x0F17 - Reserved **/ UINT8 Reserved28[7]; -/** Offset 0x0F16 - I2Cn Device Mode +/** Offset 0x0F1E - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[8]; -/** Offset 0x0F1E - Reserved +/** Offset 0x0F26 - Reserved **/ UINT8 Reserved29[2]; -/** Offset 0x0F20 - Serial IO I2C SDA Pin Muxing +/** Offset 0x0F28 - Serial IO I2C SDA Pin Muxing Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values. **/ UINT32 PchSerialIoI2cSdaPinMux[8]; -/** Offset 0x0F40 - Serial IO I2C SCL Pin Muxing +/** Offset 0x0F48 - Serial IO I2C SCL Pin Muxing Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values. **/ UINT32 PchSerialIoI2cSclPinMux[8]; -/** Offset 0x0F60 - PCH SerialIo I2C Pads Termination +/** Offset 0x0F68 - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. **/ UINT8 PchSerialIoI2cPadsTermination[8]; -/** Offset 0x0F68 - I3C Device Mode +/** Offset 0x0F70 - I3C Device Mode Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci, 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling) **/ UINT8 SerialIoI3cMode[3]; -/** Offset 0x0F6B - Reserved +/** Offset 0x0F73 - Reserved **/ UINT8 Reserved30[48]; -/** Offset 0x0F9B - Enable VMD controller +/** Offset 0x0FA3 - Enable VMD controller Enable/disable to VMD controller.0: Disable; 1: Enable(Default) $EN_DIS **/ UINT8 VmdEnable; -/** Offset 0x0F9C - Enable VMD Global Mapping +/** Offset 0x0FA4 - Enable VMD Global Mapping Enable/disable to VMD controller.0: Disable(Default); 1: Enable $EN_DIS **/ UINT8 VmdGlobalMapping; -/** Offset 0x0F9D - Map port under VMD +/** Offset 0x0FA5 - Map port under VMD Map/UnMap port under VMD $EN_DIS **/ UINT8 VmdPort[31]; -/** Offset 0x0FBC - Reserved +/** Offset 0x0FC4 - Reserved **/ UINT8 Reserved31[31]; -/** Offset 0x0FDB - VMD Port Device +/** Offset 0x0FE3 - VMD Port Device VMD Root port device number. **/ UINT8 VmdPortDev[31]; -/** Offset 0x0FFA - VMD Port Func +/** Offset 0x1002 - VMD Port Func VMD Root port function number. **/ UINT8 VmdPortFunc[31]; -/** Offset 0x1019 - Reserved +/** Offset 0x1021 - Reserved **/ UINT8 Reserved32[7]; -/** Offset 0x1020 - VMD Variable +/** Offset 0x1028 - VMD Variable VMD Variable Pointer. **/ UINT64 VmdVariablePtr; -/** Offset 0x1028 - Reserved +/** Offset 0x1030 - Reserved **/ UINT8 Reserved33[4]; -/** Offset 0x102C - Temporary MemBar1 address for VMD +/** Offset 0x1034 - Temporary MemBar1 address for VMD VMD Variable Pointer. **/ UINT32 VmdMemBar1Base; -/** Offset 0x1030 - Temporary MemBar2 address for VMD +/** Offset 0x1038 - Temporary MemBar2 address for VMD VMD Variable Pointer. **/ UINT32 VmdMemBar2Base; -/** Offset 0x1034 - Enable D3 Hot in TCSS +/** Offset 0x103C - Enable D3 Hot in TCSS This policy will enable/disable D3 hot support in IOM $EN_DIS **/ UINT8 D3HotEnable; -/** Offset 0x1035 - Reserved +/** Offset 0x103D - Reserved **/ UINT8 Reserved34[3]; -/** Offset 0x1038 - TypeC port GPIO setting +/** Offset 0x1040 - TypeC port GPIO setting GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl = LunarLake) **/ UINT32 IomTypeCPortPadCfg[12]; -/** Offset 0x1068 - CPU USB3 Port Over Current Pin +/** Offset 0x1070 - CPU USB3 Port Over Current Pin Describe the specific over current pin number of USBC Port N. **/ UINT8 CpuUsb3OverCurrentPin[10]; -/** Offset 0x1072 - Enable D3 Cold in TCSS +/** Offset 0x107A - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM $EN_DIS **/ UINT8 D3ColdEnable; -/** Offset 0x1073 - TC State in TCSS +/** Offset 0x107B - TC State in TCSS This TC C-State Limit in IOM **/ UINT8 TcCstateLimit; -/** Offset 0x1074 - Reserved +/** Offset 0x107C - Reserved **/ UINT8 Reserved35[2]; -/** Offset 0x1076 - Enable/Disable PMC-PD Solution +/** Offset 0x107E - Enable/Disable PMC-PD Solution This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution $EN_DIS **/ UINT8 PmcPdEnable; -/** Offset 0x1077 - Reserved +/** Offset 0x107F - Reserved **/ UINT8 Reserved36; -/** Offset 0x1078 - TCSS Aux Orientation Override Enable +/** Offset 0x1080 - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x107A - TCSS HSL Orientation Override Enable +/** Offset 0x1082 - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x107C - TCSS USB Port Enable +/** Offset 0x1084 - TCSS USB Port Enable Bits 0, 1, ... max Type C port control enables **/ UINT8 UsbTcPortEn; -/** Offset 0x107D - VCCST request for IOM +/** Offset 0x1085 - VCCST request for IOM This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 $EN_DIS **/ UINT8 VccSt; -/** Offset 0x107E - Enable/Disable PTM +/** Offset 0x1086 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports $EN_DIS **/ UINT8 PtmEnabled[4]; -/** Offset 0x1082 - PCIE RP Ltr Enable +/** Offset 0x108A - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 SaPcieItbtRpLtrEnable[4]; -/** Offset 0x1086 - PCIE RP Snoop Latency Override Mode +/** Offset 0x108E - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; -/** Offset 0x108A - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x1092 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x108E - PCIE RP Snoop Latency Override Value +/** Offset 0x1096 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; -/** Offset 0x1096 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x109E - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; -/** Offset 0x109A - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x10A2 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x109E - PCIE RP Non Snoop Latency Override Value +/** Offset 0x10A6 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; -/** Offset 0x10A6 - Force LTR Override +/** Offset 0x10AE - Force LTR Override Force LTR Override. **/ UINT8 SaPcieItbtRpForceLtrOverride[4]; -/** Offset 0x10AA - PCIE RP Ltr Config Lock +/** Offset 0x10B2 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 SaPcieItbtRpLtrConfigLock[4]; -/** Offset 0x10AE - Reserved +/** Offset 0x10B6 - Reserved **/ UINT8 Reserved37[4]; -/** Offset 0x10B2 - Touch Host Controller Assignment +/** Offset 0x10BA - Touch Host Controller Assignment Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcAssignment[2]; -/** Offset 0x10B4 - Touch Host Controller Interrupt Pin Mux +/** Offset 0x10BC - Touch Host Controller Interrupt Pin Mux Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. **/ UINT8 ThcInterruptPinMuxing[8]; -/** Offset 0x10BC - Touch Host Controller Mode +/** Offset 0x10C4 - Touch Host Controller Mode Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid **/ UINT8 ThcMode[2]; -/** Offset 0x10BE - Touch Host Controller Wake On Touch +/** Offset 0x10C6 - Touch Host Controller Wake On Touch Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI **/ UINT8 ThcWakeOnTouch[2]; -/** Offset 0x10C0 - Reserved +/** Offset 0x10C8 - Reserved **/ UINT8 Reserved38[337]; -/** Offset 0x1211 - PCHHOT# pin +/** Offset 0x1219 - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ UINT8 PchHotEnable; -/** Offset 0x1212 - Thermal Throttling Custimized T0Level Value +/** Offset 0x121A - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x1214 - Thermal Throttling Custimized T1Level Value +/** Offset 0x121C - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x1216 - Thermal Throttling Custimized T2Level Value +/** Offset 0x121E - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x1218 - Enable The Thermal Throttle +/** Offset 0x1220 - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x1219 - PMSync State 13 +/** Offset 0x1221 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x121A - Thermal Throttle Lock +/** Offset 0x1222 - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x121B - Thermal Throttling Suggested Setting +/** Offset 0x1223 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x121C - Thermal Device Temperature +/** Offset 0x1224 - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x121E +/** Offset 0x1226 **/ UINT8 PchTsnEnable[4]; -/** Offset 0x1222 - Reserved +/** Offset 0x122A - Reserved **/ UINT8 Reserved39[34]; -/** Offset 0x1244 - Enable USB2 ports +/** Offset 0x124C - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x1254 - Enable USB3 ports +/** Offset 0x125C - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x125E - Enable xDCI controller +/** Offset 0x1266 - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x125F - USB PDO Programming +/** Offset 0x1267 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable $EN_DIS **/ UINT8 UsbPdoProgramming; -/** Offset 0x1260 - Reserved +/** Offset 0x1268 - Reserved **/ UINT8 Reserved40; -/** Offset 0x1261 - PCH USB OverCurrent mapping enable +/** Offset 0x1269 - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS **/ UINT8 PchUsbOverCurrentEnable; -/** Offset 0x1262 - USB2 Port Over Current Pin +/** Offset 0x126A - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x1272 - USB3 Port Over Current Pin +/** Offset 0x127A - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x127C - Enable xHCI LTR override +/** Offset 0x1284 - Enable xHCI LTR override Enables override of recommended LTR values for xHCI $EN_DIS **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x127D - Reserved +/** Offset 0x1285 - Reserved **/ UINT8 Reserved41[3]; -/** Offset 0x1280 - xHCI High Idle Time LTR override +/** Offset 0x1288 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting **/ UINT32 PchUsbLtrHighIdleTimeOverride; -/** Offset 0x1284 - xHCI Medium Idle Time LTR override +/** Offset 0x128C - xHCI Medium Idle Time LTR override Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting **/ UINT32 PchUsbLtrMediumIdleTimeOverride; -/** Offset 0x1288 - xHCI Low Idle Time LTR override +/** Offset 0x1290 - xHCI Low Idle Time LTR override Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting **/ UINT32 PchUsbLtrLowIdleTimeOverride; -/** Offset 0x128C - USB2 Port Reset Message Enable +/** Offset 0x1294 - USB2 Port Reset Message Enable 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must be enable for USB2 Port those are paired with CPU XHCI Port **/ UINT8 PortResetMessageEnable[16]; -/** Offset 0x129C - PCH USB OverCurrent mapping lock enable +/** Offset 0x12A4 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x129D - USB Per Port HS Preemphasis Bias +/** Offset 0x12A5 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2PhyPetxiset[16]; -/** Offset 0x12AD - USB Per Port HS Transmitter Bias +/** Offset 0x12B5 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2PhyTxiset[16]; -/** Offset 0x12BD - USB Per Port HS Transmitter Emphasis +/** Offset 0x12C5 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2PhyPredeemp[16]; -/** Offset 0x12CD - USB Per Port Half Bit Pre-emphasis +/** Offset 0x12D5 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2PhyPehalfbit[16]; -/** Offset 0x12DD - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x12E5 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x12E7 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x12EF - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x12F1 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x12F9 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x12FB - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x1303 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x1305 +/** Offset 0x130D **/ UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; -/** Offset 0x130F +/** Offset 0x1317 **/ UINT8 PchUsb3HsioFilterSelNEnable[10]; -/** Offset 0x1319 +/** Offset 0x1321 **/ UINT8 PchUsb3HsioFilterSelPEnable[10]; -/** Offset 0x1323 +/** Offset 0x132B **/ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; -/** Offset 0x132D +/** Offset 0x1335 **/ UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; -/** Offset 0x1337 +/** Offset 0x133F **/ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; -/** Offset 0x1341 +/** Offset 0x1349 **/ UINT8 PchUsb3HsioFilterSelN[10]; -/** Offset 0x134B +/** Offset 0x1353 **/ UINT8 PchUsb3HsioFilterSelP[10]; -/** Offset 0x1355 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 +/** Offset 0x135D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTranEnable[10]; -/** Offset 0x135F - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 +/** Offset 0x1367 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTran[10]; -/** Offset 0x1369 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 +/** Offset 0x1371 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTranEnable[10]; -/** Offset 0x1373 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 +/** Offset 0x137B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTran[10]; -/** Offset 0x137D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 +/** Offset 0x1385 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTranEnable[10]; -/** Offset 0x1387 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 +/** Offset 0x138F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTran[10]; -/** Offset 0x1391 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 +/** Offset 0x1399 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTranEnable[10]; -/** Offset 0x139B - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 +/** Offset 0x13A3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTran[10]; -/** Offset 0x13A5 - Reserved +/** Offset 0x13AD - Reserved **/ UINT8 Reserved42[4]; -/** Offset 0x13A9 - Enable/Disable NPU Device +/** Offset 0x13B1 - Enable/Disable NPU Device Enable(Default): Enable NPU Device, Disable: Disable NPU Device $EN_DIS **/ UINT8 NpuEnable; -/** Offset 0x13AA - Enable LAN +/** Offset 0x13B2 - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x13AB - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x13B3 - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x13AC - Reserved +/** Offset 0x13B4 - Reserved **/ UINT8 Reserved43; -/** Offset 0x13AD - Skip Ssid Programming. +/** Offset 0x13B5 - Skip Ssid Programming. When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly. $EN_DIS **/ UINT8 SiSkipSsidProgramming; -/** Offset 0x13AE - Change Default SVID +/** Offset 0x13B6 - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSvid; -/** Offset 0x13B0 - Change Default SSID +/** Offset 0x13B8 - Change Default SSID Change the default SSID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSsid; -/** Offset 0x13B2 - Reserved +/** Offset 0x13BA - Reserved **/ UINT8 Reserved44[6]; -/** Offset 0x13B8 - SVID SDID table Poniter. +/** Offset 0x13C0 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE. **/ UINT64 SiSsidTablePtr; -/** Offset 0x13C0 - Number of ssid table. +/** Offset 0x13C8 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x13C2 - Reserved +/** Offset 0x13CA - Reserved **/ UINT8 Reserved45[10]; -/** Offset 0x13CC - LogoPixelHeight Address +/** Offset 0x13D4 - LogoPixelHeight Address Address of LogoPixelHeight **/ UINT32 LogoPixelHeight; -/** Offset 0x13D0 - LogoPixelWidth Address +/** Offset 0x13D8 - LogoPixelWidth Address Address of LogoPixelWidth **/ UINT32 LogoPixelWidth; -/** Offset 0x13D4 - Reserved +/** Offset 0x13DC - Reserved **/ UINT8 Reserved46[4]; -/** Offset 0x13D8 - Blt Buffer Address +/** Offset 0x13E0 - Blt Buffer Address Address of Blt buffer **/ UINT64 BltBufferAddress; -/** Offset 0x13E0 - Graphics Configuration Ptr +/** Offset 0x13E8 - Graphics Configuration Ptr Points to VBT **/ UINT64 GraphicsConfigPtr; -/** Offset 0x13E8 - Enable/Disable SkipFspGop +/** Offset 0x13F0 - Enable/Disable SkipFspGop Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver $EN_DIS **/ UINT8 SkipFspGop; -/** Offset 0x13E9 - Reserved +/** Offset 0x13F1 - Reserved **/ UINT8 Reserved47; -/** Offset 0x13EA - Enable/Disable IGFX RenderStandby +/** Offset 0x13F2 - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x13EB - Reserved +/** Offset 0x13F3 - Reserved **/ UINT8 Reserved48[3]; -/** Offset 0x13EE - Enable/Disable PavpEnable +/** Offset 0x13F6 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS **/ UINT8 PavpEnable; -/** Offset 0x13EF - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x13F7 - Enable/Disable PeiGraphicsPeimInit Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x13F0 - Reserved +/** Offset 0x13F8 - Reserved **/ UINT8 Reserved49[4]; -/** Offset 0x13F4 - Intel Graphics VBT (Video BIOS Table) Size +/** Offset 0x13FC - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image **/ UINT32 VbtSize; -/** Offset 0x13F8 - Platform LID Status for LFP Displays. +/** Offset 0x1400 - Platform LID Status for LFP Displays. LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. 0: LidClosed, 1: LidOpen **/ UINT8 LidStatus; -/** Offset 0x13F9 - Reserved +/** Offset 0x1401 - Reserved **/ UINT8 Reserved50[11]; -/** Offset 0x1404 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. +/** Offset 0x140C - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. **/ UINT32 DevIntConfigPtr; -/** Offset 0x1408 - Number of DevIntConfig Entry +/** Offset 0x1410 - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. **/ UINT8 NumOfDevIntConfig; -/** Offset 0x1409 - Select GPIO IRQ Route +/** Offset 0x1411 - Select GPIO IRQ Route GPIO IRQ Select. The valid value is 14 or 15. **/ UINT8 GpioIrqRoute; -/** Offset 0x140A - Select SciIrqSelect +/** Offset 0x1412 - Select SciIrqSelect SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. **/ UINT8 SciIrqSelect; -/** Offset 0x140B - Select TcoIrqSelect +/** Offset 0x1413 - Select TcoIrqSelect TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. **/ UINT8 TcoIrqSelect; -/** Offset 0x140C - Enable/Disable Tco IRQ +/** Offset 0x1414 - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS **/ UINT8 TcoIrqEnable; -/** Offset 0x140D - Reserved +/** Offset 0x1415 - Reserved **/ UINT8 Reserved51[5]; -/** Offset 0x1412 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states +/** Offset 0x141A - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtV1p05RailEnabledStates; -/** Offset 0x1413 - Mask to enable the platform configuration of external V1p05 VR rail +/** Offset 0x141B - Mask to enable the platform configuration of external V1p05 VR rail External V1P05 Rail Supported Configuration **/ UINT8 PchFivrExtV1p05RailSupportedVoltageStates; -/** Offset 0x1414 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states +/** Offset 0x141C - External V1P05 Voltage Value that will be used in S0i2/S0i3 states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) **/ UINT16 PchFivrExtV1p05RailVoltage; -/** Offset 0x1416 - External V1P05 Icc Max Value +/** Offset 0x141E - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtV1p05RailIccMax; -/** Offset 0x1417 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states +/** Offset 0x141F - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtVnnRailEnabledStates; -/** Offset 0x1418 - Mask to enable the platform configuration of external Vnn VR rail +/** Offset 0x1420 - Mask to enable the platform configuration of external Vnn VR rail External Vnn Rail Supported Configuration **/ UINT8 PchFivrExtVnnRailSupportedVoltageStates; -/** Offset 0x1419 - Reserved +/** Offset 0x1421 - Reserved **/ UINT8 Reserved52; -/** Offset 0x141A - External Vnn Voltage Value that will be used in S0ix/Sx states +/** Offset 0x1422 - External Vnn Voltage Value that will be used in S0ix/Sx states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 **/ UINT16 PchFivrExtVnnRailVoltage; -/** Offset 0x141C - External Vnn Icc Max Value that will be used in S0ix/Sx states +/** Offset 0x1424 - External Vnn Icc Max Value that will be used in S0ix/Sx states Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtVnnRailIccMax; -/** Offset 0x141D - Mask to enable the usage of external Vnn VR rail in Sx states +/** Offset 0x1425 - Mask to enable the usage of external Vnn VR rail in Sx states Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtVnnRailSxEnabledStates; -/** Offset 0x141E - External Vnn Voltage Value that will be used in Sx states +/** Offset 0x1426 - External Vnn Voltage Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) **/ UINT16 PchFivrExtVnnRailSxVoltage; -/** Offset 0x1420 - External Vnn Icc Max Value that will be used in Sx states +/** Offset 0x1428 - External Vnn Icc Max Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtVnnRailSxIccMax; -/** Offset 0x1421 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage +/** Offset 0x1429 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage. **/ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; -/** Offset 0x1422 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage +/** Offset 0x142A - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage. **/ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; -/** Offset 0x1423 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage +/** Offset 0x142B - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage. **/ UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; -/** Offset 0x1424 - Transition time in microseconds from Off (0V) to High Current Mode Voltage +/** Offset 0x142C - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. **/ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; -/** Offset 0x1426 - FIVR Dynamic Power Management +/** Offset 0x142E - FIVR Dynamic Power Management Enable/Disable FIVR Dynamic Power Management. $EN_DIS **/ UINT8 PchFivrDynPm; -/** Offset 0x1427 - Reserved +/** Offset 0x142F - Reserved **/ UINT8 Reserved53; -/** Offset 0x1428 - External V1P05 Icc Max Value +/** Offset 0x1430 - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtV1p05RailIccMaximum; -/** Offset 0x142A - External Vnn Icc Max Value that will be used in S0ix/Sx states +/** Offset 0x1432 - External Vnn Icc Max Value that will be used in S0ix/Sx states Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtVnnRailIccMaximum; -/** Offset 0x142C - External Vnn Icc Max Value that will be used in Sx states +/** Offset 0x1434 - External Vnn Icc Max Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtVnnRailSxIccMaximum; -/** Offset 0x142E - External V1P05 Control Ramp Timer value +/** Offset 0x1436 - External V1P05 Control Ramp Timer value Hold off time to be used when changing the v1p05_ctrl for external bypass value in us **/ UINT8 PchFivrExtV1p05RailCtrlRampTmr; -/** Offset 0x142F - External VNN Control Ramp Timer value +/** Offset 0x1437 - External VNN Control Ramp Timer value Hold off time to be used when changing the vnn_ctrl for external bypass value in us **/ UINT8 PchFivrExtVnnRailCtrlRampTmr; -/** Offset 0x1430 - PCH Compatibility Revision ID +/** Offset 0x1438 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x1431 - PCH Legacy IO Low Latency Enable +/** Offset 0x1439 - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x1432 - Reserved +/** Offset 0x143A - Reserved **/ UINT8 Reserved54; -/** Offset 0x1433 - PCH Unlock SideBand access +/** Offset 0x143B - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x1434 - Enable 8254 Static Clock Gating +/** Offset 0x143C - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -2216,7 +2216,7 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x1435 - Enable 8254 Static Clock Gating On S3 +/** Offset 0x143D - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -2224,172 +2224,172 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x1436 - Enable PCH Io Apic Entry 24-119 +/** Offset 0x143E - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x1437 - PCH Io Apic ID +/** Offset 0x143F - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x1438 - CNVi Configuration +/** Offset 0x1440 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x1439 - CNVi Wi-Fi Core +/** Offset 0x1441 - CNVi Wi-Fi Core Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviWifiCore; -/** Offset 0x143A - CNVi BT Core +/** Offset 0x1442 - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x143B - CNVi BT Interface +/** Offset 0x1443 - CNVi BT Interface This option configures BT device interface to either USB/PCI 1:USB, 2:PCI **/ UINT8 CnviBtInterface; -/** Offset 0x143C - CNVi BT Audio Offload +/** Offset 0x1444 - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x143D - Reserved +/** Offset 0x1445 - Reserved **/ UINT8 Reserved55[3]; -/** Offset 0x1440 - CNVi RF_RESET pin muxing +/** Offset 0x1448 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. **/ UINT32 CnviRfResetPinMux; -/** Offset 0x1444 - CNVi CLKREQ pin muxing +/** Offset 0x144C - CNVi CLKREQ pin muxing Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in GpioPins*.h. **/ UINT32 CnviClkreqPinMux; -/** Offset 0x1448 - Reserved +/** Offset 0x1450 - Reserved **/ UINT8 Reserved56; -/** Offset 0x1449 - Enable Device 4 +/** Offset 0x1451 - Enable Device 4 Enable/disable Device 4 $EN_DIS **/ UINT8 Device4Enable; -/** Offset 0x144A - Skip PAM regsiter lock +/** Offset 0x1452 - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x144B - Reserved +/** Offset 0x1453 - Reserved **/ UINT8 Reserved57; -/** Offset 0x144C - PCH HDA Verb Table Entry Number +/** Offset 0x1454 - PCH HDA Verb Table Entry Number Number of Entries in Verb Table. **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x144D - Reserved +/** Offset 0x1455 - Reserved **/ UINT8 Reserved58[3]; -/** Offset 0x1450 - PCH HDA Verb Table Pointer +/** Offset 0x1458 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. **/ UINT64 PchHdaVerbTablePtr; -/** Offset 0x1458 - PCH HDA Codec Sx Wake Capability +/** Offset 0x1460 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx **/ UINT8 PchHdaCodecSxWakeCapability; -/** Offset 0x1459 - Enable Pme +/** Offset 0x1461 - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x145A - HD Audio Link Frequency +/** Offset 0x1462 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x145B - Reserved +/** Offset 0x1463 - Reserved **/ UINT8 Reserved59[2]; -/** Offset 0x145D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode +/** Offset 0x1465 - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire0; -/** Offset 0x145E - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode +/** Offset 0x1466 - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire1; -/** Offset 0x145F - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode +/** Offset 0x1467 - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire2; -/** Offset 0x1460 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode +/** Offset 0x1468 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire3; -/** Offset 0x1461 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode +/** Offset 0x1469 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire4; -/** Offset 0x1462 - HD Audio Microphone Privacy applied for Dmic in HW Mode +/** Offset 0x146A - HD Audio Microphone Privacy applied for Dmic in HW Mode HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeDmic; -/** Offset 0x1463 - Reserved +/** Offset 0x146B - Reserved **/ UINT8 Reserved60[13]; -/** Offset 0x1470 - Pointer to ChipsetInit Binary +/** Offset 0x1478 - Pointer to ChipsetInit Binary ChipsetInit Binary Pointer. **/ UINT64 ChipsetInitBinPtr; -/** Offset 0x1478 - Length of ChipsetInit Binary +/** Offset 0x1480 - Length of ChipsetInit Binary ChipsetInit Binary Length. **/ UINT32 ChipsetInitBinLen; -/** Offset 0x147C - Reserved +/** Offset 0x1484 - Reserved **/ UINT8 Reserved61[36]; } FSP_S_CONFIG; @@ -2410,11 +2410,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x14A0 +/** Offset 0x14A8 **/ UINT8 FspsUpdRsvd36[6]; -/** Offset 0x14A6 +/** Offset 0x14AE **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/86642?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9657eb2b6db1b05adc721b3ef2cf8661642d91e8 Gerrit-Change-Number: 86642 Gerrit-PatchSet: 1 Gerrit-Owner: srinivas.kulkarni(a)intel.com

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coreboot-gerrit February 2025