coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD
by Felix Held (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Angel Pons, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/86643?usp=email ) Change subject: soc/amd/common/uart: Configure UART PAD ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: the root cause seems to be an fsp bug, so i'd say that that one should be fixed instead -- To view, visit https://review.coreboot.org/c/coreboot/+/86643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc Gerrit-Change-Number: 86643 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 11:39:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya/vell: Enable RTD3 for SSD
by Pranava Y N (Code Review) 28 Feb '25

28 Feb '25

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86646?usp=email ) Change subject: mb/google/brya/vell: Enable RTD3 for SSD ...................................................................... mb/google/brya/vell: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on vell and verify that the device suspends to S0ix. Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/86646/1 diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 697d0ef..6f9b325 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -191,6 +191,13 @@ .clk_src = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D3)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end end device ref tbt_pcie_rp3 on end device ref cnvi_wifi on -- To view, visit https://review.coreboot.org/c/coreboot/+/86646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3 Gerrit-Change-Number: 86646 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya/lisbon: Enable RTD3 for SSD
by Pranava Y N (Code Review) 28 Feb '25

28 Feb '25

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86645?usp=email ) Change subject: mb/google/brya/lisbon: Enable RTD3 for SSD ...................................................................... mb/google/brya/lisbon: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on lisbon and verify that the device suspends to S0ix. Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/lisbon/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/86645/1 diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 4c3ffff..6c3eaf9 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -149,6 +149,13 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_NVME end #NVMe device ref tbt_pcie_rp0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/86645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0 Gerrit-Change-Number: 86645 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya/bujia: Enable RTD3 for SSD
by Subrata Banik (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N. Subrata Banik has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/86644?usp=email ) Change subject: mb/google/brya/bujia: Enable RTD3 for SSD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459 Gerrit-Change-Number: 86644 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 11:19:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya/bujia: Enable RTD3 for SSD
by Pranava Y N (Code Review) 28 Feb '25

28 Feb '25

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86644?usp=email ) Change subject: mb/google/brya/bujia: Enable RTD3 for SSD ...................................................................... mb/google/brya/bujia: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on Bujia and verify that the device suspends to S0ix. Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/bujia/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/86644/1 diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index 6db60ac..370c052 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -119,6 +119,13 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end #NVME device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/86644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459 Gerrit-Change-Number: 86644 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: MAINTAINERS: Drop myself from Xeon-SP
by Shuo Liu (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Patrick Rudolph. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86641?usp=email ) Change subject: MAINTAINERS: Drop myself from Xeon-SP ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Sorry to see this request but I sincerely hope to continue to work with Patrick on Xeon-SP. -- To view, visit https://review.coreboot.org/c/coreboot/+/86641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c6492f4e37b21bdc2b8d413fb30beaf16403345 Gerrit-Change-Number: 86641 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 11:08:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Set psys_pmax_watts to 65W
by Paul Menzel (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Matt DeVillier, Sean Rhodes. Paul Menzel has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86629?usp=email ) Change subject: mb/starlabs/starbook/mtl: Set psys_pmax_watts to 65W ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86629/comment/4f5288e8_abbf312d?us… : PS1, Line 9: Set psys_pmax_watts to 65W, which is 1.0C of the battery to : avoid drawing more power than is available. What was the value before? -- To view, visit https://review.coreboot.org/c/coreboot/+/86629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0460f87deb23925db30829135a4d3b9bfc92bf6 Gerrit-Change-Number: 86629 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 10:36:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Don't generate a TME on S3 exit
by Subrata Banik (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Sean Rhodes, Tarun. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86625?usp=email ) Change subject: soc/intel/meteorlake: Don't generate a TME on S3 exit ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie19cb7f11ad633405a9fc3c1faf1c3cc53113f51 Gerrit-Change-Number: 86625 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 10:29:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: MAINTAINERS: Drop myself from Xeon-SP
by Paul Menzel (Code Review) 28 Feb '25

28 Feb '25

Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86641?usp=email ) Change subject: MAINTAINERS: Drop myself from Xeon-SP ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86641/comment/28a571cc_3a178dae?us… : PS1, Line 7: myself Patrick Rudolph It’s than more useful, when using `git log --oneline`. -- To view, visit https://review.coreboot.org/c/coreboot/+/86641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c6492f4e37b21bdc2b8d413fb30beaf16403345 Gerrit-Change-Number: 86641 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 10:27:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Don't generate a TME on S3 exit
by Sean Rhodes (Code Review) 28 Feb '25

28 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86625?usp=email ) Change subject: soc/intel/meteorlake: Don't generate a TME on S3 exit ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie19cb7f11ad633405a9fc3c1faf1c3cc53113f51 Gerrit-Change-Number: 86625 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 28 Feb 2025 10:23:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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coreboot-gerrit February 2025