Change in coreboot[master]: pci: Add support for assigning resources to SR-IOV VF BARs
stephend@silicom-usa.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34620 ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages like: pci 0000:03:00.0: BAR 7: no space for [mem size 0x00100000 64bit] pci 0000:03:00.0: BAR 7: failed to assign [mem size 0x00100000 64bit] Tested on Camelback Mountain, and Harcuvar. Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pci_def.h M src/include/device/pciexp.h 4 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7786043..c96fc8d 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -439,6 +439,11 @@ { pci_read_bases(dev, 6); pci_get_rom_resource(dev, PCI_ROM_ADDRESS); + +#if CONFIG(PCIEXP_PLUGIN_SUPPORT) + /* Check for SR-IOV BARs if we have PCIe support */ + pciexp_dev_read_resources(dev); +#endif } void pci_bus_read_resources(struct device *dev) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c209816..8d660b1 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -442,6 +442,82 @@ pciexp_enable_aspm(root, root_cap, dev, cap); } +/* + * Check if this is an SR-IOV capable device and add resources for all VF bars + * + * @param dev Pointer to the dev structure. + */ +void pciexp_dev_read_resources(struct device *dev) +{ + unsigned long sriovpos; + u16 numvfs, i; + + sriovpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!sriovpos) { + return; + } + + sriovpos = pciexp_find_extended_cap(dev, PCI_EXT_CAP_ID_SRIOV); + if (!sriovpos) { + return; + } + + numvfs = pci_read_config16(dev, sriovpos + PCI_SRIOV_TOT_VFS); + printk(BIOS_DEBUG, "%s: supports %d SR-IOV VFs\n", dev_path(dev), numvfs); + + /* The spec allows this to be 0 for some reason. Nothing to do. */ + if (numvfs == 0) { + return; + } + + for (int off = 0; off < 6; off++) { + unsigned long res_ix = sriovpos + PCI_SRIOV_VFBAR0 + off * 4; + struct resource *resource; + + resource = pci_get_resource(dev, res_ix); + + /* VF BARs aren't necessarily contiguous, skip the unused ones */ + if (resource->size == 0) { + continue; + } + + printk(BIOS_DEBUG, "%s: found %dbit SR-IOV BAR, size 0x%llx @ index %lx\n", + dev_path(dev), (resource->flags & IORESOURCE_PCI64) ? 64 : 32, + resource->size, resource->index); + + if (resource->flags & IORESOURCE_PCI64) { + off++; + } + + /* + * SR-IOV BARs break the resource allocator assumption for PCI + * dev resources that size = gran = alignment. + * + * alignment = gran = pci_get_resource() result, but... + * size is pci_get_resource()->size * numvfs, and there's no + * power of two guarantee on size either since numvfs is just + * an integer. + * + * Rather than add code to handle this as a special case in the + * resource allocator, just round up the size. In practice + * MaxVfs tends to be 2^n or 2^n - 1, so the holes produced + * should only be the size of a single VF BAR + */ + for (i = 1; i < numvfs; i <<= 1) { + resource->size <<= 1; + resource->align += 1; + resource->gran += 1; + } + + if (i != numvfs) { + printk(BIOS_DEBUG, "%s: VFs != 2^n, wasting MMIO space...\n", + dev_path(dev)); + } + } + + compact_resources(dev); +} + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn) { diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..39a6137 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -453,6 +453,7 @@ #define PCI_EXT_CAP_ID_VC 2 #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +#define PCI_EXT_CAP_ID_SRIOV 0x0010 /* Extended Capability lists*/ #define PCIE_EXT_CAP_OFFSET 0x100 @@ -518,6 +519,34 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ +/* SR-IOV */ +#define PCI_SRIOV_CAPS 0x04 /* SR-IOV capabilities */ +#define PCI_SRIOV_VF_MIG (1 << 0) /* VF Migration capable */ +#define PCI_SRIOV_ARI_CAP (1 << 1) /* ARI Capable Hierarchy Preserved */ +#define PCI_SRIOV_MIG_INT(x) (((x) >> 21) & 0x7ff) +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define PCI_SRIOV_VF_EN (1 << 0) +#define PCI_SRIOV_MIG_EN (1 << 1) +#define PCI_SRIOV_MIG_INT_EN (1 << 2) +#define PCI_SRIOV_MSE (1 << 3) +#define PCI_SRIOV_ARI_CAP_EN (1 << 4) +#define PCI_SRIOV_STATUS 0x0A /* SR-IOV Status */ +#define PCI_SRIOV_INIT_VFS 0x0C +#define PCI_SRIOV_TOT_VFS 0x0E +#define PCI_SRIOV_NUM_VFS 0x10 +#define PCI_SRIOV_FN_DEP_LINK 0x12 +#define PCI_SRIOV_VF_OFF 0x14 +#define PCI_SRIOV_VF_STRIDE 0x16 +#define PCI_SRIOV_VF_DEVID 0x1A +#define PCI_SRIOV_SUP_PAGE_SIZE 0x1C +#define PCI_SRIOV_PAGE_SIZE 0x20 +#define PCI_SRIOV_VFBAR0 0x24 +#define PCI_SRIOV_VFBAR1 0x28 +#define PCI_SRIOV_VFBAR2 0x2C +#define PCI_SRIOV_VFBAR3 0x30 +#define PCI_SRIOV_VFBAR4 0x34 +#define PCI_SRIOV_VFBAR5 0x38 +#define PCI_SRIOV_MIG_ARRAY 0x3C /* * The PCI interface treats multi-function devices as independent diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 3a9825d..94a80bf 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -19,6 +19,8 @@ /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003 +void pciexp_dev_read_resources(struct device *dev); + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 1 Gerrit-Owner: stephend@silicom-usa.com Gerrit-MessageType: newchange
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34620 ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/c/coreboot/+/34620/1/src/device/pciexp_device.c File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/34620/1/src/device/pciexp_device.c@... PS1, Line 456: if (!sriovpos) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/34620/1/src/device/pciexp_device.c@... PS1, Line 461: if (!sriovpos) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/34620/1/src/device/pciexp_device.c@... PS1, Line 469: if (numvfs == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/34620/1/src/device/pciexp_device.c@... PS1, Line 480: if (resource->size == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/34620/1/src/device/pciexp_device.c@... PS1, Line 488: if (resource->flags & IORESOURCE_PCI64) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 1 Gerrit-Owner: stephend@silicom-usa.com Gerrit-CC: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Mon, 29 Jul 2019 21:12:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34620 to look at the new patch set (#2). Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages like: pci 0000:03:00.0: BAR 7: no space for [mem size 0x00100000 64bit] pci 0000:03:00.0: BAR 7: failed to assign [mem size 0x00100000 64bit] Tested on Camelback Mountain, and Harcuvar. Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pci_def.h M src/include/device/pciexp.h 4 files changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 2 Gerrit-Owner: stephend@silicom-usa.com Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: newpatchset
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34620 ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 2: Code-Review+1 Looks good to me at least from the code perspective -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 2 Gerrit-Owner: stephend@silicom-usa.com Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-Comment-Date: Tue, 30 Jul 2019 10:49:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Attention is currently required from: Stephen Douthit. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34620 ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/34620/comment/bb55a8d8_ee0e9165 PS2, Line 10: Linux Please mention the/a version. -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 2 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 11:12:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Attention is currently required from: Stephen Douthit. Harrie Paijmans has posted comments on this change by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi, We see this same problem on our Raptorlake P platform. I have rebased this patch on the latest main branch and updated it to accommodate changes made after this patchset, it solves the issues described above. I want to ask if I can update this patchset with my updated version? -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 2 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 10:27:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No
Attention is currently required from: Harrie Paijmans, Stephen Douthit. Harrie Paijmans has uploaded a new patch set (#3) to the change originally created by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages, these messages may differ depending on the kernel version used. Debian GNU/Linux 12 (kernel 6.1.0-28-amd64): pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref] pci 0000:06:00.0: BAR 7: failed to assign [mem size 0x00200000 64bit pref] Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic): pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't assign; no space pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: failed to assign TEST=Raptorlake-P Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pciexp.h 3 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 3 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Attention: Harrie Paijmans <hpaijmans@eltan.com>
Attention is currently required from: Frans Hendriks, Paul Menzel, Stephen Douthit. Harrie Paijmans has posted comments on this change by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 3: (2 comments) Patchset: PS2:
Hi, […] Done
Commit Message: https://review.coreboot.org/c/coreboot/+/34620/comment/fff8f57e_970cd590?usp... : PS2, Line 10: Linux
Please mention the/a version. Done
-- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 3 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Frans Hendriks <fhendriks@eltan.com> Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Attention: Paul Menzel <paulepanter@mailbox.org> Gerrit-Comment-Date: Mon, 26 May 2025 08:49:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter@mailbox.org> Comment-In-Reply-To: Harrie Paijmans <hpaijmans@eltan.com>
Attention is currently required from: Frans Hendriks, Paul Menzel, Stephen Douthit. Harrie Paijmans has uploaded a new patch set (#4) to the change originally created by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages, these messages may differ depending on the kernel version used. Debian GNU/Linux 12 (kernel 6.1.0-28-amd64): pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref] pci 0000:06:00.0: BAR 7: failed to assign [mem size 0x00200000 64bit pref] Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic): pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't assign; no space pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: failed to assign TEST=Raptorlake-P Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pciexp.h 3 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 4 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Frans Hendriks <fhendriks@eltan.com> Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Attention: Paul Menzel <paulepanter@mailbox.org>
Attention is currently required from: Frans Hendriks, Stephen Douthit. Harrie Paijmans has posted comments on this change by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 4: (2 comments) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/34620/comment/3b380edc_95a707f0?usp... : PS3, Line 832: if ((i != numvfs) && ((i-1) != numvfs)) {
`code indent should use tabs where possible`
Please fix. https://review.coreboot.org/c/coreboot/+/34620/comment/ff9ca1ac_0de24fa3?usp... : PS3, Line 832: if ((i != numvfs) && ((i-1) != numvfs)) {
`please, no space before tabs`
Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 4 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Frans Hendriks <fhendriks@eltan.com> Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Comment-Date: Mon, 26 May 2025 08:54:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No
Attention is currently required from: Frans Hendriks, Stephen Douthit. Harrie Paijmans has uploaded a new patch set (#5) to the change originally created by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages, these messages may differ depending on the kernel version used. Debian GNU/Linux 12 (kernel 6.1.0-28-amd64): pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref] pci 0000:06:00.0: BAR 7: failed to assign [mem size 0x00200000 64bit pref] Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic): pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't assign; no space pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: failed to assign TEST=Raptorlake-P Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pciexp.h 3 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 5 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Frans Hendriks <fhendriks@eltan.com> Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com>
Attention is currently required from: Frans Hendriks, Stephen Douthit. Harrie Paijmans has posted comments on this change by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/34620/comment/691b09f7_b9ec028d?usp... : PS4, Line 14: pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref]
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Please fix. https://review.coreboot.org/c/coreboot/+/34620/comment/ae941008_77e517ad?usp... : PS4, Line 17: Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic):
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Please fix. https://review.coreboot.org/c/coreboot/+/34620/comment/496c939f_f747a615?usp... : PS4, Line 18: pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't assign; no space
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Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 5 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Frans Hendriks <fhendriks@eltan.com> Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Comment-Date: Mon, 26 May 2025 09:07:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No
Attention is currently required from: Harrie Paijmans, Stephen Douthit. Frans Hendriks has posted comments on this change by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 5 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Attention: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Attention: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Comment-Date: Mon, 26 May 2025 09:57:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes
Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages, these messages may differ depending on the kernel version used. Debian GNU/Linux 12 (kernel 6.1.0-28-amd64): pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref] pci 0000:06:00.0: BAR 7: failed to assign [mem size 0x00200000 64bit pref] Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic): pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't assign; no space pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: failed to assign TEST=Raptorlake-P Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34620 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pciexp.h 3 files changed, 81 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 29fde7c..baa7a48 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -543,6 +543,11 @@ { pci_read_bases(dev, 6); pci_get_rom_resource(dev, PCI_ROM_ADDRESS); + +#if CONFIG(PCIEXP_PLUGIN_SUPPORT) + /* Check for SR-IOV BARs if we have PCIe support */ + pciexp_dev_read_resources(dev); +#endif } void pci_bus_read_resources(struct device *dev) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 8686e38..a5f162e 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -764,6 +764,80 @@ } } +/* + * Check if this is an SR-IOV capable device and add resources for all VF bars + * + * @param dev Pointer to the dev structure. + */ +void pciexp_dev_read_resources(struct device *dev) +{ + unsigned long sriovpos; + u16 numvfs, i; + + sriovpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!sriovpos) + return; + + sriovpos = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_SRIOV_ID, PCIE_EXT_CAP_OFFSET); + if (!sriovpos) + return; + + numvfs = pci_read_config16(dev, sriovpos + PCIE_EXT_CAP_SRIOV_TOTAL_VFS); + printk(BIOS_DEBUG, "%s: supports %d SR-IOV VFs\n", dev_path(dev), numvfs); + + /* The spec allows this to be 0 for some reason. Nothing to do. */ + if (numvfs == 0) + return; + + for (int off = 0; off < 6; off++) { + unsigned long res_ix = sriovpos + PCIE_EXT_CAP_SRIOV_VF_BAR0 + off * 4; + struct resource *resource; + + resource = pci_get_resource(dev, res_ix); + + /* VF BARs aren't necessarily contiguous, skip the unused ones */ + if (resource->size == 0) + continue; + + printk(BIOS_DEBUG, "%s: found %dbit SR-IOV BAR, size 0x%llx @ index %lx\n", + dev_path(dev), (resource->flags & IORESOURCE_PCI64) ? 64 : 32, + resource->size, resource->index); + + if (resource->flags & IORESOURCE_PCI64) + off++; + + /* + * SR-IOV BARs break the resource allocator assumption for PCI + * dev resources that size = gran = alignment. + * + * alignment = gran = pci_get_resource() result, but... + * size is pci_get_resource()->size * numvfs, and there's no + * power of two guarantee on size either since numvfs is just + * an integer. + * + * Rather than add code to handle this as a special case in the + * resource allocator, just round up the size. In practice + * MaxVfs tends to be 2^n or 2^n - 1, so the holes produced + * should only be the size of a single VF BAR + */ + for (i = 1; i < numvfs; i <<= 1) { + resource->size <<= 1; + resource->align += 1; + resource->gran += 1; + } + + if (resource->size >= 16 * MiB) + resource->flags |= IORESOURCE_ABOVE_4G; + + if ((i != numvfs) && ((i-1) != numvfs)) { + printk(BIOS_DEBUG, "%s: VFs != 2^n or VFs != (2^n)-1, wasting MMIO space...\n", + dev_path(dev)); + } + } + + compact_resources(dev); +} + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn) { diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 2618c02..2afa813 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -22,6 +22,8 @@ /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003 +void pciexp_dev_read_resources(struct device *dev); + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 6 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei
9elements QA has posted comments on this change by Stephen Douthit. ( https://review.coreboot.org/c/coreboot/+/34620?usp=email ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/241749 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/241747 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/241746 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/241745 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/241744 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/241743 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/241742 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/241741 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/241740 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/241739 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/241738 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/241737 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/34620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 6 Gerrit-Owner: Stephen Douthit <stephend@silicom-usa.com> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Harrie Paijmans <hpaijmans@eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot@gmail.com> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> Gerrit-CC: Jeff Li <lijinfeng01@inspur.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: TangYiwei Gerrit-Comment-Date: Wed, 28 May 2025 17:19:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No
participants (8)
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9elements QA (Code Review) -
build bot (Jenkins) (Code Review)
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Frans Hendriks (Code Review)
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Harrie Paijmans (Code Review)
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Matt DeVillier (Code Review)
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Name of user not set (Code Review)
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Paul Menzel (Code Review)
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Philipp Deppenwiese (Code Review)