coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: cbfstool: Fix the help text
by Shuo Liu (Code Review) 27 Feb '25

27 Feb '25

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86639?usp=email ) Change subject: cbfstool: Fix the help text ...................................................................... cbfstool: Fix the help text The help text for cbfstool add/add-stage's mmap window option needs to be updated to [--mmap flash-base:mmio-base:size] from [--mmio flash-base:mmio-base:size] Change-Id: I5f8224c8789e642fc68f6ae2242e8e7a7228c8de Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M util/cbfstool/cbfstool.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/86639/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index c8b7e42..a693337 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1977,7 +1977,7 @@ " [-c compression] [-b base-address | -a alignment] \\\n" " [-p padding size] [-y|--xip if TYPE is FSP] \\\n" " [-j topswap-size] (Intel CPUs only) [--ibb] \\\n" - " [--mmio flash-base:mmio-base:size] " + " [--mmap flash-base:mmio-base:size] " "Add a component\n" " " " -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n" @@ -1990,7 +1990,7 @@ " [-S comma-separated-section(s)-to-ignore] \\\n" " [-a alignment] [-Q|--pow2page] \\\n" " [-y|--xip] [--ibb] \\\n" - " [--mmio flash-base:mmio-base:size] " + " [--mmap flash-base:mmio-base:size] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/86639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f8224c8789e642fc68f6ae2242e8e7a7228c8de Gerrit-Change-Number: 86639 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: Kconfig: Add OVERRIDE_CBFS_MMAP_WINDOW
by Shuo Liu (Code Review) 27 Feb '25

27 Feb '25

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86638?usp=email ) Change subject: Kconfig: Add OVERRIDE_CBFS_MMAP_WINDOW ...................................................................... Kconfig: Add OVERRIDE_CBFS_MMAP_WINDOW cbfstool by default uses an mmap window of $CONFIG_ROM_SIZE-16M: 4G-16M:16M (flash-base:mmio-base:size), which only allows coreboot owned flash region size smaller than 16MB. Select OVERRIDE_CBFS_MMAP_WINDOW if the default behavior needs to be changed, where cbfstool add commands will be used with extra options to specify a customized mmap window setting, by --mmap $(CONFIG_MMAP_FLASH_BASE):$(CONFIG_MMAP_MMIO_BASE): $(CONFIG_MMAP_SIZE) The usages could be various, e.g. it helps if a mainboard target uses a coreboot owned flash region larger than 16MB. Change-Id: I5f049ef62893c254cef274521324a3b90c6ff70d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M Makefile.mk M src/Kconfig M src/arch/x86/Makefile.mk 3 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86638/1 diff --git a/Makefile.mk b/Makefile.mk index 0542aef..d9ed443 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -983,6 +983,10 @@ cbfs-autogen-attributes=-g endif +ifeq ($(CONFIG_OVERRIDE_CBFS_MMAP_WINDOW),y) + cbfs-mmap-win=--mmap $(CONFIG_MMAP_FLASH_BASE):$(CONFIG_MMAP_MMIO_BASE):$(CONFIG_MMAP_SIZE) +endif + # cbfs-add-cmd-for-region # $(call cbfs-add-cmd-for-region,file in extract_nth format,region name) # @@ -999,6 +1003,7 @@ extract_nth,3,$(1))),-t $(call extract_nth,3,$(1))) \ $(if $(call extract_nth,4,$(1)),-c $(call extract_nth,4,$(1))) \ $(cbfs-autogen-attributes) \ + $(cbfs-mmap-win) \ -r $(2) \ $(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \ $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \ diff --git a/src/Kconfig b/src/Kconfig index 3914a38..3385fcf 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1515,6 +1515,25 @@ (bootblock, romstage, verstage, ramstage, postcar) in src/arch/${ARCH}/Makefile.mk. +config OVERRIDE_CBFS_MMAP_WINDOW + bool + default n + help + if set as y, all cbfs add commands will use overridden mmio window by + adding --mmap $CONFIG_CBFS_FLASH_BASE:$CONFIG_CBFS_MMIO_BASE:$CONFIG_CBFS_MMAP_SIZE + +config MMAP_FLASH_BASE + depends on OVERRIDE_CBFS_MMAP_WINDOW + hex + +config MMAP_MMIO_BASE + depends on OVERRIDE_CBFS_MMAP_WINDOW + hex + +config MMAP_SIZE + depends on OVERRIDE_CBFS_MMAP_WINDOW + hex + ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in diff --git a/src/arch/x86/Makefile.mk b/src/arch/x86/Makefile.mk index a455a09..4cd7309 100644 --- a/src/arch/x86/Makefile.mk +++ b/src/arch/x86/Makefile.mk @@ -85,7 +85,7 @@ add_bootblock = \ $(CBFSTOOL) $(1) add -f $(2) -n bootblock -t bootblock $(TXTIBB) \ -b -$(call file-size,$(2)) \ - $(cbfs-autogen-attributes) $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS) + $(cbfs-autogen-attributes) $(cbfs-mmap-win) $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS) endif ifneq ($(CONFIG_CBFS_VERIFICATION),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/86638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f049ef62893c254cef274521324a3b90c6ff70d Gerrit-Change-Number: 86638 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: mb/google/geralt: Tuning CSOT_PNA957QT1_1 panel VSP/VSN voltage for Ciri
by Yang Wu (Code Review) 27 Feb '25

27 Feb '25

Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86637?usp=email ) Change subject: mb/google/geralt: Tuning CSOT_PNA957QT1_1 panel VSP/VSN voltage for Ciri ...................................................................... mb/google/geralt: Tuning CSOT_PNA957QT1_1 panel VSP/VSN voltage for Ciri The system default VSP/VSN voltage for Ciri is +-5.7V. According to the CSOT panel vendor's requirement, VSP/VSN for the CSOT_PNA957QT1_1 panel needs to be adjusted to +-6V. So modify the relevant register values accordingly. BUG=b:399728328 TEST=Boot to firmware screen BRANCH=Geralt Change-Id: I1b69303317f5ef47818f4a6a0c851bf650285e51 Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/geralt/panel_ciri.c 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/86637/1 diff --git a/src/mainboard/google/geralt/panel_ciri.c b/src/mainboard/google/geralt/panel_ciri.c index 4c21e90..8147ebe 100644 --- a/src/mainboard/google/geralt/panel_ciri.c +++ b/src/mainboard/google/geralt/panel_ciri.c @@ -8,11 +8,11 @@ #define PMIC_TPS65132_I2C I2C3 -static void power_on_mipi_himax_83102j(void) +static void power_on_mipi_himax_83102j(uint8_t val) { const struct tps65132s_reg_setting reg_settings[] = { - { PMIC_TPS65132_VPOS, 0x11, 0x1f }, - { PMIC_TPS65132_VNEG, 0x11, 0x1f }, + { PMIC_TPS65132_VPOS, addr, 0x1f }, + { PMIC_TPS65132_VNEG, addr, 0x1f }, { PMIC_TPS65132_DLYX, 0x55, 0xff }, { PMIC_TPS65132_ASSDD, 0x5b, 0xff }, }; @@ -27,10 +27,20 @@ power_on_mipi_panel(&cfg); } +static void power_on_mipi_himax_83102j_default(void) +{ + power_on_mipi_himax_83102j(0x11); +} + +static void power_on_mipi_himax_83102j_csot(void) +{ + power_on_mipi_himax_83102j(0x14); +} + static struct panel_description ciri_panels[] = { [17] = { .name = "BOE_NV110WUM_L60", - .power_on = power_on_mipi_himax_83102j, + .power_on = power_on_mipi_himax_83102j_default, .configure_backlight = configure_mipi_pwm_backlight, .orientation = LB_FB_ORIENTATION_LEFT_UP, .disp_path = DISP_PATH_MIPI, @@ -39,7 +49,7 @@ [34] = { .name = "IVO_T109NW41", - .power_on = power_on_mipi_himax_83102j, + .power_on = power_on_mipi_himax_83102j_default, .configure_backlight = configure_mipi_pwm_backlight, .orientation = LB_FB_ORIENTATION_LEFT_UP, .disp_path = DISP_PATH_MIPI, @@ -48,7 +58,7 @@ [51] = { .name = "CSOT_PNA957QT1_1", - .power_on = power_on_mipi_himax_83102j, + .power_on = power_on_mipi_himax_83102j_csot, .configure_backlight = configure_mipi_pwm_backlight, .orientation = LB_FB_ORIENTATION_LEFT_UP, .disp_path = DISP_PATH_MIPI, -- To view, visit https://review.coreboot.org/c/coreboot/+/86637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b69303317f5ef47818f4a6a0c851bf650285e51 Gerrit-Change-Number: 86637 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/asus/p8z77-m: Move SIO ACPI device config to bootblock
by Keith Hui (Code Review) 27 Feb '25

27 Feb '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86636?usp=email ) Change subject: mb/asus/p8z77-m: Move SIO ACPI device config to bootblock ...................................................................... mb/asus/p8z77-m: Move SIO ACPI device config to bootblock ACPI S3 suspend has been failing on this mainboard for about 5 months as of this writing. This move fixes the regression. The removal of these three settings from devicetree also realized a small image size reduction. TEST=Now again able to enter S3 suspend and return to where I was. Change-Id: I35189b7977c83b3a2666dded8267b9021f0ea3f3 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 2 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/86636/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index 76eba43..7e4647c 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -12,6 +12,7 @@ #define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1) #define GPIO0_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_WDT1_GPIO01_V) +#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI) void bootblock_mainboard_early_init(void) { @@ -26,6 +27,11 @@ pnp_write_config(GPIO0_DEV, 0xe0, 0x7f); pnp_write_config(GPIO0_DEV, 0xe1, 0x00); + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); /* Enable 3VSBSW#, needed for S3 suspend */ + pnp_write_config(ACPI_DEV, 0xe7, 0x11); /* HWM reset by LRESET#, 0.5s S3 delay */ + pnp_write_config(ACPI_DEV, 0xf2, 0x5d); /* Enable RSTOUT[0-2]# and PME */ + nuvoton_pnp_exit_conf_state(GPIO0_DEV); /* diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index e84125b..058ce76 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -56,11 +56,7 @@ device pnp 2e.108 on # GPIO 0 drq 0xe1 = 0x80 # GP07 high turns DRAM_LED off end - device pnp 2e.a on # ACPI - drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend - drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility - drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME - end + device pnp 2e.a on end # ACPI device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 # HWM address io 0x62 = 0 # SB-TSI address (not used) -- To view, visit https://review.coreboot.org/c/coreboot/+/86636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I35189b7977c83b3a2666dded8267b9021f0ea3f3 Gerrit-Change-Number: 86636 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: mb/asus/p8x7x-series: Move Super I/O base port to Kconfig
by Keith Hui (Code Review) 27 Feb '25

27 Feb '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86635?usp=email ) Change subject: mb/asus/p8x7x-series: Move Super I/O base port to Kconfig ...................................................................... mb/asus/p8x7x-series: Move Super I/O base port to Kconfig By doing this the base port is now #defined as CONFIG_SUPERIO_PNP_BASE, available to both C and ASL code, the latter will soon start to make use of this as well. This will be gradually expanded to all boards using superio/nuvoton/{nct5572d,nct6776,nct6779d,nct6791d}. Change early_init.c of all variants to use this new #define. Change-Id: I6e2851db68f4867be8fa4ef0d8bd8d1b9b8bf92a Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c 7 files changed, 19 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/86635/1 diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index 133bd94..209aaa5 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -86,4 +86,8 @@ config CMOS_LAYOUT_FILE default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout" +config SUPERIO_PNP_BASE + hex + default 0x2e + endif diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c index ad240c1..f192e22 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c @@ -5,9 +5,9 @@ #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) +#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_ACPI) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c index 6d68c17..a7f7e9f 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c @@ -5,9 +5,9 @@ #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) -#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) +#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index 9ae7e1d1..76eba43 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -10,8 +10,8 @@ #include <option.h> -#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) -#define GPIO0_DEV PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1) +#define GPIO0_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_WDT1_GPIO01_V) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index 40be913..73a4c80 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -11,7 +11,7 @@ #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/pei_data.h> -#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP2) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c index bf0ba67..f693fbc 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c @@ -5,9 +5,9 @@ #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) -#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) +#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c index 6d68c17..a7f7e9f 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c @@ -5,9 +5,9 @@ #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) -#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) +#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI) void bootblock_mainboard_early_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e2851db68f4867be8fa4ef0d8bd8d1b9b8bf92a Gerrit-Change-Number: 86635 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: mb/google/nissa/var/guren: Add initial override devicetree
by Subrata Banik (Code Review) 27 Feb '25

27 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86602?usp=email ) Change subject: mb/google/nissa/var/guren: Add initial override devicetree ...................................................................... mb/google/nissa/var/guren: Add initial override devicetree The schematic is the same as Glassway project and only difference for CPU. Therefore, we clone the coreboot settings of glassway to guren then remove some configurations to meet those keypart/design for guren. BUG=b:397149037 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: Ia43a78c340426069571172319be1675b3d94eba4 Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86602 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/variants/guren/Makefile.mk A src/mainboard/google/brya/variants/guren/data.vbt A src/mainboard/google/brya/variants/guren/fw_config.c A src/mainboard/google/brya/variants/guren/gpio.c M src/mainboard/google/brya/variants/guren/include/variant/gpio.h M src/mainboard/google/brya/variants/guren/overridetree.cb A src/mainboard/google/brya/variants/guren/ramstage.c A src/mainboard/google/brya/variants/guren/variant.c 9 files changed, 847 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 5ab7d5d..0cc6624 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -297,6 +297,15 @@ config BOARD_GOOGLE_GUREN select BOARD_GOOGLE_BASEBOARD_NISSA + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select HAVE_WWAN_POWER_SEQUENCE + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_TWINLAKE config BOARD_GOOGLE_HADES select BOARD_GOOGLE_BASEBOARD_HADES diff --git a/src/mainboard/google/brya/variants/guren/Makefile.mk b/src/mainboard/google/brya/variants/guren/Makefile.mk new file mode 100644 index 0000000..b469805 --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/Makefile.mk @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += gpio.c + +ramstage-y += variant.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/guren/data.vbt b/src/mainboard/google/brya/variants/guren/data.vbt new file mode 100644 index 0000000..ba47065 --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/data.vbt Binary files differ diff --git a/src/mainboard/google/brya/variants/guren/fw_config.c b/src/mainboard/google/brya/variants/guren/fw_config.c new file mode 100644 index 0000000..52dff5c --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/fw_config.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config hdmi_disable_pads[] = { + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), +}; + +static const struct pad_config lte_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Disable HDMI GPIO pins.\n"); + gpio_padbased_override(padbased_table, hdmi_disable_pads, + ARRAY_SIZE(hdmi_disable_pads)); + } + + /* Set to Disable LTE-related GPIO pins when field DB_USB is not DB_1C_LTE and DB_HDMI_LTE. */ + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) + && !fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Disable LTE GPIO pins.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads, + ARRAY_SIZE(lte_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/guren/gpio.c b/src/mainboard/google/brya/variants/guren/gpio.c new file mode 100644 index 0000000..0c46265 --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/gpio.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage for guren */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D6 : WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : PCIE SLOT1 WAKE N */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + /* E4 : SDD_STRAP1 */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E5 : SDD_STRAP2 */ + PAD_CFG_GPI(GPP_E5, NONE, DEEP), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* F13 : GSXSLOAD ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + /* R4 : I2S2_SCLK ==> DMIC_UCAM_CLK_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : I2S2_SFRM ==> DMIC_UCAM_DATA_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : DMIC_CLK_A_1A ==> NC */ + PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock for guren */ +static const struct pad_config early_gpio_table[] = { + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* C6 : SML1CLK ==> TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_C6, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/guren/include/variant/gpio.h b/src/mainboard/google/brya/variants/guren/include/variant/gpio.h index c4fe342..c96b01f 100644 --- a/src/mainboard/google/brya/variants/guren/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/guren/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb index 4f2c04a..95c4b58 100644 --- a/src/mainboard/google/brya/variants/guren/overridetree.cb +++ b/src/mainboard/google/brya/variants/guren/overridetree.cb @@ -1,6 +1,634 @@ +fw_config + field THERMAL_SOLUTION 0 + option THERMAL_SOLUTION_PASSIVE 0 + option THERMAL_SOLUTION_ACTIVE 1 + end + field DB_USB 5 8 + option DB_NONE 0 + option DB_1C 1 + option DB_1A 2 + option DB_1C_1A 3 + option DB_1C_LTE 4 + option DB_HDMI_LTE 5 + end + field SD_CARD 9 + option SD_ABSENT 0 + option SD_GL9750S 1 + end + field WIFI_SAR_ID 11 13 + option WIFI_SAR_ID_INTEL_CONVERTIBLE 0 + option WIFI_SAR_ID_INTEL_CLAMSHELL 1 + end + field TOUCHSCREEN_SOURCE 32 34 + option TOUCHSCREEN_UNPROVISIONED 0 + option TOUCHSCREEN_ELAN0001 1 + end +end + chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on - end + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10048" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 40, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 40, + } + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1, + .time_window_max = 1, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_PASSIVE + end + end + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + TEMP_PCT(70, 50), + TEMP_PCT(65, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(50, 90), + TEMP_PCT(48, 70), + TEMP_PCT(46, 60), + TEMP_PCT(43, 40), + TEMP_PCT(40, 30), + } + } + }" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 12000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 1, + .time_window_max = 1, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 1 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_ACTIVE + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "4" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "stop_delay_ms" = "5" + register "stop_off_delay_ms" = "25" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "25" + register "has_power_resource" = "true" + device i2c 10 on + probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN0001 + end + end + + end #I2C1 + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x46" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x46" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x1b" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x20" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0xc0" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0x70" + register "reg_adv_ctrl18" = "0x20" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_msk" = "0x60" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "512" + register "ph23_resolution" = "512" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "3" + register "ph23_proxraw_strength" = "3" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""gnd"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on + probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE + end + end + end #I2C2 + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""10EC5650"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5650"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-mode"" + register "property_list[0].integer" = "2" + device i2c 1a on end + end + end #I2C3 + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""PIXART Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end #I2C5 + device ref pcie_rp4 on + # Enable wlan PCIe 4 using clk 2 + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end + device ref pcie_rp7 on + # Enable SD Card PCIe 7 using clk 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)" + register "srcclk_pin" = "3" + device generic 0 on end + end + probe SD_CARD SD_GL9750S + end + device ref emmc on + probe STORAGE STORAGE_EMMC + end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + probe STORAGE STORAGE_UFS + end + device ref ufs on + probe STORAGE STORAGE_UFS + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on + probe DB_USB DB_1C + probe DB_USB DB_1A + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on + probe DB_USB DB_1C + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on + probe DB_USB DB_1C + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on + probe DB_USB DB_1A + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on + probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on + probe DB_USB DB_1A + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on + probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE + end + end + end + end + end + end end diff --git a/src/mainboard/google/brya/variants/guren/ramstage.c b/src/mainboard/google/brya/variants/guren/ramstage.c new file mode 100644 index 0000000..6d63eaa --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->VccInAuxImonIccImax = 100; // 25 * 4 for ADL-N + printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax); +} diff --git a/src/mainboard/google/brya/variants/guren/variant.c b/src/mainboard/google/brya/variants/guren/variant.c new file mode 100644 index 0000000..ff71b64 --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/variant.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); +} + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Enable DDI PORT 2 for HPD and DDC.\n"); + config->ddi_ports_config[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia43a78c340426069571172319be1675b3d94eba4 Gerrit-Change-Number: 86602 Gerrit-PatchSet: 2 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com>

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[L] Change in coreboot[main]: mb/google/nissa/var/guren: Add initial override devicetree
by Brian Hsu (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Brian Hsu has posted comments on this change by Brian Hsu. ( https://review.coreboot.org/c/coreboot/+/86602?usp=email ) Change subject: mb/google/nissa/var/guren: Add initial override devicetree ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Dear all, if no concern, please kindly help to submit the CL. Thanks a lot. -- To view, visit https://review.coreboot.org/c/coreboot/+/86602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia43a78c340426069571172319be1675b3d94eba4 Gerrit-Change-Number: 86602 Gerrit-PatchSet: 1 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Feb 2025 04:36:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Set the default to Software Connection Manager
by Subrata Banik (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Sean Rhodes, Tarun. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86626?usp=email ) Change subject: soc/intel/meteorlake: Set the default to Software Connection Manager ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4868acdb59fca9253005222b4080356dd61b1855 Gerrit-Change-Number: 86626 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:56:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Enable Type-C Ports and TBT
by Subrata Banik (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Weimin Wu. Subrata Banik has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/86633?usp=email ) Change subject: mb/google/fatcat/var/felino: Enable Type-C Ports and TBT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbed4d16911665e820382a483607e6dae44b7f8c Gerrit-Change-Number: 86633 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:56:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Enable Type-C Ports and TBT
by Tongtong Pan (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Weimin Wu. Tongtong Pan has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/86633?usp=email ) Change subject: mb/google/fatcat/var/felino: Enable Type-C Ports and TBT ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbed4d16911665e820382a483607e6dae44b7f8c Gerrit-Change-Number: 86633 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:55:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit February 2025