coreboot-gerrit February 2025

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[S] Change in coreboot[main]: soc/amd/cezanne: Add ACPI opregion to root complex
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/77682?usp=email ) Change subject: soc/amd/cezanne: Add ACPI opregion to root complex ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/77682/comment/e4672abe_06c7d42b?us… : PS6, Line 63: Add ACPI device, opregion to host bridge needed for Windows ACP driver. : * : * This provides a mailbox interface for the ACP drivers to notify the PSP : * that the DSP firmware has been loaded, so that the PSP can validate : * the firmware and set the qualifier bit to enable running it. is this comment still valid? or should we make it more generic? -- To view, visit https://review.coreboot.org/c/coreboot/+/77682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443 Gerrit-Change-Number: 77682 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 23:09:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: src/acpigen: support 0-initialized buffer in acpigen_write_byte_buffer
by Felix Held (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86631?usp=email ) Change subject: src/acpigen: support 0-initialized buffer in acpigen_write_byte_buffer ...................................................................... src/acpigen: support 0-initialized buffer in acpigen_write_byte_buffer Previously, the 'acpigen_write_byte_buffer' function required both the byte buffer length and the initialization data byte array 'arr'. The ACPI spec however allows buffer declarations with only the length, but without an initialization data byte array. In this case the AML interpreter will create a buffer of the given length with all bytes initialized to 0x00. In order to not need another function, allow the 'arr' parameter for the pointer to the initialization data byte array to be NULL and in that case don't write the optional buffer initialization byte array. Change-Id: Ie756489e02f994c38d38907a97fb215d30f4a636 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/acpi/acpigen.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/86631/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index e577d8f..081fa2b 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1775,6 +1775,8 @@ acpigen_emit_byte(dst_op); } +/* The initializer byte array 'arr' is optional. When 'arr' is NULL, the AML interpreter will + create a 0-initialized byte buffer */ void acpigen_write_byte_buffer(uint8_t *arr, size_t size) { size_t i; @@ -1783,8 +1785,10 @@ acpigen_write_len_f(); acpigen_write_integer(size); - for (i = 0; i < size; i++) - acpigen_emit_byte(arr[i]); + if (arr != NULL) { + for (i = 0; i < size; i++) + acpigen_emit_byte(arr[i]); + } acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie756489e02f994c38d38907a97fb215d30f4a636 Gerrit-Change-Number: 86631 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

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[S] Change in coreboot[main]: src/acpigen: implement acpigen_write_create[_buffer]_bit_field
by Felix Held (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86630?usp=email ) Change subject: src/acpigen: implement acpigen_write_create[_buffer]_bit_field ...................................................................... src/acpigen: implement acpigen_write_create[_buffer]_bit_field Implement functions to write the AML bytes corresponding to CreateBitField for both OP buffers and named buffers. Change-Id: Ia5c06c2e8564b64de386871b2faf79c433e5a1da Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/86630/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index eaf95e0..e577d8f 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -2461,6 +2461,11 @@ acpigen_emit_namestring(name); } +void acpigen_write_create_bit_field(uint8_t op, size_t bit_offset, const char *name) +{ + _create_field(CREATE_BIT_OP, op, bit_offset, name); +} + void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name) { _create_field(CREATE_BYTE_OP, op, byte_offset, name); @@ -2490,6 +2495,11 @@ acpigen_emit_namestring(field); } +void acpigen_write_create_buffer_bit_field(const char *src_buf, size_t bit_offset, const char *field) +{ + _create_buffer_field(CREATE_BIT_OP, src_buf, bit_offset, field); +} + void acpigen_write_create_buffer_byte_field(const char *src_buf, size_t byte_offset, const char *field) { _create_buffer_field(CREATE_BYTE_OP, src_buf, byte_offset, field); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 56b4f78..a83be04 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -535,10 +535,12 @@ void acpigen_write_ADR(uint64_t adr); struct soundwire_address; void acpigen_write_ADR_soundwire_device(const struct soundwire_address *address); +void acpigen_write_create_bit_field(uint8_t op, size_t bit_offset, const char *name); void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name); void acpigen_write_create_word_field(uint8_t op, size_t byte_offset, const char *name); void acpigen_write_create_dword_field(uint8_t op, size_t byte_offset, const char *name); void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char *name); +void acpigen_write_create_buffer_bit_field(const char *src_buf, size_t bit_offset, const char *field); void acpigen_write_create_buffer_byte_field(const char *src_buf, size_t byte_offset, const char *name); void acpigen_write_create_buffer_word_field(const char *src_buf, size_t byte_offset, const char *name); void acpigen_write_create_buffer_dword_field(const char *src_buf, size_t byte_offset, const char *name); -- To view, visit https://review.coreboot.org/c/coreboot/+/86630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5c06c2e8564b64de386871b2faf79c433e5a1da Gerrit-Change-Number: 86630 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/cezanne: Add ACPI opregion to root complex
by Felix Held (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier. Felix Held has uploaded a new patch set (#6) to the change originally created by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/77682?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/cezanne: Add ACPI opregion to root complex ...................................................................... soc/amd/cezanne: Add ACPI opregion to root complex Add an ACPI OPREGION to access an SMN access index/data register pair in the root complex. Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/root_complex.c 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/77682/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/77682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443 Gerrit-Change-Number: 77682 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[M] Change in coreboot[main]: soc/amd/cezanne/acpi: Add ACP MSG0 method
by Felix Held (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier, Patrick Rudolph. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86466?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins) Change subject: soc/amd/cezanne/acpi: Add ACP MSG0 method ...................................................................... soc/amd/cezanne/acpi: Add ACP MSG0 method Add the MSG0 method to the ACP's SSDT entry, so that the ACP driver can talk to a two different mailbox interfaces via this ACPI MSG0 method interface. Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/acpi.c 1 file changed, 185 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/86466/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Gerrit-Change-Number: 86466 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Move IOE Bar
by Jérémy Compostella (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86309?usp=email ) Change subject: soc/intel/meteorlake: Move IOE Bar ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/86309/comment/0b9e11ba_75fd60f9?us… : PS1, Line 254: default 0x60000000 How is going to work with devices when 2G DRAM is mapped on [ 0x0, 0x80000000] ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86309?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie29618739d98f0d0c3995a60377083036f23ff18 Gerrit-Change-Number: 86309 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 22:23:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Jérémy Compostella (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Paul Menzel, Zhixing Ma. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84564?usp=email ) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... Patch Set 7: (9 comments) File src/mainboard/intel/ptlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/84564/comment/29347cc2_647f83fb?us… : PS6, Line 2: > forgot how we made UART changes for Windows RVP. […] This Change List (CL) provides the foundational support for our PTLRVP board. I suggest that we consider such an addition in follow-up Change Lists (CLs). https://review.coreboot.org/c/coreboot/+/84564/comment/305b67a3_38248db9?us… : PS6, Line 3: config BOARD_INTEL_PTLRVP_COMMON > Can we add commented flag that we used to use fill_policy instead of fsp_param back? Could you clarify? I do not comprehend your comment. https://review.coreboot.org/c/coreboot/+/84564/comment/eb0e117d_01038377?us… : PS6, Line 5: select BOARD_ROMSIZE_KB_32768 > fatcat has CPU_INTEL_SOCKET_OTHER for SMBios changes. This was added after e2ea7f22c6355d15515c049ca0dc4352173a0c01. This change will be incorporated the next time we sync up, as I do not want to void the validation we have performed on this Changelist (CL). https://review.coreboot.org/c/coreboot/+/84564/comment/b1a5bc1e_617c1f46?us… : PS6, Line 69: if BOARD_INTEL_PTLRVP_COMMON > do we want to remove BOARD_INTEL_PTLRVP_COMMON since we use board_id instead of variants? only keep […] I agree that `BOARD_INTEL_PTLRVP_COMMON` is not necessary for PTLRVP mainboard definitions. I decided to keep it in an attempt to keep the code and architecture as close as possible to the Fatcat board. It should help to smooth the integration of changes coming from Fatcat. File src/mainboard/intel/ptlrvp/chromeos.fmd: PS6: > quit a lot of difference compared to recent fatcat. […] Based on previous experience at the end of last year, I assume some of these changes, in particular the shift to 9 MB instead of 8 MB, were necessary to accommodate the firmware stored in the SI_ALL firmware region. I experimented this morning and it seems that this is not the case. Hence, I have aligned with the FatCat FMD. File src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/ec.h: https://review.coreboot.org/c/coreboot/+/84564/comment/b9184273_a4b6b927?us… : PS6, Line 78: #define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ > do we need these two when ISH enabled like Fatcat does? You are correct, we probably do not. I removed them. File src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/84564/comment/65d2c7e6_bb6bde0d?us… : PS6, Line 13: #define EC_SYNC_IRQ 0 > should we remove these two defines? it is defined in src/mainboard/intel/ptlrvp/variants/ptlrvp/incl […] Done File src/mainboard/intel/ptlrvp/variants/ptlrvp/devicetree.cb: PS6: > why do we need this file? We already have variants/baseboard/ptlrvp/devicetree.cb. Done File src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c: https://review.coreboot.org/c/coreboot/+/84564/comment/e5d19513_88b16b04?us… : PS6, Line 199: /* GPP_E07: Not used */ > in fatcat GPIO, GPP_07 is configured for EC_SOC_INT_ODL unless ISH is enabled. […] I assumed that on ptlrvp we are in the CONFIG_BOARD_GOOGLE_FATCAT and I therefore set it as NC. Am I missing something ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 27 Feb 2025 21:49:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com>

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[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Jérémy Compostella (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Bora Guvendik, Jamie Ryu, Jérémy Compostella, Paul Menzel, Zhixing Ma. Hello Bora Guvendik, Cliff Huang, Jamie Ryu, Paul Menzel, Zhixing Ma, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84564?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Bora Guvendik, Code-Review+1 by Paul Menzel, Code-Review+1 by Zhixing Ma, Verified+1 by build bot (Jenkins) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat This commit introduces the Intel Panther Lake (PTL) Reference Validation Platform (RVP) mainboard definition. It is aligned with the Google Fatcat mainboard in the coreboot codebase, with the commit hash e2ea7f22c6355d15515c049ca0dc4352173a0c01. Intel's proprietary platform, commonly referred to as PTLRVP, and Google's Fatcat mainboard share a considerable degree of similarity in their design and capabilities. Nevertheless, Intel faces unique challenges and requires specific board configurations that Google does not. Consequently, there is a necessity for a specialized mainboard tailored to Intel's individual needs. To maintain consistency with the Fatcat board definition, the Chrome OS Board Information (CBI) firmware configuration aligns with that of Google Fatcat. If necessary, new bits will be appended, starting from the end of the 32-bit firmware configuration field. BUG=b:398880064 TEST=The Intel PTLRVP board successfully boots to the operating System. Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- A src/mainboard/intel/ptlrvp/Kconfig A src/mainboard/intel/ptlrvp/Kconfig.name A src/mainboard/intel/ptlrvp/Makefile.mk A src/mainboard/intel/ptlrvp/board_info.txt A src/mainboard/intel/ptlrvp/bootblock.c A src/mainboard/intel/ptlrvp/chromeos.c A src/mainboard/intel/ptlrvp/chromeos.fmd A src/mainboard/intel/ptlrvp/dsdt.asl A src/mainboard/intel/ptlrvp/ec.c A src/mainboard/intel/ptlrvp/mainboard.c A src/mainboard/intel/ptlrvp/romstage.c A src/mainboard/intel/ptlrvp/smihandler.c A src/mainboard/intel/ptlrvp/spd/Makefile.mk A src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/ec.h A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk A src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/hda_verb.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/ec.h A src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/gpio.h A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt A src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb A src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c 32 files changed, 3,070 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/84564/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/meteorlake: Add support for USB wake up
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86628?usp=email ) Change subject: soc/intel/meteorlake: Add support for USB wake up ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86628/comment/5fbdcfcb_947d3d90?us… : PS1, Line 1: Parent: 58fdcfa8 (soc/intel/meteorlake: Set the default to Software Connection Manager) maybe add that this was carried forward from ADL -- To view, visit https://review.coreboot.org/c/coreboot/+/86628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67da6af619db947ab4830fa2d9904f3e70fbfd21 Gerrit-Change-Number: 86628 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 21:41:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Set the MMIO Size to 3GiB
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86623?usp=email ) Change subject: mb/starlabs/starbook/mtl: Set the MMIO Size to 3GiB ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a2a3e737eeb9282a4edf09eb0a24019ceeb016e Gerrit-Change-Number: 86623 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 27 Feb 2025 21:36:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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