coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Allow boards to disable INTEL_TME
by Jérémy Compostella (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Matt DeVillier, Tarun. Jérémy Compostella has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86621?usp=email ) Change subject: soc/intel/meteorlake: Allow boards to disable INTEL_TME ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09 Gerrit-Change-Number: 86621 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 17:55:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Allow boards to disable INTEL_TME
by Subrata Banik (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Matt DeVillier, Tarun. Subrata Banik has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86621?usp=email ) Change subject: soc/intel/meteorlake: Allow boards to disable INTEL_TME ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09 Gerrit-Change-Number: 86621 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 17:34:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD
by Subrata Banik (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85131?usp=email ) Change subject: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD ...................................................................... Patch Set 13: (1 comment) Patchset: PS6: > We probably can find common ground, but that would mean using the lowest common denominator, which to my understanding might undermine the performances. I would think we do not want to go that route. > > `b001`, `b004`, and `b00a` are from the Panther Lake H12Xe family, while `b002` is from the PTL H4Xe family. These two families have different IA, GT, and SA I_TRIP_NOM values. If a variant needs to support both families, I need to introduce some software architectural changes. Could you tell me if you have a variant that supports both families? do you want to push this CL as base for CB:86622 ? btw, in absence of devicetree override these UPDs would be set as zero aka disable . do you see any risk ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie72e4725cb97b4af7843a43eeaedd687d28b6752 Gerrit-Change-Number: 85131 Gerrit-PatchSet: 13 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 17:33:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Add TODO for Fast VMode settings
by Jérémy Compostella (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86622?usp=email to look at the new patch set (#2). Change subject: mainboard/google/fatcat: Add TODO for Fast VMode settings ...................................................................... mainboard/google/fatcat: Add TODO for Fast VMode settings We've added a TODO comment to the device tree configuration file to remind us to set the appropriate values for 'enable_fast_vmode', 'cep_enable', and 'fast_vmode_i_trip' chipset fields. These settings are critical for achieving optimal power performance and efficiency in the Panther Lake U series. Currently, no actual values have been set, as further investigation and testing are required to determine the most effective configurations. The TODO comment serves as a placeholder for these values and a reminder to revisit this as part of our ongoing development efforts for the Fatcat project. Further commits will include the fine-tuning of these parameters after extensive testing to ensure they meet our performance and power criteria without compromising system stability. BUG=b:357011633 Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/86622/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6 Gerrit-Change-Number: 86622 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Allow boards to disable INTEL_TME
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86621?usp=email to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Allow boards to disable INTEL_TME ...................................................................... soc/intel/meteorlake: Allow boards to disable INTEL_TME Allow boards to disable TME (total memory encryption) by guarding selection of TME_KEY_REGENERATION_ON_WARM_BOOT on INTEL_TME. This way, boards can set INTEL_TME to n in their Kconfig without generating an unmet dependencies error. The default behavior/Kconfig selections are unmodified with this change. Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/86621/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09 Gerrit-Change-Number: 86621 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Add TODO for Fast VMode settings
by Jérémy Compostella (Code Review) 27 Feb '25

27 Feb '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86622?usp=email ) Change subject: mainboard/google/fatcat: Add TODO for Fast VMode settings ...................................................................... mainboard/google/fatcat: Add TODO for Fast VMode settings We've added a TODO comment to the device tree configuration file to remind us to set the appropriate values for 'enable_fast_vmode', 'cep_enable', and 'fast_vmode_i_trip' chipset fields. These settings are critical for achieving optimal power performance and efficiency in the Panther Lake U series. Currently, no actual values have been set as further investigation and testing are required to determine the most effective configurations. The TODO comments serve as a placeholder for these values and a reminder to revisit this as part of our ongoing development efforts of the Fatcat project. Further commits will include the fine-tuning of these parameters after extensive testing to ensure they meet our performance and power criteria without compromising system stability. BUG=b:357011633 Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/86622/1 diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index b09f9e3..584354e 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -62,6 +62,10 @@ # Enable Energy Reporting register "pch_pm_energy_report_enable" = "true" + # TODO: Set Fast VMode Voltage Regulator fine tuned values for + # PTL U (enable_fast_vmode, cep_enable and fast_vmode_i_trip + # chipset fields). + # Enable CNVi BT register "cnvi_bt_core" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/86622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6 Gerrit-Change-Number: 86622 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Allow boards to disable INTEL_TME
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86621?usp=email ) Change subject: soc/intel/meteorlake: Allow boards to disable INTEL_TME ...................................................................... soc/intel/meteorlake: Allow boards to disable INTEL_TME Allow boards to disable TME (total memory encryption) by guarding selection of TME_KEY_REGENERATION_ON_WARM_BOOT on INTEL_TME. This way, boards can set INTEL_TME to n in their Kconfig without generating an unmet dependencies error. The default behavior/Kconfig selectons are unmodified with this change. Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/86621/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index bc0183d..d5b4a06 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -99,7 +99,7 @@ select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TME_KEY_REGENERATION_ON_WARM_BOOT + select TME_KEY_REGENERATION_ON_WARM_BOOT if INTEL_TME select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202302_BINDING -- To view, visit https://review.coreboot.org/c/coreboot/+/86621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09 Gerrit-Change-Number: 86621 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Naresh Solanki (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune, Patrick Rudolph, Paul Menzel. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... Patch Set 5: (3 comments) File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/0d183f40_59def24c?us… : PS5, Line 24: uint32_t leaf = DETERMINISTIC_CACHE_PARAMETERS_CPUID_AMD; : uint8_t level = 3; : : struct cpuid_result cache_info_res = cpuid_ext(leaf, level); : : info->type = CPUID_CACHE_TYPE(cache_info_res); : info->level = CPUID_CACHE_LEVEL(cache_info_res); : info->num_ways = CPUID_CACHE_WAYS_OF_ASSOC(cache_info_res) + 1; : info->num_sets = CPUID_CACHE_NO_OF_SETS(cache_info_res) + 1; : info->line_size = CPUID_CACHE_COHER_LINE(cache_info_res) + 1; : info->physical_partitions = CPUID_CACHE_PHYS_LINE(cache_info_res) + 1; : info->num_cores_shared = CPUID_CACHE_SHARING_CACHE(cache_info_res) + 1; : info->fully_associative = CPUID_CACHE_FULL_ASSOC(cache_info_res); : info->size = get_cache_size(info); > This is pretty much the same as `fill_cpu_cache_info` (excluding the call to `soc_fill_cpu_cache_inf […] 1. yes its possible to deduplicate it. 2. Multiplying uniq id with cache size might not work considering that glinda SoC has 16MB + 8MB. We want it to report total L3 cache as 24MB instead of 32. https://review.coreboot.org/c/coreboot/+/85640/comment/a4cbdb10_ee6026c3?us… : PS5, Line 52: if (!info) : return false; > This is checked by `fill_cpu_cache_info` Acknowledged https://review.coreboot.org/c/coreboot/+/85640/comment/1d82fb47_de5ac3b4?us… : PS5, Line 70: :: > nit: drop one colon […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 17:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Angel Pons (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Alicja Michalska, Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86131?usp=email ) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 10 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 17:07:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: Kconfig: Update prompt and help text for CBFS_SIZE
by Angel Pons (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Alexander Couzens, Alicja Michalska, Christian Walter, Dinesh Gehlot, Eran Mitrani, Erik van den Bogaert, Felix Held, Felix Singer, Frans Hendriks, Fred Reitberger, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jason Glenesk, Jason Nien, Jayvik Desai, Jeremy Soller, Jonathon Hall, Jérémy Compostella, Kapil Porwal, Martin L Roth, Martin Roth, Maxim Polyakov, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nicholas Chin, Nick Vaccaro, Patrick Rudolph, Piotr Król, Pranava Y N, Shuo Liu, Stefan Ott, Subrata Banik, Tarun, Tim Crawford, Werner Zeh, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86571?usp=email ) Change subject: Kconfig: Update prompt and help text for CBFS_SIZE ...................................................................... Patch Set 8: (2 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/86571/comment/7657b086_6c8a9f83?us… : PS8, Line 641: ROM (Read-Only Memory) Technically speaking, it can't be ROM - otherwise you wouldn't be able to flash coreboot :D https://review.coreboot.org/c/coreboot/+/86571/comment/07e2cfee_b4975e5f?us… : PS8, Line 644: Firmware > ```suggestion […] N.B. I've seen Intel documents refer to the IFD both as "Intel Firmware Descriptor" and as "Intel Flash Descriptor". -- To view, visit https://review.coreboot.org/c/coreboot/+/86571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I762042fae6357ee368b22a47b8e1168902041675 Gerrit-Change-Number: 86571 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix 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Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 17:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit February 2025