coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Set psys_pmax_watts to 65W
by Sean Rhodes (Code Review) 27 Feb '25

27 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86629?usp=email ) Change subject: mb/starlabs/starbook/mtl: Set psys_pmax_watts to 65W ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0460f87deb23925db30829135a4d3b9bfc92bf6 Gerrit-Change-Number: 86629 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 27 Feb 2025 20:30:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Move IOE Bar
by Sean Rhodes (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86309?usp=email to look at the new patch set (#4). Change subject: soc/intel/meteorlake: Move IOE Bar ...................................................................... soc/intel/meteorlake: Move IOE Bar When using large amounts of memory, there aren't enough MTRR's: [ERROR] Not enough MTRRs available! MTRR index is 10... [WARN ] Not enough MTRRs: 11 vs 10 Move the IOE bar to save space. Test=boot `starlabs/starbook/mtl` and check MTRR limit isn't exceeded. Change-Id: Ie29618739d98f0d0c3995a60377083036f23ff18 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/include/soc/iomap.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/86309/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86309?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie29618739d98f0d0c3995a60377083036f23ff18 Gerrit-Change-Number: 86309 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

1 0

[S] Change in coreboot[main]: soc/amd/glinda/Kconfig: Increase APOB NV size
by Maximilian Brune (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Hello Felix Held, Fred Reitberger, Jason Glenesk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86624?usp=email to look at the new patch set (#2). Change subject: soc/amd/glinda/Kconfig: Increase APOB NV size ...................................................................... soc/amd/glinda/Kconfig: Increase APOB NV size A glinda based platform reports: [WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000 APOB NV size is not enough on recent platforms to cache memory training, which causes the same amount of boot time on subsequent boots as on the first boot. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I8cc1f1e4f8d6f99c8e2b717926b66a5a683bffdc --- M src/mainboard/amd/birman/board_glinda.fmd M src/mainboard/amd/birman/chromeos_glinda.fmd M src/mainboard/amd/birman_plus/board_glinda.fmd M src/mainboard/amd/birman_plus/chromeos_glinda.fmd M src/soc/amd/glinda/Kconfig 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/86624/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86624?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8cc1f1e4f8d6f99c8e2b717926b66a5a683bffdc Gerrit-Change-Number: 86624 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[S] Change in coreboot[main]: soc/intel/meteorlake: Add support for USB wake up
by Sean Rhodes (Code Review) 27 Feb '25

27 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86628?usp=email ) Change subject: soc/intel/meteorlake: Add support for USB wake up ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67da6af619db947ab4830fa2d9904f3e70fbfd21 Gerrit-Change-Number: 86628 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 27 Feb 2025 20:23:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: soc/amd: Rename PSP_APOB_DRAM_SIZE -> PSP_APOB_NV_DRAM_SIZE
by Maximilian Brune (Code Review) 27 Feb '25

27 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86627?usp=email ) Change subject: soc/amd: Rename PSP_APOB_DRAM_SIZE -> PSP_APOB_NV_DRAM_SIZE ...................................................................... soc/amd: Rename PSP_APOB_DRAM_SIZE -> PSP_APOB_NV_DRAM_SIZE Since there is both an APOB as well as a APOB_NV region it is confusing when the naming is mixed. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I8f497685dfe51a7a5283f6d7421e7273cb8b4b1d --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/glinda/Kconfig M src/soc/amd/mendocino/Kconfig M src/soc/amd/phoenix/Kconfig M src/soc/amd/picasso/Kconfig 8 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86627/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7b97ce7..ba0d80c 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -132,7 +132,7 @@ Location in DRAM where the PSP will copy the AGESA PSP Output Block. -config PSP_APOB_DRAM_SIZE +config PSP_APOB_NV_DRAM_SIZE hex default 0x10000 diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index 713826a..470ce1c 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -41,10 +41,10 @@ #error Incorrect APOB configuration setting(s) #endif -_Static_assert(CONFIG_PSP_APOB_DRAM_SIZE == DEFAULT_MRC_CACHE_SIZE, +_Static_assert(CONFIG_PSP_APOB_NV_DRAM_SIZE == DEFAULT_MRC_CACHE_SIZE, "APOB DRAM reserved space != to MRC CACHE size - check your config"); -_Static_assert(CONFIG_PSP_APOB_DRAM_SIZE == RECOVERY_MRC_CACHE_SIZE, +_Static_assert(CONFIG_PSP_APOB_NV_DRAM_SIZE == RECOVERY_MRC_CACHE_SIZE, "APOB DRAM reserved space != to RECOVERY MRC CACHE size - check your config"); #define APOB_SIGNATURE 0x424F5041 /* 'APOB' */ diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 3c596f4..63eba25 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -62,7 +62,7 @@ * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 * | Transfer Info Structure | * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (PSP_APOB_DRAM_SIZE) | + * | APOB (PSP_APOB_NV_DRAM_SIZE) | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS * | Early BSP stack | * | (EARLYRAM_BSP_STACK_SIZE) | @@ -83,7 +83,7 @@ EARLY_RESERVED_DRAM_START(CONFIG_EARLY_RESERVED_DRAM_BASE) EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE) - REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, CONFIG_PSP_APOB_DRAM_SIZE, 1) + REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, CONFIG_PSP_APOB_NV_DRAM_SIZE, 1) #if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE) diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig index 25dd914..5aec453 100644 --- a/src/soc/amd/genoa_poc/Kconfig +++ b/src/soc/amd/genoa_poc/Kconfig @@ -87,7 +87,7 @@ Location in DRAM where the PSP will copy the AGESA PSP Output Block. -config PSP_APOB_DRAM_SIZE +config PSP_APOB_NV_DRAM_SIZE hex default 0x20000 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 1bd5b2f..38002a0 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -121,7 +121,7 @@ Location in DRAM where the PSP will copy the AGESA PSP Output Block. -config PSP_APOB_DRAM_SIZE +config PSP_APOB_NV_DRAM_SIZE hex default 0x40000 diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index ee6c968..4d1a4e1 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -152,7 +152,7 @@ Location in DRAM where the PSP will copy the AGESA PSP Output Block. -config PSP_APOB_DRAM_SIZE +config PSP_APOB_NV_DRAM_SIZE hex default 0x1E000 diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index b15c12d..e7f450c 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -134,7 +134,7 @@ Location in DRAM where the PSP will copy the AGESA PSP Output Block. -config PSP_APOB_DRAM_SIZE +config PSP_APOB_NV_DRAM_SIZE hex default 0x40000 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f450e29..52b16d9 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -122,7 +122,7 @@ Location in DRAM where the PSP will copy the AGESA PSP Output Block. -config PSP_APOB_DRAM_SIZE +config PSP_APOB_NV_DRAM_SIZE hex default 0x10000 -- To view, visit https://review.coreboot.org/c/coreboot/+/86627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f497685dfe51a7a5283f6d7421e7273cb8b4b1d Gerrit-Change-Number: 86627 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Set the default to Software Connection Manager
by Sean Rhodes (Code Review) 27 Feb '25

27 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86626?usp=email ) Change subject: soc/intel/meteorlake: Set the default to Software Connection Manager ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4868acdb59fca9253005222b4080356dd61b1855 Gerrit-Change-Number: 86626 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 27 Feb 2025 19:56:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/amd/glinda/Kconfig: Increase APOB NV size
by Maximilian Brune (Code Review) 27 Feb '25

27 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86624?usp=email ) Change subject: soc/amd/glinda/Kconfig: Increase APOB NV size ...................................................................... soc/amd/glinda/Kconfig: Increase APOB NV size A glinda based platform reports: [WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000 APOB NV size is not enough on recent platforms to cache memory training, which causes the same amount of boot time on subsequent boots as on the first boot. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I8cc1f1e4f8d6f99c8e2b717926b66a5a683bffdc --- M src/mainboard/amd/birman/board_glinda.fmd M src/mainboard/amd/birman_plus/board_glinda.fmd M src/soc/amd/glinda/Kconfig 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/86624/1 diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd index 7567090..bc09fe7 100644 --- a/src/mainboard/amd/birman/board_glinda.fmd +++ b/src/mainboard/amd/birman/board_glinda.fmd @@ -4,6 +4,6 @@ FMAP 4K COREBOOT(CBFS) EC_BODY@15872K 256K - RW_MRC_CACHE 120K + RW_MRC_CACHE 256K } } diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd index b946576..96e1e8d 100644 --- a/src/mainboard/amd/birman_plus/board_glinda.fmd +++ b/src/mainboard/amd/birman_plus/board_glinda.fmd @@ -5,6 +5,6 @@ COREBOOT(CBFS) SMMSTORE(PRESERVE) 256K EC_BODY@15872K 256K - RW_MRC_CACHE 120K + RW_MRC_CACHE 256K } } diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 70bdb69..1bd5b2f 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -123,7 +123,7 @@ config PSP_APOB_DRAM_SIZE hex - default 0x1E000 + default 0x40000 config PSP_SHAREDMEM_BASE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/86624?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8cc1f1e4f8d6f99c8e2b717926b66a5a683bffdc Gerrit-Change-Number: 86624 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Move IOE Bar
by Sean Rhodes (Code Review) 27 Feb '25

27 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86309?usp=email ) Change subject: soc/intel/meteorlake: Move IOE Bar ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86309?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie29618739d98f0d0c3995a60377083036f23ff18 Gerrit-Change-Number: 86309 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Feb 2025 19:45:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Set the MMIO Size to 3GiB
by Sean Rhodes (Code Review) 27 Feb '25

27 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86623?usp=email ) Change subject: mb/starlabs/starbook/mtl: Set the MMIO Size to 3GiB ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a2a3e737eeb9282a4edf09eb0a24019ceeb016e Gerrit-Change-Number: 86623 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 27 Feb 2025 19:45:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
by Bora Guvendik (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim. Bora Guvendik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86414?usp=email ) Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86414?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 Gerrit-Change-Number: 86414 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 17:59:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025