coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Move IOE Bar
by Subrata Banik (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Sean Rhodes, Tarun. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86309?usp=email ) Change subject: soc/intel/meteorlake: Move IOE Bar ...................................................................... Patch Set 4: Code-Review-2 (1 comment) Patchset: PS4: Please take a look at Intel FAS where it's clear that IOE BAR has moved > 4GB of boundary. -- To view, visit https://review.coreboot.org/c/coreboot/+/86309?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie29618739d98f0d0c3995a60377083036f23ff18 Gerrit-Change-Number: 86309 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:55:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Enable Type-C Ports and TBT
by Weimin Wu (Code Review) 27 Feb '25

27 Feb '25

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86633?usp=email ) Change subject: mb/google/fatcat/var/felino: Enable Type-C Ports and TBT ...................................................................... mb/google/fatcat/var/felino: Enable Type-C Ports and TBT Test with PDC fw 19.16.3. BUG=b:397313651 TEST= 1. FW_NAME=felino emerge-fatcat coreboot-private-files-baseboard-fatcat coreboot chromeos-bootimage 2. Type-C Ports and TBT work fine. Change-Id: Icbed4d16911665e820382a483607e6dae44b7f8c Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/felino/gpio.c M src/mainboard/google/fatcat/variants/felino/overridetree.cb 2 files changed, 27 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/86633/1 diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index e5ca754..a32d44b7 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -68,7 +68,7 @@ /* GPP_B09: NC */ PAD_NC(GPP_B09, NONE), /* GPP_B10: SOC_DP1_HDMI_HPD */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2), /* GPP_B11: PD1_OC_P0_P1_N */ PAD_NC(GPP_B11, NONE), /* GPP_B12: SLP_S0_SOC_N */ @@ -137,9 +137,9 @@ /* GPP_C17: NC */ PAD_NC(GPP_C17, NONE), /* GPP_C18: TCP3_DDC_SCL */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF2), /* GPP_C19: TCP3_DDC_SDA */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF2), /* GPP_C20: TBT_LSX1_TXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GPP_C21: TBT_LSX1_RXD */ diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 6b4d32e..c13aa43 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -34,11 +34,17 @@ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 # USB HUB (USB2 Camera) - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port A1 / + register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # Type-A Port A1 / register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 / + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN" + #gpe configuration register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw1" = "GPP_D" @@ -83,6 +89,9 @@ device ref iaa off end +device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on @@ -93,7 +102,7 @@ device ref tcss_usb3_port2 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C3"" + register "desc" = ""USB3 Type-C Port C1"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref tcss_usb3_port3 on end @@ -102,6 +111,19 @@ end end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F11)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F11)" + use tcss_usb3_port2 as dfp[1].typec_port + device generic 0 on end + end + end + device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on @@ -145,17 +167,6 @@ end end - device ref tcss_dma1 on - chip drivers/intel/usb4/retimer - use tcss_usb3_port2 as dfp[0].typec_port - device generic 0 on end - end - chip drivers/intel/usb4/retimer - use tcss_usb3_port3 as dfp[1].typec_port - device generic 0 on end - end - end - device ref pcie_rp1 on # Enable PCH PCIE x1 slot using CLK 2 register "pcie_rp[PCIE_RP(3)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/86633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbed4d16911665e820382a483607e6dae44b7f8c Gerrit-Change-Number: 86633 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>

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[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Jérémy Compostella (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Paul Menzel, Zhixing Ma. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84564?usp=email ) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/ptlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/84564/comment/659b1dcb_5c34619a?us… : PS6, Line 3: config BOARD_INTEL_PTLRVP_COMMON > There is no plan to support configuration blocks on Panther Lake. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:43:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Jérémy Compostella (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Paul Menzel, Zhixing Ma. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84564?usp=email ) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/ptlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/84564/comment/ab6be459_e78be8c3?us… : PS6, Line 3: config BOARD_INTEL_PTLRVP_COMMON > Currently, we are using fsp_param.c. […] There is no plan to support configuration blocks on Panther Lake. -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:43:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 7: (2 comments) Patchset: PS6: > Looks like GPIO 5 is reset by either RSMRST# (pin 101) or SLPS5# (pin 84) depending on the setting i […] According to the SIO datasheet I could temporarily change RSTOUT2# to GP76 using config register 0x2b and manually pulse the reset lines on the PCH PCIe slots this way. (I would need this one to be OD - it has a pull up.) Am I being too ambitious? Looks like the root cause is a disruption of PCIe clock between PCIEX1_2 and ASM1061. Sadly the only reset signal ASM1061 gets is PLTRST#, so a system_reset() is still going to be necessary. Patchset: PS7: I implemented the additional logic Nicholas suggested. Let's give it a try. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:29:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Angel Pons, Keith Hui. Hello Bill XIE, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85413?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... mb/asus/p8z77-v: Attempt to correctly route PCIe lanes Bill Xie documented in his initial code drop that he was unsuccessful in reproducing all the PCIe configurations possible with vendor firmware. I obtained a boardview to this board and have identified the PCIe lane topology and the required control signals. There are PCIe slot presence signals wired to GPIOs 34,20,7 for PCIEX1_1,PCIEX1_2,PCIEX16_3 respectively, the last one only sense the presence of a PCIe x4 or larger card. PCIe lanes 1-4 are routed by way of three ASM1440 2-way switches controlled by GP54-GP56 on NCT6779D super I/O chip. PCIe lanes 5-8 are fixed. With these details, it is now possible to attempt to reproduce all the vendor PCIe configurations. 1. Change GPIO20 of PCH to GPIO input so coreboot can detect a card inserted into PCIEX1_2. 2. Add an nvram option to force PCIe lane 4 to serve ASM1061 and its two SATA 6Gbps ports. Another one needs to be added later to enable users to allocate all lanes to PCIEX16_3 and make it x4. 3. Add code to bootblock to check the PCHSTRP9 soft strap and whether (1) is true. There is a sanity check to warn of a PCIe configuration that is not valid on this board. 4. Based on (1) and (2), program SIO GPIO5 as appropriate. Remove all GPIO5 settings from devicetree so this code has full control. Changing PCIEX16_3 from x1 to x4 (and vice versa) requires changing PCHSTRP9 in the SPI flash descriptor. How coreboot can manage this is TBD. This is based on boardview only, and is untested because I have no hardware. Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb 5 files changed, 126 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85413/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: payloads/libpayload: Add fast data types to types.h
by Yu-Ping Wu (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Hsuan-ting Chen, Julius Werner. Yu-Ping Wu has posted comments on this change by Masa Nakura. ( https://review.coreboot.org/c/coreboot/+/86632?usp=email ) Change subject: payloads/libpayload: Add fast data types to types.h ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9197866ae9b6c27d3f26c11d8409ecb90321c74 Gerrit-Change-Number: 86632 Gerrit-PatchSet: 2 Gerrit-Owner: Masa Nakura <nakura(a)google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:09:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: amdfwtool: Move ISH before PSP L2
by Bao Zheng (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Maximilian Brune, Zheng Bao, ritul guru. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84533?usp=email ) Change subject: amdfwtool: Move ISH before PSP L2 ...................................................................... Patch Set 12: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84533/comment/dd7d3bf6_91238841?us… : PS12, Line 972: if (!cb_config->combo_new_rab || ctx->combo_index == 0) { : pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie); : ctx->pspdir = pspdir; : if (recovery_ab) : ctx->pspdir_bak = new_psp_dir(ctx, cb_config->multi_level, cookie); : } : /* The ISH tables are with PSP L1. */ : if (cb_config->need_ish && ctx->ish_a_dir == NULL) /* Need ISH */ : ctx->ish_a_dir = new_ish_dir(ctx); : if (cb_config->need_ish && ctx->ish_b_dir == NULL) /* Need ISH */ : ctx->ish_b_dir = new_ish_dir(ctx); > For the family older than mendocino, it uses the old combo definition. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75 Gerrit-Change-Number: 84533 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 02:04:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: payloads/libpayload: Add fast data types to types.h
by Masa Nakura (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Hsuan-ting Chen, Yu-Ping Wu. Hello Hsuan-ting Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86632?usp=email to look at the new patch set (#2). Change subject: payloads/libpayload: Add fast data types to types.h ...................................................................... payloads/libpayload: Add fast data types to types.h libpayload stdint.h only supports typedefs for datatypes of exact bits. This makes libpayload less flexible to support libraries that reference different data types. Add fast data types in types.h. BUG=b:386913035 Change-Id: Ie9197866ae9b6c27d3f26c11d8409ecb90321c74 Signed-off-by: Masa Nakura <nakura(a)google.com> --- M payloads/libpayload/include/arm/arch/types.h M payloads/libpayload/include/arm64/arch/types.h M payloads/libpayload/include/mock/arch/types.h M payloads/libpayload/include/x86/arch/types.h 4 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86632/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9197866ae9b6c27d3f26c11d8409ecb90321c74 Gerrit-Change-Number: 86632 Gerrit-PatchSet: 2 Gerrit-Owner: Masa Nakura <nakura(a)google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: payloads/libpayload/include: Add fast data types to types.h
by Masa Nakura (Code Review) 27 Feb '25

27 Feb '25

Masa Nakura has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86632?usp=email ) Change subject: payloads/libpayload/include: Add fast data types to types.h ...................................................................... payloads/libpayload/include: Add fast data types to types.h libpayload stdint.h only supports typedefs for datatypes of exact bits. This makes libpayload less flexible to support libraries that reference different data types. Add fast data types in types.h. BUG=b:386913035 Change-Id: Ie9197866ae9b6c27d3f26c11d8409ecb90321c74 Signed-off-by: Masa Nakura <nakura(a)google.com> --- M payloads/libpayload/include/arm/arch/types.h M payloads/libpayload/include/arm64/arch/types.h M payloads/libpayload/include/mock/arch/types.h M payloads/libpayload/include/x86/arch/types.h 4 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86632/1 diff --git a/payloads/libpayload/include/arm/arch/types.h b/payloads/libpayload/include/arm/arch/types.h index 3f2eeaa..43ba84e 100644 --- a/payloads/libpayload/include/arm/arch/types.h +++ b/payloads/libpayload/include/arm/arch/types.h @@ -30,23 +30,31 @@ #define _ARCH_TYPES_H typedef unsigned char uint8_t; +typedef unsigned char uint_fast8_t; typedef unsigned char u8; typedef signed char int8_t; +typedef signed char int_fast8_t; typedef signed char s8; typedef unsigned short uint16_t; typedef unsigned short u16; +typedef unsigned short uint_fast16_t; typedef signed short int16_t; +typedef signed short int_fast16_t; typedef signed short s16; typedef unsigned int uint32_t; +typedef unsigned int uint_fast32_t; typedef unsigned int u32; typedef signed int int32_t; +typedef signed int int_fast32_t; typedef signed int s32; typedef unsigned long long uint64_t; +typedef unsigned long long uint_fast64_t; typedef unsigned long long u64; typedef signed long long int64_t; +typedef signed long long int_fast64_t; typedef signed long long s64; typedef long time_t; diff --git a/payloads/libpayload/include/arm64/arch/types.h b/payloads/libpayload/include/arm64/arch/types.h index 3f2eeaa..43ba84e 100644 --- a/payloads/libpayload/include/arm64/arch/types.h +++ b/payloads/libpayload/include/arm64/arch/types.h @@ -30,23 +30,31 @@ #define _ARCH_TYPES_H typedef unsigned char uint8_t; +typedef unsigned char uint_fast8_t; typedef unsigned char u8; typedef signed char int8_t; +typedef signed char int_fast8_t; typedef signed char s8; typedef unsigned short uint16_t; typedef unsigned short u16; +typedef unsigned short uint_fast16_t; typedef signed short int16_t; +typedef signed short int_fast16_t; typedef signed short s16; typedef unsigned int uint32_t; +typedef unsigned int uint_fast32_t; typedef unsigned int u32; typedef signed int int32_t; +typedef signed int int_fast32_t; typedef signed int s32; typedef unsigned long long uint64_t; +typedef unsigned long long uint_fast64_t; typedef unsigned long long u64; typedef signed long long int64_t; +typedef signed long long int_fast64_t; typedef signed long long s64; typedef long time_t; diff --git a/payloads/libpayload/include/mock/arch/types.h b/payloads/libpayload/include/mock/arch/types.h index 8f090ca..63b0e86 100644 --- a/payloads/libpayload/include/mock/arch/types.h +++ b/payloads/libpayload/include/mock/arch/types.h @@ -4,23 +4,31 @@ #define _ARCH_TYPES_H typedef unsigned char uint8_t; +typedef unsigned char uint_fast8_t; typedef unsigned char u8; typedef signed char int8_t; +typedef signed char int_fast8_t; typedef signed char s8; typedef unsigned short uint16_t; typedef unsigned short u16; +typedef unsigned short uint_fast16_t; typedef signed short int16_t; +typedef signed short int_fast16_t; typedef signed short s16; typedef unsigned int uint32_t; +typedef unsigned int uint_fast32_t; typedef unsigned int u32; typedef signed int int32_t; +typedef signed int int_fast32_t; typedef signed int s32; typedef unsigned long long uint64_t; +typedef unsigned long long uint_fast64_t; typedef unsigned long long u64; typedef signed long long int64_t; +typedef signed long long int_fast64_t; typedef signed long long s64; typedef long time_t; diff --git a/payloads/libpayload/include/x86/arch/types.h b/payloads/libpayload/include/x86/arch/types.h index 3f2eeaa..43ba84e 100644 --- a/payloads/libpayload/include/x86/arch/types.h +++ b/payloads/libpayload/include/x86/arch/types.h @@ -30,23 +30,31 @@ #define _ARCH_TYPES_H typedef unsigned char uint8_t; +typedef unsigned char uint_fast8_t; typedef unsigned char u8; typedef signed char int8_t; +typedef signed char int_fast8_t; typedef signed char s8; typedef unsigned short uint16_t; typedef unsigned short u16; +typedef unsigned short uint_fast16_t; typedef signed short int16_t; +typedef signed short int_fast16_t; typedef signed short s16; typedef unsigned int uint32_t; +typedef unsigned int uint_fast32_t; typedef unsigned int u32; typedef signed int int32_t; +typedef signed int int_fast32_t; typedef signed int s32; typedef unsigned long long uint64_t; +typedef unsigned long long uint_fast64_t; typedef unsigned long long u64; typedef signed long long int64_t; +typedef signed long long int_fast64_t; typedef signed long long s64; typedef long time_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/86632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9197866ae9b6c27d3f26c11d8409ecb90321c74 Gerrit-Change-Number: 86632 Gerrit-PatchSet: 1 Gerrit-Owner: Masa Nakura <nakura(a)google.com>

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