coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Angel Pons (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Jérémy Compostella, Maximilian Brune, Naresh Solanki, Patrick Rudolph, Paul Menzel. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... Patch Set 5: (3 comments) File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/920a8788_f06336c0?us… : PS5, Line 24: uint32_t leaf = DETERMINISTIC_CACHE_PARAMETERS_CPUID_AMD; : uint8_t level = 3; : : struct cpuid_result cache_info_res = cpuid_ext(leaf, level); : : info->type = CPUID_CACHE_TYPE(cache_info_res); : info->level = CPUID_CACHE_LEVEL(cache_info_res); : info->num_ways = CPUID_CACHE_WAYS_OF_ASSOC(cache_info_res) + 1; : info->num_sets = CPUID_CACHE_NO_OF_SETS(cache_info_res) + 1; : info->line_size = CPUID_CACHE_COHER_LINE(cache_info_res) + 1; : info->physical_partitions = CPUID_CACHE_PHYS_LINE(cache_info_res) + 1; : info->num_cores_shared = CPUID_CACHE_SHARING_CACHE(cache_info_res) + 1; : info->fully_associative = CPUID_CACHE_FULL_ASSOC(cache_info_res); : info->size = get_cache_size(info); This is pretty much the same as `fill_cpu_cache_info` (excluding the call to `soc_fill_cpu_cache_info`). I'm wondering if there's any way to deduplicate it - perhaps by introducing an "internal" function in `cpu_common.c`. Also, could any of these values be different between cores of a CPU? If not (this information is the same for all CPUs), it would be easier to count the number of unique IDs and multiply the cache size by that number. Which would simplify things quite a bit - common code can fill in the parameters, and `soc_fill_cpu_cache_info` would be adapted to run after that to modify/extend the cache info accordingly. https://review.coreboot.org/c/coreboot/+/85640/comment/1693e322_8a05818a?us… : PS5, Line 52: if (!info) : return false; This is checked by `fill_cpu_cache_info` https://review.coreboot.org/c/coreboot/+/85640/comment/a4f8ded1_b46f44e5?us… : PS5, Line 70: :: nit: drop one colon ```suggestion printk(BIOS_SPEW, " Cache ID: %d\n", info_list[i].unique_id); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 17:03:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Alicja Michalska, Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Matt DeVillier has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86131?usp=email ) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... Patch Set 10: Code-Review+1 (1 comment) Patchset: PS9: > after re-reviewing the code in question I agree with Angel that the rename isn't correct. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 10 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 16:52:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: Kconfig: Update prompt and help text for CBFS_SIZE
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Alexander Couzens, Alicja Michalska, Angel Pons, Christian Walter, Dinesh Gehlot, Eran Mitrani, Erik van den Bogaert, Felix Held, Felix Singer, Frans Hendriks, Fred Reitberger, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jason Glenesk, Jason Nien, Jayvik Desai, Jeremy Soller, Jonathon Hall, Jérémy Compostella, Kapil Porwal, Martin L Roth, Martin Roth, Maxim Polyakov, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nicholas Chin, Nick Vaccaro, Patrick Rudolph, Piotr Król, Pranava Y N, Shuo Liu, Stefan Ott, Subrata Banik, Tarun, Tim Crawford, Werner Zeh, yuchi.chen(a)intel.com. Matt DeVillier has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86571?usp=email ) Change subject: Kconfig: Update prompt and help text for CBFS_SIZE ...................................................................... Patch Set 8: (5 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/86571/comment/f5d2345e_0deaf04f?us… : PS8, Line 642: located at the end of the ROM on x86 systems and at the start of the ROM : everywhere else. This implies that x86 is top down and others are bottom up, is that what you're trying to say? https://review.coreboot.org/c/coreboot/+/86571/comment/0984de05_9d87ebfe?us… : PS8, Line 644: Firmware ```suggestion Intel systems that use an Intel Flash Descriptor. It can be overridden to ``` https://review.coreboot.org/c/coreboot/+/86571/comment/1e81d77c_14654c6c?us… : PS8, Line 646: Firmware Descriptor ```suggestion Flash Descriptor), ME (Management Engine), and TXE (Trusted Execution ``` https://review.coreboot.org/c/coreboot/+/86571/comment/4ab6c6d4_f23eca5e?us… : PS8, Line 647: should only be used ```suggestion Engine) binaries. This symbol is only used to generate a default FMAP ``` https://review.coreboot.org/c/coreboot/+/86571/comment/5c54642f_5b0baf2f?us… : PS8, Line 648: non-default ```suggestion (Flash Memory Map) and is unused when a .fmd file is provided ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/86571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I762042fae6357ee368b22a47b8e1168902041675 Gerrit-Change-Number: 86571 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 16:52:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Angel Pons (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Jérémy Compostella, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 16:48:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Angel Pons (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Jérémy Compostella, Maximilian Brune, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 16:48:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/dram/ddr5: Add 7500 MT/s support
by Angel Pons (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Maximilian Brune, Paul Menzel. Angel Pons has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86543?usp=email ) Change subject: device/dram/ddr5: Add 7500 MT/s support ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/device/dram/ddr5.c: https://review.coreboot.org/c/coreboot/+/86543/comment/9bf2d649_d615f339?us… : PS2, Line 24: DDR5_7500, Do you know if there are any speed grades in between? -- To view, visit https://review.coreboot.org/c/coreboot/+/86543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d Gerrit-Change-Number: 86543 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 16:47:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Alicja Michalska (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Alicja Michalska, Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86131?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... device/Kconfig: Make option to allocate above 4G appear in Kconfig Previously only tested on server platforms - it wasn't working correctly on consumer platforms due to missing boolean. This patch fixes it, which makes resource allocator use uint64 instead of uint32. Thanks to that, modern GPUs like Intel Arc or Radeon RX now work correctly with ReBAR enabled, and correctly initialize the framebuffer in payload (i.e EDK2) after initializing the OpROMs. Example of issue caused by resource allocator using uint32 (Intel Arc A580): [ERROR] Resource didn't fit!!! [ERROR] PCI: 00:01:00.0 10 prefmem64 size: 0x0000800000 not assigned [ERROR] PCI: 00:03:00.0 18 prefmem64 size: 0x0200000000 not assigned (Followed by Linux reporting that BAR space was limited to 256MB, which severely hindered the performance). TESTed on Intel TigerLake-H (mb/erying/tgl) with Intel Arc A580 and AMD Radeon RX7800XT. Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M src/device/Kconfig 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/86131/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 10 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/intel/common: Add support for WiFi SW RF Kill on CNVi
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Nick Vaccaro, Sean Rhodes, Subrata Banik. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86403?usp=email ) Change subject: soc/intel/common: Add support for WiFi SW RF Kill on CNVi ...................................................................... Patch Set 30: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Gerrit-Change-Number: 86403 Gerrit-PatchSet: 30 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 27 Feb 2025 16:26:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/cbfstool: Add missing \n and use __func__ in debug messages
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86567?usp=email ) Change subject: util/cbfstool: Add missing \n and use __func__ in debug messages ...................................................................... util/cbfstool: Add missing \n and use __func__ in debug messages For adding missing \n, find all potential missings by below script and apply manual checks and fixes. grep -nE "(DEBUG|ERROR)\(\".+[^\\n]\"" util/cbfstool/ -r For using __func__ in debug message, below script is used with manual checks and fixes. grep -nE "DEBUG\(.+:" util/cbfstool/ -r Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86567 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/cbfstool/cbfs_image.c M util/cbfstool/fit.c 2 files changed, 18 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index e935357..bb7c6f1 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -257,13 +257,13 @@ void *header_loc; size_t size = image->buffer.size; - DEBUG("cbfs_image_create: bootblock=0x%x+0x%zx, " - "header=0x%x+0x%zx, entries_offset=0x%x\n", + DEBUG("%s: bootblock=0x%x+0x%zx, " + "header=0x%x+0x%zx, entries_offset=0x%x\n", __func__, bootblock_offset, bootblock->size, header_offset, sizeof(image->header), entries_offset); - DEBUG("cbfs_create_image: (real offset) bootblock=0x%x, " - "header=0x%x, entries_offset=0x%x\n", + DEBUG("%s: (real offset) bootblock=0x%x, " + "header=0x%x, entries_offset=0x%x\n", __func__, bootblock_offset, header_offset, entries_offset); // Prepare bootblock @@ -636,7 +636,7 @@ if (header_offset % align) header_offset -= header_offset % align; if (header_offset < addr) { - ERROR("No space to hold cbfs_file header."); + ERROR("No space to hold cbfs_file header.\n"); return -1; } @@ -771,7 +771,7 @@ entry_size = addr_next - addr; max_null_entry_size = MAX(max_null_entry_size, entry_size); - DEBUG("cbfs_add_entry: space at 0x%x+0x%x(%d) bytes\n", + DEBUG("%s: space at 0x%x+0x%x(%d) bytes\n", __func__, addr, entry_size, entry_size); /* Will the file fit? Don't yet worry if we have space for a new @@ -783,10 +783,10 @@ // Test for complicated cases if (content_offset > 0) { if (addr_next < content_offset) { - DEBUG("Not for specified offset yet"); + DEBUG("Not for specified offset yet.\n"); continue; } else if (addr > content_offset) { - DEBUG("Exceed specified content_offset."); + DEBUG("Exceed specified content_offset.\n"); break; } else if (addr + header_size > content_offset) { ERROR("Not enough space for header.\n"); @@ -830,7 +830,7 @@ entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { if (strcasecmp(entry->filename, name) == 0) { - DEBUG("cbfs_get_entry: found %s\n", name); + DEBUG("%s: found %s\n", __func__, name); return entry; } } @@ -1323,7 +1323,7 @@ ERROR("CBFS file %s not found.\n", name); return -1; } - DEBUG("cbfs_remove_entry: Removed %s @ 0x%x\n", + DEBUG("%s: Removed %s @ 0x%x\n", __func__, entry->filename, cbfs_get_entry_addr(image, entry)); entry->type = htobe32(CBFS_TYPE_DELETED); cbfs_legacy_walk(image, cbfs_merge_empty_entry, NULL); @@ -1879,7 +1879,7 @@ } while (next != NULL); uint32_t header_size = be32toh(header->offset) + size; if (header_size > CBFS_METADATA_MAX_SIZE) { - DEBUG("exceeding allocated space for cbfs_file headers"); + DEBUG("exceeding allocated space for cbfs_file headers.\n"); return NULL; } /* attr points to the last valid attribute now. @@ -2024,14 +2024,14 @@ offset = absolute_align(image, addr + metadata_size, align); if (is_in_same_page(offset, size, page_size) && is_in_range(addr, addr_next, metadata_size, offset, size)) { - DEBUG("cbfs_locate_entry: FIT (PAGE1)."); + DEBUG("%s: FIT (PAGE1).\n", __func__); return offset; } addr2 = align_up(addr, page_size); offset = absolute_align(image, addr2, align); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { - DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); + DEBUG("%s: OVERLAP (PAGE2).\n", __func__); return offset; } @@ -2041,7 +2041,7 @@ addr3 = addr2 + page_size; offset = absolute_align(image, addr3, align); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { - DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); + DEBUG("%s: OVERLAP+ (PAGE3).\n", __func__); return offset; } } diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index d4e48f1..ca60720 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -719,12 +719,12 @@ struct fit_entry *entry; if (!fit) { - ERROR("Internal error."); + ERROR("Internal error.\n"); return 1; } if (fit_free_space(fit, max_fit_entries) < 1) { - ERROR("No space left in FIT."); + ERROR("No space left in FIT.\n"); return 1; } @@ -781,12 +781,12 @@ const size_t idx) { if (!fit) { - ERROR("Internal error."); + ERROR("Internal error.\n"); return 1; } if (idx >= fit_table_entries(fit)) { - ERROR("Index out of range."); + ERROR("Index out of range.\n"); return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/86567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8 Gerrit-Change-Number: 86567 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/meliks: Update GPIO configuration
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86378?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/meliks: Update GPIO configuration ...................................................................... mb/google/nissa/var/meliks: Update GPIO configuration Update the initial GPIO configuration for meliks by referring to the schematics. BUG=b:394359785 BRANCH=nissa TEST=FW_NAME=meliks emerge-nissa coreboot Change-Id: I33e1e3be5f2530feb396e7413f3f0cd75d5f38ca Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86378 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/variants/meliks/Makefile.mk A src/mainboard/google/brya/variants/meliks/gpio.c M src/mainboard/google/brya/variants/meliks/include/variant/gpio.h 3 files changed, 115 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/meliks/Makefile.mk b/src/mainboard/google/brya/variants/meliks/Makefile.mk index c44e4f0..227b163 100644 --- a/src/mainboard/google/brya/variants/meliks/Makefile.mk +++ b/src/mainboard/google/brya/variants/meliks/Makefile.mk @@ -1,2 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/meliks/gpio.c b/src/mainboard/google/brya/variants/meliks/gpio.c new file mode 100644 index 0000000..431b613 --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/gpio.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF6), + /* A15 : USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF6), + + /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + + /* D6 : WWAN_EN ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : WLAN_CLKREQ_ODL ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : SD_CLKREQ_ODL ==> NC */ + PAD_NC(GPP_D8, NONE), + + /* E14 : EDP_HPD ==> NC */ + PAD_NC(GPP_E14, NONE), + /* E20 : HDMI_DDC_SCL ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> LCD_RST_N - used for MIPI Power seq. */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* E23 : NC */ + PAD_NC(GPP_E23, NONE), + + /* F6 : NC */ + PAD_NC(GPP_F6, NONE), + /* F12 : GSXDOUT ==> EMR_INT_ODL */ + PAD_CFG_GPI_INT(GPP_F12, NONE, PLTRST, LEVEL), + /* F13 : SOC_PEN_DETECT_R_ODL ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F15 : SOC_PEN_DETECT_OEL ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> EMR_RESET_L */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + + /* H3 : NC */ + PAD_NC(GPP_H3, NONE), + /* H8 : I2C4_SDA ==> SOC_I2C_EMR_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : I2C4_SCL ==> SOC_I2C_EMR_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H12 : SD_PERST_L ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H19 : NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : NC */ + PAD_NC(GPP_H20, NONE), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock for pirrha */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h b/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h index c4fe342..b98b09d 100644 --- a/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h @@ -5,4 +5,6 @@ #include <baseboard/gpio.h> +#define SD_CARD_POWER GPP_H13 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33e1e3be5f2530feb396e7413f3f0cd75d5f38ca Gerrit-Change-Number: 86378 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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