coreboot-gerrit February 2025

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[S] Change in coreboot[main]: soc/amd/common: Always use genoa SPI MMAP driver
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Patrick Rudolph, Varshit Pandya. Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86618?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/amd/common: Always use genoa SPI MMAP driver ...................................................................... soc/amd/common: Always use genoa SPI MMAP driver Currently the generic x86 SPI flash mmap driver is being when not using DMA and when not on GENOA. It only works for ROM_SIZE of 16 MiB or less and prevents boot when the ROM is bigger than that. Use the genoa_poc SPI MMAP driver on all platforms by default as it allows to use a ROM_SIZE greater than 16MiB. The newly introduced Kconfig SOC_AMD_COMMON_BLOCK_SPI_MMAP is used for all platforms when the SPI DMA driver is not in use. This doesn't allow to access the whole SPI flash using the ROM2 MMIO window, but it no longer prevents boot when the mainboard specifies the correct SPI flash size in Kconfig. TEST: Booted an AMD/birman+ with 64MiB ROM specified in Kconfig. Change-Id: I39e33c71d27179212ddb1f5bcca4c5d4a39d47e4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/Makefile.mk R src/soc/amd/common/block/spi/mmap_boot.c M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/genoa_poc/Makefile.mk 5 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/86618/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e33c71d27179212ddb1f5bcca4c5d4a39d47e4 Gerrit-Change-Number: 86618 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/amd/common/block/lpc: Limit ROM2 to 16MiB
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86582?usp=email ) Change subject: soc/amd/common/block/lpc: Limit ROM2 to 16MiB ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/lpc/lpc_util.c: https://review.coreboot.org/c/coreboot/+/86582/comment/21b1c72d_5d3b9901?us… : PS1, Line 284: pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0xff00); > nit: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89 Gerrit-Change-Number: 86582 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 13:53:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: soc/amd/common/block: Cache ROM3
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86620?usp=email ) Change subject: soc/amd/common/block: Cache ROM3 ...................................................................... soc/amd/common/block: Cache ROM3 Mark ROM3 as cached in bootblock entry as done for ROM2. Mark ROM3 as cached after MP-init as done for ROM2. Change-Id: I2df51ee3f492e5a80f5ee2676196830045dcdeb3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/cpu/noncar/early_cache.c M src/soc/amd/common/block/cpu/noncar/mpinit.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/86620/1 diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c index 8c5fbc3..887ea68 100644 --- a/src/soc/amd/common/block/cpu/noncar/early_cache.c +++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c @@ -2,6 +2,7 @@ #include <amdblocks/cpu.h> #include <amdblocks/iomap.h> +#include <amdblocks/lpc.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> @@ -64,6 +65,18 @@ var_mtrr_set(&mtrr_ctx.ctx, FLASH_BELOW_4GB_MAPPING_REGION_BASE, FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); + /* ROM3 is only accessible in x86_64. Only required when ROM2 doesn't cover whole flash. */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3)) { + size_t rom3_size = 0; + uint64_t rom3_start = lpc_get_rom3_region(&rom3_size); + + if (rom3_start && rom3_size) { + /* The flash is now no longer cacheable. Reset to WP for performance. */ + rom3_size = 1 << log2_ceil(rom3_size); + var_mtrr_set(&mtrr_ctx.ctx, rom3_start, rom3_size, MTRR_TYPE_WRPROT); + } + } + commit_mtrr_setup(&mtrr_ctx.ctx); /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ diff --git a/src/soc/amd/common/block/cpu/noncar/mpinit.c b/src/soc/amd/common/block/cpu/noncar/mpinit.c index 002c505..00b8a207 100644 --- a/src/soc/amd/common/block/cpu/noncar/mpinit.c +++ b/src/soc/amd/common/block/cpu/noncar/mpinit.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <amdblocks/iomap.h> +#include <amdblocks/lpc.h> #include <console/console.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> @@ -20,6 +21,17 @@ mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE, FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3)) { + size_t rom3_size = 0; + uint64_t rom3_start = lpc_get_rom3_region(&rom3_size); + + if (rom3_start && rom3_size) { + /* The flash is now no longer cacheable. Reset to WP for performance. */ + rom3_size = 1 << log2_ceil(rom3_size); + mtrr_use_temp_range(rom3_start, rom3_size, MTRR_TYPE_WRPROT); + } + } + /* SMMINFO only needs to be set up when booting from S5 */ if (!acpi_is_wakeup_s3()) apm_control(APM_CNT_SMMINFO); -- To view, visit https://review.coreboot.org/c/coreboot/+/86620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2df51ee3f492e5a80f5ee2676196830045dcdeb3 Gerrit-Change-Number: 86620 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/amd/common/block: Enable MMCONF first
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

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[S] Change in coreboot[main]: soc/amd/common: Always use genoa SPI MMAP driver
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86618?usp=email ) Change subject: soc/amd/common: Always use genoa SPI MMAP driver ...................................................................... soc/amd/common: Always use genoa SPI MMAP driver Currently the generic x86 SPI flash mmap driver is being when not using DMA and when not on GENOA. It only works for ROM_SIZE of 16 MiB or less and prevent boot when the ROM is bigger. Use the genoa_poc SPI MMAP driver on all platforms by default as it allows to use a ROM_SIZE greater than 16MiB. The newly introduced Kconfig SOC_AMD_COMMON_BLOCK_SPI_MMAP is used for all platforms when the SPI DMA driver is not in use. This doesn't allow to access the whole SPI flash using the ROM2 MMIO window, but it no longer prevents boot when the mainboard specifies the correct SPI flash size in Kconfig. TEST: Booted an AMD/birman+ with 64MiB ROM specified in Kconfig. Change-Id: I39e33c71d27179212ddb1f5bcca4c5d4a39d47e4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/Makefile.mk R src/soc/amd/common/block/spi/mmap_boot.c M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/genoa_poc/Makefile.mk 5 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/86618/1 diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index e5f6857..6f76650 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -16,6 +16,14 @@ help Select this option to keep the 4 DWORD burst support enabled. +config SOC_AMD_COMMON_BLOCK_SPI_MMAP + dev_bool y + select X86_CUSTOM_BOOTMEDIA + depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + help + Select this option to use a SPI flash driver that supports bigger than + 16 MiB ROMs. + config EFS_SPI_READ_MODE int range 0 7 diff --git a/src/soc/amd/common/block/spi/Makefile.mk b/src/soc/amd/common/block/spi/Makefile.mk index 55ca308..faa31bb 100644 --- a/src/soc/amd/common/block/spi/Makefile.mk +++ b/src/soc/amd/common/block/spi/Makefile.mk @@ -1,6 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y) +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP) += mmap_boot.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP) += mmap_boot.c + bootblock-y += fch_spi_ctrl.c romstage-y += fch_spi_ctrl.c verstage-y += fch_spi_ctrl.c diff --git a/src/soc/amd/genoa_poc/mmap_boot.c b/src/soc/amd/common/block/spi/mmap_boot.c similarity index 100% rename from src/soc/amd/genoa_poc/mmap_boot.c rename to src/soc/amd/common/block/spi/mmap_boot.c diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig index 25dd914..3e7246b 100644 --- a/src/soc/amd/genoa_poc/Kconfig +++ b/src/soc/amd/genoa_poc/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY + select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_UART @@ -49,7 +50,6 @@ select SOC_AMD_OPENSIL select SOC_AMD_OPENSIL_GENOA_POC select OPENSIL_DRIVER - select X86_CUSTOM_BOOTMEDIA config USE_X86_64_SUPPORT default y diff --git a/src/soc/amd/genoa_poc/Makefile.mk b/src/soc/amd/genoa_poc/Makefile.mk index bde8b18..73f10a8 100644 --- a/src/soc/amd/genoa_poc/Makefile.mk +++ b/src/soc/amd/genoa_poc/Makefile.mk @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_GENOA_POC),y) -all-y += mmap_boot.c all-y += reset.c all-y += config.c all-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/86618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e33c71d27179212ddb1f5bcca4c5d4a39d47e4 Gerrit-Change-Number: 86618 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/amd/common/block/lpc: Limit ROM2 to 16MiB
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86582?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/common/block/lpc: Limit ROM2 to 16MiB ...................................................................... soc/amd/common/block/lpc: Limit ROM2 to 16MiB Don't map more than 16MiB when the SPI ROM size is bigger than 16MiB. Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/lpc/lpc_util.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/86582/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89 Gerrit-Change-Number: 86582 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86583?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions ...................................................................... soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions Add functions to return the position and size of the ROM2 and ROM3 MMIO window that mmap the SPI flash. TEST: Verified that both functions return sane values. Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86583/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a Gerrit-Change-Number: 86583 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/common/block/lpc: Use ROM3 window if possible
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86584?usp=email to look at the new patch set (#2). Change subject: soc/amd/common/block/lpc: Use ROM3 window if possible ...................................................................... soc/amd/common/block/lpc: Use ROM3 window if possible On x86_64 use the ROM3 window to access the SPI flash. Use the same mechanism as on Intel, where the lower 16Mbyte are mapped using ROM2 window and the upper pages are mapped using the ROM3 window. By default the ROM3 window resides in high MMIO and thus needs 1024GiB of the address space to be identity mapped in the page tables. On x86_32 still only 16 MiB of the SPI flash can be mapped using the ROM2 MMIO space. This allows legacy 32-bit code to work on mappings in the lower 16MiB of the flash chip. Introduces new messages in coreboot log: [INFO ] ROM2 Decode Window: SPI flash base=0x0, Host base=0xff000000, Size=0x1000000 [INFO ] ROM3 Decode Window: SPI flash base=0x1000000, Host base=0xfd01000000, Size=0x3000000 TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64 on amd/birman+. Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/Makefile.mk A src/soc/amd/common/block/spi/mmap_boot_rom3.c M src/soc/amd/glinda/Kconfig 4 files changed, 187 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86584/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Gerrit-Change-Number: 86584 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: device/dram/ddr5: Add 7500 MT/s support
by Andy Ebrahiem (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Maximilian Brune, Paul Menzel. Andy Ebrahiem has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86543?usp=email ) Change subject: device/dram/ddr5: Add 7500 MT/s support ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d Gerrit-Change-Number: 86543 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 13:25:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/dram/ddr5: Add 7500 MT/s support
by Alicja Michalska (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Maximilian Brune, Paul Menzel. Alicja Michalska has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86543?usp=email ) Change subject: device/dram/ddr5: Add 7500 MT/s support ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d Gerrit-Change-Number: 86543 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 13:17:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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