coreboot-gerrit February 2025

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[S] Change in blobs[main]: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0
by Jarried Lin (Code Review) 27 Feb '25

27 Feb '25

Jarried Lin has uploaded a new patch set (#3). ( https://review.coreboot.org/c/blobs/+/86614?usp=email ) Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0 ...................................................................... soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0 Update mtk_fsp_ramstage.elf includes: - Add read and write permission of USB register for SSPM. - Add read and write permission of VLP register for SSPM. TEST=Build pass BUG=b:361690180,b:394704589 Change-Id: I0df03cdded80449a6e64ea88e3d1f93deb84eec7 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/mtk_fsp_ramstage.elf M soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 M soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt 3 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/14/86614/3 -- To view, visit https://review.coreboot.org/c/blobs/+/86614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I0df03cdded80449a6e64ea88e3d1f93deb84eec7 Gerrit-Change-Number: 86614 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/amd/common: Support sbin ucode files
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, Maximilian Brune, Raul Rangel. Patrick Rudolph has posted comments on this change by Fred Reitberger. ( https://review.coreboot.org/c/coreboot/+/68122?usp=email ) Change subject: soc/amd/common: Support sbin ucode files ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae Gerrit-Change-Number: 68122 Gerrit-PatchSet: 10 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 08:27:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in blobs[main]: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0
by Jarried Lin (Code Review) 27 Feb '25

27 Feb '25

Jarried Lin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/blobs/+/86614?usp=email ) Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0 ...................................................................... soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0 Update mtk_fsp_ramstage.elf includes: - Add read and write permission of USB register for SSPM. - Add read and write permission of VLP register for SSPM. TEST=Build pass BUG=b:317009620 Change-Id: I0df03cdded80449a6e64ea88e3d1f93deb84eec7 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/mtk_fsp_ramstage.elf M soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 M soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt 3 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/14/86614/2 -- To view, visit https://review.coreboot.org/c/blobs/+/86614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I0df03cdded80449a6e64ea88e3d1f93deb84eec7 Gerrit-Change-Number: 86614 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0
by Jarried Lin (Code Review) 27 Feb '25

27 Feb '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/86614?usp=email ) Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0 ...................................................................... soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.45.0 Update mtk_fsp_ramstage.elf includes: - Add read and write permission of USB register for SSPM. - Add read and write permission of VLP register for SSPM. TEST=Build pass BUG=b:317009620 Change-Id: I0df03cdded80449a6e64ea88e3d1f93deb84eec7 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/mtk_fsp_ramstage.elf M soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 M soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt 3 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/14/86614/1 diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf index e363b3b..e28a3a3 100644 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf Binary files differ diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 index 2fac575..b338649 100644 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 @@ -1 +1 @@ -d003c56a9cb53d8d3e09bf6cc6881520 *mtk_fsp_ramstage.elf +496b72aa197b3e68242220c1adf776a0 *mtk_fsp_ramstage.elf diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt b/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt index 579d8cb..4b14597 100644 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt @@ -1,3 +1,12 @@ +# 16174.45.0 + +1. An official build from ChromeOS version 16174.45.0. + +2. Included changes: + +- CL:*8059008 mt8196: Add read and write permission of VLP register for SSPM +- CL:*8058690 mt8196: Add read and write permission of USB register for SSPM + # 16174.22.0 1. An official build from ChromeOS version 16174.22.0. -- To view, visit https://review.coreboot.org/c/blobs/+/86614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I0df03cdded80449a6e64ea88e3d1f93deb84eec7 Gerrit-Change-Number: 86614 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization
by John Su (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86514?usp=email to look at the new patch set (#8). Change subject: mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization ...................................................................... mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization The previous approach would increase the delay time by 50 ms. So move WWAN power sequence to GPIO control to reduce boot time caused by WWAN initialization. Additionally, add a 150ms delay to T0_OFF_MS before powering off the WWAN. This ensures that the WWAN Power OFF Sequence operates correctly during a reboot. BUG=b:383212261 BRANCH=firmware-trulo-15217.771.B TEST=Confirm the measured WWAN power sequence Change-Id: Ie01019eca7eaa4bbb34dd80aeb65b9b6b08587fd Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/gpio.c M src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h M src/mainboard/google/brya/variants/uldrenite/variant.c M src/mainboard/google/brya/wwan_power.asl 4 files changed, 10 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/86514/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/86514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie01019eca7eaa4bbb34dd80aeb65b9b6b08587fd Gerrit-Change-Number: 86514 Gerrit-PatchSet: 8 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Add Fn key scancode
by Subrata Banik (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Tongtong Pan, Weimin Wu. Subrata Banik has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/86613?usp=email ) Change subject: mb/google/fatcat/var/felino: Add Fn key scancode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I297cc3dea577acff6c85804ba1f7e5778fc63736 Gerrit-Change-Number: 86613 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 07:49:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: fatcat: Add 64M fmd file
by Subrata Banik (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Tongtong Pan. Subrata Banik has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/86612?usp=email ) Change subject: fatcat: Add 64M fmd file ...................................................................... Patch Set 1: Code-Review-2 (1 comment) Patchset: PS1: As mentioned earlier, you may not need 64MB flash layout as Intel SoC is not 64MB memory mapped. please use Kconfig that would allow you to create a 64MB image where the upper bank is padded. example: https://review.coreboot.org/c/coreboot/+/66828 -- To view, visit https://review.coreboot.org/c/coreboot/+/86612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7793fbf4ece3a6c1d3ac04f89c69f956402bba10 Gerrit-Change-Number: 86612 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 07:49:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Add Fn key scancode
by Tongtong Pan (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86613?usp=email ) Change subject: mb/google/fatcat/var/felino: Add Fn key scancode ...................................................................... mb/google/fatcat/var/felino: Add Fn key scancode The Fn key on felino emits a scancode of 94 (0x5e). BUG=b:395822961 TEST=Flash Felino, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I297cc3dea577acff6c85804ba1f7e5778fc63736 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/86613/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 6966660..7009e27 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -79,6 +79,7 @@ config BOARD_GOOGLE_FELINO select BOARD_GOOGLE_BASEBOARD_FATCAT + select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD config BOARD_GOOGLE_FRANCKA select BOARD_GOOGLE_BASEBOARD_FATCAT -- To view, visit https://review.coreboot.org/c/coreboot/+/86613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I297cc3dea577acff6c85804ba1f7e5778fc63736 Gerrit-Change-Number: 86613 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: fatcat: Add 64M fmd file
by Tongtong Pan (Code Review) 27 Feb '25

27 Feb '25

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86612?usp=email ) Change subject: fatcat: Add 64M fmd file ...................................................................... fatcat: Add 64M fmd file add 64MiB size rom support on fatcat only add size to 64M and no others flashmap change Change-Id: I7793fbf4ece3a6c1d3ac04f89c69f956402bba10 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig A src/mainboard/google/fatcat/chromeos-64M.fmd 2 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/86612/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index e82081d..6966660 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -120,6 +120,10 @@ default 0x01 if BOARD_GOOGLE_FRANCKA default 0x01 if BOARD_GOOGLE_FELINO +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-64M.fmd" if CHROMEOS && BOARD_GOOGLE_FELINO + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS + config HAVE_SLP_S0_GATE def_bool n diff --git a/src/mainboard/google/fatcat/chromeos-64M.fmd b/src/mainboard/google/fatcat/chromeos-64M.fmd new file mode 100644 index 0000000..ba33cfd --- /dev/null +++ b/src/mainboard/google/fatcat/chromeos-64M.fmd @@ -0,0 +1,51 @@ + +FLASH 64M { + SI_ALL 8M { + SI_DESC 16K + SI_ME + } + SI_BIOS 24M { + RW_SECTION_A 8M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 2M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/86612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7793fbf4ece3a6c1d3ac04f89c69f956402bba10 Gerrit-Change-Number: 86612 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: util/cbfstool: Place XIP components and FIT at high flash addresses
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Andrey Petrov, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Ronak Kanabar, Shuo Liu, Tim Chu, Yu-Ping Wu. Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email ) Change subject: util/cbfstool: Place XIP components and FIT at high flash addresses ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86570/comment/08c1a767_1623f0f2?us… : PS8, Line 9: CACHE_ROM_SIZE > The problem is that - the cached region cannot be arbitrarily grown due to limitation of early SoC c […] I don't get the problem. Of course it can be grown arbitrarily. If you don't access the whole SPI, but only a small region (like a CBFS file), it will use the same amount in the cache as it would when the file is located in the upper part. If there's not enough cache it will evict cache lines, no matter where it's positioned in flash. I don't see the correlation to cache as ram. -- To view, visit https://review.coreboot.org/c/coreboot/+/86570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8eb469fdcd18d01652979f28049fe1ea3b59311c Gerrit-Change-Number: 86570 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 07:40:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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coreboot-gerrit February 2025