coreboot-gerrit February 2025

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[L] Change in coreboot[main]: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86377?usp=email ) Change subject: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one ...................................................................... mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one Upload the initial devicetree for meliks. All devices and port usages are the same as pirrha, just copied from pirrha's devicetree for the initial configuration except typec_aux_bias_pads[0] since pirrha had incorrect setting. About detection method of the touch screen device, the panel-built-in touch screen for meliks needs some delay after panel power up, so it may not be detected in coreboot phase. So we would keep `probed` instead of `detect` for this special touch screen device to avoid missing it in OS. BUG=b:394359785 BRANCH=nissa TEST=FW_NAME=meliks emerge-nissa coreboot Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86377 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/variants/meliks/overridetree.cb 1 file changed, 508 insertions(+), 2 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Matt DeVillier: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb index 4f2c04a..1d9ced5 100644 --- a/src/mainboard/google/brya/variants/meliks/overridetree.cb +++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb @@ -1,6 +1,512 @@ chip soc/intel/alderlake + # GPE configuration + register "pmc_gpe0_dw1" = "GPP_C" - device domain 0 on - end + # Enable MIPI DSI on DDI port A + register "ddi_portA_config" = "2" # MIPI DSI + register "sagv" = "SaGv_Enabled" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A14, .pad_auxn_dc = GPP_A15}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + .type_c = 1, + }" # USB2_C0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_11P25MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + .type_c = 1, + }" # USB2_C1 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_11P25MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # USB2_A0 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # uSD + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # UFCamera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX , + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX , + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + # VR Settings + register "domain_vr_config[VR_DOMAIN_IA]" = "{ + .vr_config_enable = 1, + .tdc_timewindow = 1000, + .ac_loadline = 500, + .dc_loadline = 500, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + }" + + register "domain_vr_config[VR_DOMAIN_GT]" = "{ + .vr_config_enable = 1, + .tdc_timewindow = 1000, + .psi1threshold = VR_CFG_AMP(13), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | WCAM | + #| I2C3 | Audio | + #| I2C4 | EMR | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .panel_orientation = LB_FB_ORIENTATION_RIGHT_UP, + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + register "options.tsr[3].desc" = ""Sub Charger"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1, + .time_window_max = 1, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""HX121A"" + register "generic.desc" = ""HX Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "200" + register "generic.reset_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 4F on end + end + end + device ref i2c2 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360000000" + register "link_freq[1]" = "180000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "true" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "btn_cfg" = "50" + register "mic_det_thr" = "200" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device ref i2c4 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM014B"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_F12)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "20" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "generic.reset_delay_ms" = "100" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 09 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ZNT0000"" + register "generic.desc" = ""Zinitix Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0xE" + device i2c 40 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "da7219" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end + device ref pcie_rp7 off end + device ref pcie_rp9 off end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 SDCard"" + register "type" = "UPC_TYPE_EXPRESSCARD" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Gerrit-Change-Number: 86377 Gerrit-PatchSet: 10 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Jayvik Desai, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik. Matt DeVillier has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/86377?usp=email ) Change subject: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one ...................................................................... Patch Set 9: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86377/comment/1308fcb7_b5de25ee?us… : PS9, Line 15: About detection method of the touch screen device, the panel-built-in : touch screen for meliks needs some delay after panel power up, so it : may not be detected in coreboot phase. So we would keep `probed` : instead of `detect` for this special touch screen device to avoid : missing it in OS. this is not a problem since there is only a single touchscreen currently, but if more are to be added and 'detect' cannot be used, please use fw_config to disambiguate between them. -- To view, visit https://review.coreboot.org/c/coreboot/+/86377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Gerrit-Change-Number: 86377 Gerrit-PatchSet: 9 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 27 Feb 2025 16:23:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/meliks: Generate SPD ID for 3 supported parts
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86375?usp=email ) Change subject: mb/google/nissa/var/meliks: Generate SPD ID for 3 supported parts ...................................................................... mb/google/nissa/var/meliks: Generate SPD ID for 3 supported parts Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. - K3KL6L60GM-MGCT (Samsung) - MT62F512M32D2DR-031 WT:B (Micron) - K3KL8L80DM-MGCU (Samsung) BUG=b:394359785 TEST=Build coreboot and verified booting to depthcharge Change-Id: Ief1272ef4cb7971c3abfe6ee982b019121f54793 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86375 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/meliks/memory/Makefile.mk M src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt 3 files changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk index eace2e4..1f7a706 100644 --- a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/meliks/memory src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = K3KL8L80DM-MGCU diff --git a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt index fa24790..5ca8b34 100644 --- a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt @@ -1 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/meliks/memory src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K3KL6L60GM-MGCT 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) +K3KL8L80DM-MGCU 2 (0010) diff --git a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt index 2499005..cb07b52 100644 --- a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt @@ -9,3 +9,6 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K3KL6L60GM-MGCT +MT62F512M32D2DR-031 WT:B +K3KL8L80DM-MGCU -- To view, visit https://review.coreboot.org/c/coreboot/+/86375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief1272ef4cb7971c3abfe6ee982b019121f54793 Gerrit-Change-Number: 86375 Gerrit-PatchSet: 9 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Enable DPTF oem_variables
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86394?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Enable DPTF oem_variables ...................................................................... mb/google/trulo/var/uldrenite: Enable DPTF oem_variables Support oem_variables and change based on EC notify event. BUG=b:394177292 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot Change-Id: Iac18cb968906a9dfe53836432ba8dbefee1dcc8e Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86394 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 2 files changed, 8 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h index 7a2a6ff..818cdef 100644 --- a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h @@ -5,4 +5,7 @@ #include <baseboard/ec.h> +/* Enable DPTF OEM variable */ +#define DPTF_ENABLE_OEM_VARIABLES + #endif diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index fdc933e..5571fe7 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -225,7 +225,11 @@ [3] = { 8, 500 } }" - device generic 0 on end + register "oem_data.oem_variables" = "{ + [0] = 0x0 + }" + + device generic 0 alias dptf_policy on end end end # DPTF device ref tcss_xhci on -- To view, visit https://review.coreboot.org/c/coreboot/+/86394?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac18cb968906a9dfe53836432ba8dbefee1dcc8e Gerrit-Change-Number: 86394 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table
by Matt DeVillier (Code Review) 27 Feb '25

27 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84872?usp=email ) Change subject: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table ...................................................................... soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table Get boot performance timestamps from CSE and inject them into CBMEM timestamp table. For Panther Lake, remove "Die Management Unit (DMU) load completed" and add "ESE completed AUnit loading" instead. 990:CSME ROM started execution 0 992:ESE completed AUnit loading 0 944:CSE sent 'Boot Stall Done' to PMC 174,000 945:CSE started to handle ICC configuration 274,000 (100,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 274,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 448,000 (174,000) 0:1st timestamp 556,874 (108,874) BUG=b:376218080 TEST=Able to see TS elapse prior to IA reset on Fatcat Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Reviewed-on: https://review.coreboot.org/c/coreboot/+/84872 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/include/intelblocks/cse_telemetry.h A src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h M src/soc/intel/pantherlake/cse_telemetry.c 4 files changed, 52 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index bfef3d5..d1548a1 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -295,6 +295,13 @@ This config will make mainboard use version 2 of the CSE timestamp definitions, it can be used for Meteor Lake M/P. +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V3 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 3 of the CSE timestamp + definitions, it can be used for Panther Lake U/H. + config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h index 291a264..66cc7f4 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h @@ -7,6 +7,8 @@ #include "cse_telemetry_v1.h" #elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2) #include "cse_telemetry_v2.h" +#elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V3) +#include "cse_telemetry_v3.h" #endif #endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h new file mode 100644 index 0000000..6dbadff --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H +#define SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H + +enum cse_boot_perf_data_v3 { + /* CSME ROM start execution */ + PERF_DATA_CSME_ROM_START = 0, + + /* 1 - 5 Reserved */ + + /* CSME RBE set "Boot Stall Done" indication to PMC */ + PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6, + + /* 7 - 14 Reserved */ + + /* CSME got ICC_CFG_START message from PMC */ + PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC = 15, + + /* 15 - 16 Reserved */ + + /* CSME set "Host Boot Prep Done" indication to PMC */ + PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 17, + + /* 18 - 32 Reserved */ + + /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ + PERF_DATA_PMC_SENT_CRDA = 33, + + /* 34 - 35 Reserved */ + + /* ESE completed AUnit loading */ + PERF_DATA_ESE_LOAD_AUNIT_COMPLETED = 36, + + /* 37 - 62 Reserved */ + + /* Timestamp when CSME responded to BupGetBootData message itself */ + PERF_DATA_CSME_GET_PERF_RESPONSE = 63, +}; + +#endif /* SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H */ diff --git a/src/soc/intel/pantherlake/cse_telemetry.c b/src/soc/intel/pantherlake/cse_telemetry.c index 6a599c9..60faeb2 100644 --- a/src/soc/intel/pantherlake/cse_telemetry.c +++ b/src/soc/intel/pantherlake/cse_telemetry.c @@ -24,6 +24,6 @@ start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); - timestamp_add(TS_ISSE_DMU_LOAD_END, - start_stamp + ts[PERF_DATA_ISSE_DMU_LOAD_COMPLETED]); + timestamp_add(TS_ESE_LOAD_AUNIT_END, + start_stamp + ts[PERF_DATA_ESE_LOAD_AUNIT_COMPLETED]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 12 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: device/dram/ddr5: Add 7500 MT/s support
by Naresh Solanki (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Maximilian Brune, Paul Menzel. Naresh Solanki has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86543?usp=email ) Change subject: device/dram/ddr5: Add 7500 MT/s support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d Gerrit-Change-Number: 86543 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 27 Feb 2025 15:20:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/common/block/lpc: Use ROM3 window if possible
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph, Paul Menzel. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86584?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/amd/common/block/lpc: Use ROM3 window if possible ...................................................................... soc/amd/common/block/lpc: Use ROM3 window if possible On x86_64 use the ROM3 window to access the SPI flash. Use the same mechanism as on Intel, where the lower 16Mbyte are mapped using ROM2 window and the upper pages are mapped using the ROM3 window. By default the ROM3 window resides in high MMIO and thus needs 1024GiB of the address space to be identity mapped in the page tables. On x86_32 still only 16 MiB of the SPI flash can be mapped using the ROM2 MMIO space. This allows legacy 32-bit code to work on mappings in the lower 16MiB of the flash chip. Introduces new messages in coreboot log: [INFO ] ROM2 Decode Window: SPI flash base=0x0, Host base=0xff000000, Size=0x1000000 [INFO ] ROM3 Decode Window: SPI flash base=0x1000000, Host base=0xfd01000000, Size=0x3000000 TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64 on amd/birman+. Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/Makefile.mk A src/soc/amd/common/block/spi/mmap_boot_rom3.c M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/glinda/Kconfig 5 files changed, 190 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86584/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Gerrit-Change-Number: 86584 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/common/block/lpc: Use ROM3 window if possible
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86584?usp=email ) Change subject: soc/amd/common/block/lpc: Use ROM3 window if possible ...................................................................... Patch Set 3: (3 comments) Patchset: PS1: > The linter found several things. Most(?) of them valid. Done Commit Message: https://review.coreboot.org/c/coreboot/+/86584/comment/37efe7a2_061af62b?us… : PS1, Line 21: > Maybe paste the new log messages. Done File src/soc/amd/common/block/lpc/mmap_boot_rom3.c: https://review.coreboot.org/c/coreboot/+/86584/comment/9e13d44f_abb809a2?us… : PS1, Line 27: (type == ROM2_DECODE_WINDOW) ? 2: 3); > > `spaces required around that ':' (ctx:VxW)` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Gerrit-Change-Number: 86584 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 14:00:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86583?usp=email ) Change subject: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions ...................................................................... Patch Set 3: (3 comments) File src/soc/amd/common/block/include/amdblocks/lpc.h: https://review.coreboot.org/c/coreboot/+/86583/comment/81bc80b5_551c22ab?us… : PS1, Line 106: ROM_ADDRESS_RANGE3_START > Shouldn't it be moved down after LPC_WIDEIO2_GENERIC_PORT to keep numerical order? Done File src/soc/amd/common/block/lpc/lpc_util.c: https://review.coreboot.org/c/coreboot/+/86583/comment/5adff3be_2478bef6?us… : PS1, Line 292: * The maxium window size is 16 MiB. > > `'maxium' may be misspelled - perhaps 'maximum'?` […] Done https://review.coreboot.org/c/coreboot/+/86583/comment/e608397c_b9982080?us… : PS1, Line 314: * Default at 0xfd00000000. The maxium window size is 64 MiB. > > `'maxium' may be misspelled - perhaps 'maximum'?` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a Gerrit-Change-Number: 86583 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Feb 2025 13:59:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions
by Patrick Rudolph (Code Review) 27 Feb '25

27 Feb '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86583?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions ...................................................................... soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions Add functions to return the position and size of the ROM2 and ROM3 MMIO window that mmap the SPI flash. TEST: Verified that both functions return sane values. Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86583/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a Gerrit-Change-Number: 86583 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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