coreboot-gerrit February 2025

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[L] Change in coreboot[main]: tree: Use true false for PcieRpLtrEnable[]
by Elyes Haouas (Code Review) 02 Feb '25

02 Feb '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86193?usp=email ) Change subject: tree: Use true false for PcieRpLtrEnable[] ...................................................................... tree: Use true false for PcieRpLtrEnable[] PcieRpLtrEnable[] is a boolean, so use true false. Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193 Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/imb-1222/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/dell/optiplex_3050/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/awasuki/overridetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/dooly/overridetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb M src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb M src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h M util/mainboard/google/puff/template/overridetree.cb 76 files changed, 243 insertions(+), 247 deletions(-) Approvals: Erik van den Bogaert: Looks good to me, but someone else must approve Sean Rhodes: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, but someone else must approve diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1de7292..d0084e7 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -94,7 +94,7 @@ register "PcieRpClkReqNumber[2]" = "0" register "PcieRpClkSrcNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" end device ref pcie_rp4 on # Wireless controller @@ -103,7 +103,7 @@ register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" end device ref pcie_rp9 on # NVMe controller @@ -112,7 +112,7 @@ register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 996bced..e3abec8 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -253,7 +253,7 @@ # dGPU; x4 register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "0" register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" @@ -262,7 +262,7 @@ # NGFF; x2 register "PcieRpEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "3" register "PcieRpMaxPayload[6]" = "RpMaxPayload_256" @@ -271,7 +271,7 @@ # LAN register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" @@ -280,7 +280,7 @@ # WLAN register "PcieRpEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" - register "PcieRpLtrEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "true" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "2" register "PcieRpMaxPayload[9]" = "RpMaxPayload_256" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index d999973..cc36ce8 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -117,7 +117,7 @@ register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "2" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "2" register "PcieRpHotPlug[4]" = "1" end @@ -127,7 +127,7 @@ # Disable CLKREQ#, since onboard LAN is always present register "PcieRpClkReqSupport[5]" = "0" register "PcieRpAdvancedErrorReporting[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on @@ -135,7 +135,7 @@ register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "3" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkSrcNumber[6]" = "3" register "PcieRpHotPlug[6]" = "1" end diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb index 4a01a5a..8edbf62 100644 --- a/src/mainboard/asrock/imb-1222/devicetree.cb +++ b/src/mainboard/asrock/imb-1222/devicetree.cb @@ -210,7 +210,7 @@ end device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4) register "PcieRpEnable[16]" = "true" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieRpSlotImplemented[16]" = "1" register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" @@ -218,14 +218,14 @@ end device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[3]" = "4" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1) register "PcieRpEnable[5]" = "true" register "PcieRpSlotImplemented[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X" @@ -233,7 +233,7 @@ device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1) register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[6]" = "6" register "PcieClkSrcClkReq[6]" = "6" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/B 3042/3052 (M2_KEYB1)" "SlotDataBusWidth1X" diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 48a2bbc..749488f 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -113,7 +113,7 @@ device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader register "PcieRpEnable[5]" = "true" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" end @@ -122,7 +122,7 @@ device pci 00.0 on end end register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" @@ -130,7 +130,7 @@ end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[8]" = "1" @@ -138,7 +138,7 @@ end device ref pcie_rp13 on register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[12]" = "1" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 749cb7c..15e7064 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -71,7 +71,7 @@ register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" register "PcieRpHotPlug[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" end device ref pcie_rp5 on @@ -80,7 +80,7 @@ register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" end device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN @@ -88,7 +88,7 @@ register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end device ref pcie_rp9 on @@ -97,7 +97,7 @@ register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb index 039709a..da11085 100644 --- a/src/mainboard/dell/optiplex_3050/devicetree.cb +++ b/src/mainboard/dell/optiplex_3050/devicetree.cb @@ -43,7 +43,7 @@ register "PcieRpClkReqSupport[20]" = "1" register "PcieRpClkReqNumber[20]" = "3" register "PcieRpAdvancedErrorReporting[20]" = "1" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieRpClkSrcNumber[20]" = "3" register "PcieRpHotPlug[20]" = "1" end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 64c9760..d87db24 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -160,7 +160,7 @@ register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "0" register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieRpAdvancedErrorReporting[2]" = "1" register "pcie_rp_aspm[2]" = "AspmDisabled" end @@ -170,7 +170,7 @@ register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "0" register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" register "pcie_rp_aspm[5]" = "AspmDisabled" end @@ -181,7 +181,7 @@ register "PcieRpClkReqSupport[8]" = "0" register "PcieRpHotPlug[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "pcie_rp_aspm[8]" = "AspmDisabled" end diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb index bf45bcf..76b7033 100644 --- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -1,6 +1,6 @@ chip soc/intel/jasperlake # PCIe RP LTR configuration - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # USB Port Configuration register "usb2_ports[1]" = "USB2_PORT_EMPTY" diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 791f697..9173036 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -8,7 +8,7 @@ chip soc/intel/jasperlake # PCIe RP LTR configuration - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 3e1ccab..0f72b08 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -194,13 +194,13 @@ # PCIe port 9 for Card Reader register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 8187868..0189e62 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -340,7 +340,7 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpHotPlug[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic @@ -353,7 +353,7 @@ register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "4" end device ref uart0 on end diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 7424247..145b093 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -293,7 +293,7 @@ register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieRpClkSrcNumber[2]" = "0" chip drivers/net register "customized_leds" = "0x0fa5" @@ -308,7 +308,7 @@ register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "5" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" register "PcieRpClkSrcNumber[3]" = "5" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" @@ -321,7 +321,7 @@ register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "1" end device ref pcie_rp9 on @@ -330,7 +330,7 @@ register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "2" chip drivers/net register "customized_leds" = "0x0fa5" @@ -343,7 +343,7 @@ register "PcieRpClkReqSupport[10]" = "1" register "PcieRpClkReqNumber[10]" = "2" register "PcieRpAdvancedErrorReporting[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieRpClkSrcNumber[10]" = "2" end device ref pcie_rp12 on @@ -351,7 +351,7 @@ register "PcieRpClkReqSupport[11]" = "1" register "PcieRpClkReqNumber[11]" = "2" register "PcieRpAdvancedErrorReporting[11]" = "1" - register "PcieRpLtrEnable[11]" = "1" + register "PcieRpLtrEnable[11]" = "true" register "PcieRpClkSrcNumber[11]" = "2" end device ref uart0 on end diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 421ebc1..7b6de18 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -120,7 +120,7 @@ register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "4" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkSrcNumber[6]" = "4" end device ref pcie_rp8 on @@ -129,7 +129,7 @@ register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "2" register "PcieRpAdvancedErrorReporting[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieRpClkSrcNumber[7]" = "2" end device ref pcie_rp9 on @@ -137,7 +137,7 @@ register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "0" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "2" end device ref pcie_rp10 off diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 54dc960..6b3eff6 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -163,7 +163,7 @@ # Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -171,7 +171,7 @@ # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 8e7c0b0..7bc453d 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -21,7 +21,7 @@ # Enable Root port 9(x2) for NVMe. register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -29,7 +29,7 @@ # Enable Root port 11(x2) for NVMe. register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # RP 11 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "10" # ClkReq-to-ClkSrc mapping for CLK SRC 2 diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 27d642d..985c1af 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -72,14 +72,14 @@ # PCIe port 7 for M.2 E-key WLAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # RP 7 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" # Enable Root port 13 (x4) for dGPU register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" # RP 13 uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "12" # ClkReq-to-ClkSrc mapping for CLK SRC 5 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index e143327..159acb3 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -315,7 +315,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW1_07" # GPP_B7 device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4f5e543..8fa6a14 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -327,7 +327,7 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d9238b8..3a5806b 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -371,7 +371,7 @@ register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 device pci 00.0 on end @@ -384,7 +384,7 @@ register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" end device ref pcie_rp9 on # x2 @@ -393,7 +393,7 @@ register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref uart0 on end device ref gspi0 on diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b3eabfd..c0c9861 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -366,7 +366,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index c1c0b20..39b4e74 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -330,7 +330,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW2_01" device pci 00.0 on end @@ -343,7 +343,7 @@ register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref gspi0 on chip drivers/spi/acpi diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 0c40c92..5cc1be7 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -319,7 +319,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" # GPP_B0 device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 676b331..de3b2ab 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -309,7 +309,7 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 199a63c..9c9880f 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -185,10 +185,10 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 6482682..de4631a 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -163,7 +163,7 @@ # Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -171,7 +171,7 @@ # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index 81fac90..a9a9b8e 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -174,7 +174,7 @@ # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index 2db0b63..408a00b 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -246,10 +246,10 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 0bd90ee..eac754e 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -254,10 +254,10 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index ec19352..19e42ba 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -178,21 +178,21 @@ # PCIe root port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5" # PCIe root port 9 for SSD (PCIe Lanes 11, 12) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" @@ -202,21 +202,21 @@ # PCIe root port 11 TPU1 register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4" # PCIe root port 12 TPU0 register "PcieRpEnable[11]" = "true" - register "PcieRpLtrEnable[11]" = "1" + register "PcieRpLtrEnable[11]" = "true" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2" # PCIe port 13 for i350 NIC (x4) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" # RP 13 does not use a source clock request line diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index 88f98ef..f0bad9d 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -246,10 +246,10 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index 6e6a869..9b6f020 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -178,21 +178,21 @@ # PCIe root port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5" # PCIe root port 9 for SSD (PCIe Lanes 11, 12) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" @@ -202,21 +202,21 @@ # PCIe root port 11 TPU1 register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4" # PCIe root port 12 TPU0 register "PcieRpEnable[11]" = "true" - register "PcieRpLtrEnable[11]" = "1" + register "PcieRpLtrEnable[11]" = "true" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2" # PCIe port 13 for i350 NIC (x4) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" # RP 13 does not use a source clock request line diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 7e43c2b..61f73a0 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -169,10 +169,10 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index 859da99..4638eee 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -179,10 +179,10 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 7125c40..66bf31f 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -185,21 +185,21 @@ # PCIe root port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # Uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" # PCIe root port 9 for SSD (PCIe Lanes 9-12) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" @@ -211,14 +211,14 @@ # PCIe root port 13 TPU0 register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" # RP 13 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" # PCIe root port 14 TPU1 register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" # RP 14 uses CLK SRC 4 register "PcieClkSrcUsage[4]" = "13" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index df25e86..a373bea7 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -180,10 +180,10 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index e09e861..b521763 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -188,13 +188,13 @@ # PCIe port 11 for card reader register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e0f052f..d47e183 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -183,7 +183,7 @@ # PCIe port 8 for Card Reader register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4" @@ -199,7 +199,7 @@ # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ac55ac0..8110bb7 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -425,14 +425,14 @@ end device ref pcie_rp7 on # WLAN PCIE 7 using clk 1 - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[6]" = "1" end device ref pcie_rp8 on # SD Card PCIE 8 using clk 3 - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieRpHotPlug[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" @@ -464,14 +464,14 @@ end device ref pcie_rp9 on # NVMe PCIE 9 using clk 0 - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[8]" = "1" end device ref pcie_rp11 on # Optane PCIE 11 using clk 0 - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "HybridStorageMode" = "0" register "PcieRpSlotImplemented[10]" = "1" end diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 017a35d..4688c23 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -268,7 +268,7 @@ end device ref pcie_rp5 on # EMMC PCIE 5 using clk 5 - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 8267867..abf2345 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -269,7 +269,7 @@ end device ref pcie_rp5 on # EMMC PCIE 5 using clk 5 - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index afc67c6..abcc64a 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -90,13 +90,13 @@ device ref pcie_rp7 off # Disable WLAN PCIE 7 - register "PcieRpLtrEnable[6]" = "0" + register "PcieRpLtrEnable[6]" = "false" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" register "PcieRpSlotImplemented[6]" = "1" end device ref pcie_rp8 off # Disable SD Card PCIE 8 - register "PcieRpLtrEnable[7]" = "0" + register "PcieRpLtrEnable[7]" = "false" register "PcieRpHotPlug[7]" = "0" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" # override-devicetree rules say it's only diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 3b07bf7..afb564e 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -65,7 +65,7 @@ device ref pcie_rp5 on # IT8893E PCI Bridge register "PcieRpEnable[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpClkSrcNumber[4]" = "11" end @@ -73,14 +73,14 @@ # PCIe x1 slot register "PcieRpEnable[5]" = "1" register "PcieRpHotPlug[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" register "PcieRpClkSrcNumber[5]" = "6" end device ref pcie_rp7 on # RTL8111 GbE NIC register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpClkSrcNumber[6]" = "10" end @@ -88,7 +88,7 @@ # M.2 2230 slot register "PcieRpEnable[7]" = "1" register "PcieRpHotPlug[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieRpAdvancedErrorReporting[7]" = "1" register "PcieRpClkSrcNumber[7]" = "12" end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 70adca6..b9af2c5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -243,13 +243,13 @@ device ref pcie_rp2 off end device ref pcie_rp3 on register "PcieRpSlotImplemented[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "0x2" register "PcieClkSrcClkReq[1]" = "1" end device ref pcie_rp4 on register "PcieRpSlotImplemented[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcClkReq[2]" = "2" chip soc/intel/common/block/pcie/rtd3 @@ -264,14 +264,14 @@ device ref pcie_rp8 off end device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "0x8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 off end device ref pcie_rp11 on register "PcieRpSlotImplemented[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" end device ref pcie_rp12 off end device ref uart0 off end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d1deea3..7e00917 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -245,14 +245,14 @@ device ref pcie_rp2 off end device ref pcie_rp3 on register "PcieRpSlotImplemented[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "0x2" register "PcieClkSrcClkReq[1]" = "1" end device ref pcie_rp4 on register "PcieRpSlotImplemented[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcClkReq[2]" = "2" chip soc/intel/common/block/pcie/rtd3 @@ -267,14 +267,14 @@ device ref pcie_rp8 off end device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "0x8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 off end device ref pcie_rp11 on register "PcieRpSlotImplemented[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" end device ref pcie_rp12 off end device ref uart0 off end diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index b923ec7..c2ac2ba 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -165,7 +165,7 @@ register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "1" register "PcieRpAdvancedErrorReporting[16]" = "1" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieRpClkSrcNumber[16]" = "7" register "PcieRpHotPlug[16]" = "1" end @@ -174,7 +174,7 @@ register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "11" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkSrcNumber[6]" = "1" register "PcieRpHotPlug[6]" = "1" chip drivers/wifi/generic diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index e097123..cb5f211 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -172,7 +172,7 @@ device ref pcie_rp21 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieRpSlotImplemented[20]" = "1" register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" register "PcieRpAdvancedErrorReporting[20]" = "1" @@ -181,7 +181,7 @@ device ref pcie_rp1 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" register "PcieRpEnable[0]" = "true" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpSlotImplemented[0]" = "1" register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -189,28 +189,28 @@ end device ref pcie_rp5 on # PHY 3 register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" device pci 00.0 on smbios_dev_info 3 end end device ref pcie_rp6 on # PHY 4 register "PcieRpEnable[5]" = "true" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" device pci 00.0 on smbios_dev_info 4 end end device ref pcie_rp7 on # PHY 2 register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" device pci 00.0 on smbios_dev_info 2 end end device ref pcie_rp8 on # PHY 1 register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" device pci 00.0 on smbios_dev_info 1 end @@ -218,12 +218,12 @@ device ref pcie_rp9 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpSlotImplemented[8]" = "1" end device ref pcie_rp14 on # PHY 0 register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" device pci 00.0 on smbios_dev_info 0 end @@ -233,13 +233,13 @@ device pci 00.0 on end # Aspeed 2500 VGA end register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieRpSlotImplemented[14]" = "1" end device ref pcie_rp16 on # M.2 E/CNVi # Disabled when CNVi is present register "PcieRpEnable[15]" = "true" - register "PcieRpLtrEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "true" register "PcieRpSlotImplemented[15]" = "1" end device ref uart0 on end diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index f2c75f3..7143aad 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -72,14 +72,14 @@ register "PcieRpAdvancedErrorReporting[12]" = "1" # Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13 - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieRpLtrEnable[6]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieRpLtrEnable[9]" = "1" - register "PcieRpLtrEnable[11]" = "1" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[4]" = "true" + register "PcieRpLtrEnable[5]" = "true" + register "PcieRpLtrEnable[6]" = "true" + register "PcieRpLtrEnable[7]" = "true" + register "PcieRpLtrEnable[8]" = "true" + register "PcieRpLtrEnable[9]" = "true" + register "PcieRpLtrEnable[11]" = "true" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index ef1c1a9..af7fd5b 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -144,49 +144,49 @@ # LAN register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkSrcNumber[0]" = "0" end device ref pcie_rp2 on # LAN register "PcieRpEnable[1]" = "true" register "PcieRpAdvancedErrorReporting[1]" = "1" - register "PcieRpLtrEnable[1]" = "1" + register "PcieRpLtrEnable[1]" = "true" register "PcieRpClkSrcNumber[1]" = "1" end device ref pcie_rp3 on # LAN register "PcieRpEnable[2]" = "true" register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieRpClkSrcNumber[2]" = "2" end device ref pcie_rp4 on # LAN register "PcieRpEnable[3]" = "true" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" register "PcieRpClkSrcNumber[3]" = "3" end device ref pcie_rp5 on # LAN register "PcieRpEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "4" end device ref pcie_rp6 on # LAN register "PcieRpEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieRpClkSrcNumber[5]" = "5" end device ref pcie_rp9 on # mPCIe WIFI register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "5" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "0" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index 9bd8e4f..e9a4d88 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -127,7 +127,7 @@ device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN) register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpHotPlug[6]" = "1" register "PcieClkSrcUsage[2]" = "6" register "PcieClkSrcClkReq[2]" = "2" @@ -142,7 +142,7 @@ device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe) register "PcieRpEnable[8]" = "true" register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" @@ -150,7 +150,7 @@ device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe) register "PcieRpEnable[12]" = "true" register "PcieRpSlotImplemented[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[1]" = "12" register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index a043006..f4455b7 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -119,7 +119,7 @@ device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN) register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" @@ -133,7 +133,7 @@ device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[1]" = "12" register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index e10e41a..cd40993 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -211,20 +211,20 @@ device ref pcie_rp21 on register "PcieRpSlotImplemented[20]" = "1" register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[10]" = "20" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X" end device ref pcie_rp1 on register "PcieRpSlotImplemented[0]" = "1" register "PcieRpEnable[0]" = "true" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieClkSrcUsage[1]" = "0x80" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end device ref pcie_rp9 on # GbE #1 register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[14]" = "8" # Type indexes are needed for systemd to use "onboard" names by default # (eno0, eno1). Otherwise it uses "slot" names that can change if any @@ -237,12 +237,12 @@ end device ref pcie_rp10 on # BMC video register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "true" register "PcieClkSrcUsage[8]" = "9" end device ref pcie_rp11 on # GbE #2 register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieClkSrcUsage[11]" = "10" device pci 00.0 on smbios_dev_info 2 diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 00b5ea6..05c619a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -158,16 +158,16 @@ device ref pcie_rp1 on end device ref pcie_rp3 on register "PcieRpEnable[2]" = "true" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" end device ref pcie_rp5 on register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index efabe95..9ab9179 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -159,7 +159,7 @@ device ref pcie_rp9 on # SSD x4 register "PcieRpSlotImplemented[8]" = "1" register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[1]" = "0x08" register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index a9e85ce..ed61df8 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -88,7 +88,7 @@ register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" chip drivers/wifi/generic register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" @@ -100,7 +100,7 @@ register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "0" register "PcieRpClkSrcNumber[8]" = "0" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device ref uart0 on end diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index b53a01f..d7505ef 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -45,20 +45,20 @@ device ref pcie_rp1 on # Slot JPCIE4 register "PcieRpEnable[0]" = "true" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp5 on # Slot JPCIE5 register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" device pci 00.0 on # GbE 1 subsystemid 0x15d9 0x1533 @@ -66,7 +66,7 @@ end device ref pcie_rp10 on register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" device pci 00.0 on # GbE 2 subsystemid 0x15d9 0x1533 @@ -74,7 +74,7 @@ end device ref pcie_rp11 on register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieRpAdvancedErrorReporting[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index f951aae..850d485 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -99,7 +99,7 @@ device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 0 (Thunderbolt) register "PcieRpEnable[16]" = "true" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" register "PcieClkSrcClkReq[0]" = "0" @@ -107,7 +107,7 @@ device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 10 (SSD2) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[10]" = "20" register "PcieClkSrcClkReq[10]" = "10" register "PcieRpSlotImplemented[20]" = "1" @@ -115,7 +115,7 @@ device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 9 (SSD1) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" register "PcieRpSlotImplemented[8]" = "1" @@ -123,7 +123,7 @@ device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 5 (GLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[5]" = "13" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[13]" = "1" @@ -131,7 +131,7 @@ device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 7 (Card Reader) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[7]" = "14" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[14]" = "1" @@ -139,7 +139,7 @@ device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 6 (WLAN) register "PcieRpEnable[15]" = "true" - register "PcieRpLtrEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "true" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" register "PcieRpSlotImplemented[15]" = "1" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index afdc264..36a9b90 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -114,21 +114,21 @@ device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 14 (SSD2) register "PcieRpEnable[16]" = "true" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieClkSrcUsage[14]" = "16" register "PcieClkSrcClkReq[14]" = "14" end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 15 (SSD3) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[15]" = "20" register "PcieClkSrcClkReq[15]" = "15" end device ref pcie_rp1 on # PCI Express root port #1 x4, Clock 6 (Thunderbolt) register "PcieRpEnable[0]" = "true" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpHotPlug[0]" = "1" register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED register "PcieClkSrcClkReq[6]" = "6" @@ -136,35 +136,35 @@ device ref pcie_rp5 on # PCI Express root port #5 x4, Clock 10 (USB 3.2) register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[10]" = "4" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 8 (SSD) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[8]" = "8" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp13 on # PCI Express root port #13 x1, Clock 0 (WLAN) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[0]" = "12" register "PcieClkSrcClkReq[0]" = "0" end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 1 (GLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[1]" = "13" register "PcieClkSrcClkReq[1]" = "1" end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 4 (Card Reader) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[4]" = "14" register "PcieClkSrcClkReq[4]" = "4" end diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index 630d669..5e70ec0 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -41,7 +41,7 @@ device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" @@ -49,21 +49,21 @@ device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "0" + register "PcieRpLtrEnable[9]" = "false" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" end diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index 132272d..fb902bb 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -34,7 +34,7 @@ device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" @@ -42,21 +42,21 @@ device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "0" + register "PcieRpLtrEnable[9]" = "false" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" end diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb index 7d2beab..2010b82 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -42,7 +42,7 @@ device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader register "PcieRpEnable[5]" = "true" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" register "PcieRpSlotImplemented[5]" = "1" @@ -50,7 +50,7 @@ device ref pcie_rp8 on device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" @@ -62,7 +62,7 @@ device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[8]" = "1" @@ -71,7 +71,7 @@ device ref pcie_rp13 on device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[12]" = "1" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index d0a79806..1c5aed6 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -97,7 +97,7 @@ device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" register "PcieRpSlotImplemented[20]" = "1" @@ -105,7 +105,7 @@ device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 10 (SSD) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" register "PcieRpSlotImplemented[8]" = "1" @@ -113,7 +113,7 @@ device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 6 (WLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[6]" = "13" register "PcieClkSrcClkReq[6]" = "6" register "PcieRpSlotImplemented[13]" = "1" @@ -121,7 +121,7 @@ device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 5 (LAN) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[5]" = "14" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[14]" = "1" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 291cb45..10a5750 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -138,7 +138,7 @@ register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpHotPlug[0]" = "1" end device ref pcie_rp5 on @@ -148,7 +148,7 @@ register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" end device ref pcie_rp6 on # Root port #6 x1 (WLAN) @@ -157,7 +157,7 @@ register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" register "PcieRpAdvancedErrorReporting[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" end device ref pcie_rp9 on # Root port #9 x4 (NVMe) @@ -166,7 +166,7 @@ register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 6dd4eb3..a465e56 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -110,35 +110,35 @@ device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 12 (SSD) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 13 (WLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[13]" = "13" register "PcieClkSrcClkReq[13]" = "13" end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 14 (GLAN) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[14]" = "14" register "PcieClkSrcClkReq[14]" = "14" end device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 15 (Card Reader) register "PcieRpEnable[15]" = "true" - register "PcieRpLtrEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "true" register "PcieClkSrcUsage[15]" = "15" register "PcieClkSrcClkReq[15]" = "15" end diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index bb49da9..b1a0097 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -107,7 +107,7 @@ device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 0 (Thunderbolt) register "PcieRpEnable[16]" = "true" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" register "PcieClkSrcClkReq[0]" = "0" @@ -116,7 +116,7 @@ device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" register "PcieRpSlotImplemented[20]" = "1" @@ -124,7 +124,7 @@ device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 12 (SSD1) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" register "PcieRpSlotImplemented[8]" = "1" @@ -132,7 +132,7 @@ device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 7 (GLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[7]" = "13" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[13]" = "1" @@ -140,7 +140,7 @@ device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 9 (Card Reader) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[9]" = "14" register "PcieClkSrcClkReq[9]" = "9" register "PcieRpSlotImplemented[14]" = "1" @@ -148,7 +148,7 @@ device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 6 (WLAN) register "PcieRpEnable[15]" = "true" - register "PcieRpLtrEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "true" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" register "PcieRpSlotImplemented[15]" = "1" diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index 6ac474d..6fa540c 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -55,26 +55,26 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 5 (GLAN) - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[5]" = "4" register "PcieClkSrcClkReq[5]" = "5" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 7 (CARD) - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[7]" = "6" register "PcieClkSrcClkReq[7]" = "7" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 8 (WLAN) - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[8]" = "7" register "PcieClkSrcClkReq[8]" = "8" register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 9 (SSD1) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index b4b62fa..1eab4c9 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -55,26 +55,26 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 8 (GLAN) - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" #register "PcieClkSrcUsage[8]" = "4" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 3 (CARD) - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 2 (WLAN) - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 10 (SSD2) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index 0967154..de1e445 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -64,26 +64,26 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 8 (GLAN) - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[8]" = "4" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 10 (CARD) - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[10]" = "5" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 2 (WLAN) - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 6 (SSD2) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[6]" = "8" register "PcieClkSrcClkReq[6]" = "6" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb index b263c5a..768f1c7 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb @@ -139,17 +139,17 @@ register "SataSalpSupport" = "1" end device ref pcie_rp1 on - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 3 (GLAN) - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" chip soc/intel/common/block/pcie/rtd3 @@ -161,14 +161,14 @@ end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 1 (WLAN) - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[1]" = "7" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 4 (SSD0) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 7cfc62b..8683bb8 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -143,7 +143,7 @@ end device ref pcie_rp5 on # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[2]" = "4" register "PcieClkSrcClkReq[2]" = "2" chip soc/intel/common/block/pcie/rtd3 @@ -159,13 +159,13 @@ end device ref pcie_rp9 on # PCIe root port #9 x1, Clock 3 (CARD) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCIe root port #10 x1, Clock 4 (GLAN) - register "PcieRpLtrEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "true" register "PcieClkSrcUsage[4]" = "9" register "PcieClkSrcClkReq[4]" = "4" chip soc/intel/common/block/pcie/rtd3 @@ -177,7 +177,7 @@ end device ref pcie_rp11 on # PCIe root port #11 x1, Clock 1 (WLAN) - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[10]" = "1" diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb index a4e3052..45abfec 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -120,21 +120,21 @@ end device ref pcie_rp3 on # PCIe root port #3 x1, Clock 1 (WLAN) - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "2" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[2]" = "1" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 0 (SSD2) # Despite the name, SSD1_CLKREQ# is used for SSD2 - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 05f4f02..f3a7dff 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -100,7 +100,7 @@ device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" @@ -108,21 +108,21 @@ device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "0" + register "PcieRpLtrEnable[9]" = "false" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" end diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index ae0a514..408cdcf 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -152,8 +152,8 @@ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; - /* PCIe LTR: Enable (1) / Disable (0) */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR */ + bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4e0ba86..8d5a9d1 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -201,11 +201,7 @@ */ bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; - /* - * Enable/Disable Latency Tolerance Reporting for Root Port - * 0: Disable LTR - * 1: Enable LTR - */ + /* Enable/Disable Latency Tolerance Reporting for Root Port */ bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* Enable/Disable HotPlug support for Root Port */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 437f015..41c7dd3c 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -277,8 +277,8 @@ /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; - /* PCIe LTR: Enable (1) / Disable (0) */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR */ + bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index 7a6033a..4b33a26 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -184,10 +184,10 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/86193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf Gerrit-Change-Number: 86193 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: tree: Use true false for PcieRpEnable[]
by Elyes Haouas (Code Review) 02 Feb '25

02 Feb '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86192?usp=email ) Change subject: tree: Use true false for PcieRpEnable[] ...................................................................... tree: Use true false for PcieRpEnable[] PcieRpEnable[] is a boolean, so use true false instead of 0 1. Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86192 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/imb-1222/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/dooly/overridetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb M src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M util/mainboard/google/puff/template/overridetree.cb 78 files changed, 370 insertions(+), 370 deletions(-) Approvals: Sean Rhodes: Looks good to me, but someone else must approve Maxim Polyakov: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1338292..1de7292 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -89,7 +89,7 @@ end device ref pcie_rp3 on # Ethernet controller - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpClkSrcNumber[2]" = "0" @@ -98,7 +98,7 @@ end device ref pcie_rp4 on # Wireless controller - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" @@ -107,7 +107,7 @@ end device ref pcie_rp9 on # NVMe controller - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 21661f9..996bced 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -251,7 +251,7 @@ # Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text) device ref pcie_rp1 on # dGPU; x4 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" @@ -260,7 +260,7 @@ end device ref pcie_rp7 on # NGFF; x2 - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" @@ -269,7 +269,7 @@ end device ref pcie_rp9 on # LAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" @@ -278,7 +278,7 @@ end device ref pcie_rp10 on # WLAN - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb index c91ffaa..4a01a5a 100644 --- a/src/mainboard/asrock/imb-1222/devicetree.cb +++ b/src/mainboard/asrock/imb-1222/devicetree.cb @@ -209,7 +209,7 @@ }" end device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpLtrEnable[16]" = "1" register "PcieRpSlotImplemented[16]" = "1" register "PcieClkSrcUsage[7]" = "16" @@ -217,13 +217,13 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X" end device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[3]" = "4" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1) - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpSlotImplemented[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[5]" = "5" @@ -231,7 +231,7 @@ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X" end device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1) - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[6]" = "6" diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 2fa7a30..48a2bbc 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -112,7 +112,7 @@ device ref uart2 on end device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" @@ -121,7 +121,7 @@ chip drivers/wifi/generic device pci 00.0 on end end - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -129,7 +129,7 @@ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" @@ -137,7 +137,7 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index ac4ec46..749cb7c 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -66,7 +66,7 @@ device ref uart2 on end device ref pcie_rp1 on device pci 00.0 on end # x4 TBT - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" @@ -76,7 +76,7 @@ end device ref pcie_rp5 on device pci 00.0 on end # x1 LAN - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -84,7 +84,7 @@ end device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" @@ -93,7 +93,7 @@ end device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M (J_SSD1) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index d7070fe..64c9760 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -157,7 +157,7 @@ device ref pcie_rp3 on # x1 baseboard WWAN # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "0" register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" register "PcieRpLtrEnable[2]" = "1" @@ -167,7 +167,7 @@ device ref pcie_rp6 on # x1 baseboard i210 # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "0" register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" register "PcieRpLtrEnable[5]" = "1" @@ -177,7 +177,7 @@ device ref pcie_rp9 on # x4 FPGA # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "0" register "PcieRpHotPlug[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 971d886..3e1ccab 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -193,13 +193,13 @@ }" # PCIe port 9 for Card Reader - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 9c1cc44..8187868 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -336,7 +336,7 @@ end end # I2C #4 device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -349,7 +349,7 @@ end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index ed83f86..7424247 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -289,7 +289,7 @@ device ref pcie_rp3 on # LAN, will be swapped to port 1 by FSP # x1 - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" @@ -304,7 +304,7 @@ end device ref pcie_rp4 on # x1 WLAN - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "5" register "PcieRpAdvancedErrorReporting[3]" = "1" @@ -317,7 +317,7 @@ end device ref pcie_rp5 on # x4 NVMe - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -326,7 +326,7 @@ end device ref pcie_rp9 on # 2nd LAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" @@ -339,7 +339,7 @@ end end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpClkReqSupport[10]" = "1" register "PcieRpClkReqNumber[10]" = "2" register "PcieRpAdvancedErrorReporting[10]" = "1" @@ -347,7 +347,7 @@ register "PcieRpClkSrcNumber[10]" = "2" end device ref pcie_rp12 on - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" register "PcieRpClkReqSupport[11]" = "1" register "PcieRpClkReqNumber[11]" = "2" register "PcieRpAdvancedErrorReporting[11]" = "1" diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index f359bf3..421ebc1 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -116,7 +116,7 @@ end device ref pcie_rp7 on # x1 TPU1 - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "4" register "PcieRpAdvancedErrorReporting[6]" = "1" @@ -125,7 +125,7 @@ end device ref pcie_rp8 on # x1 TPU0 - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "2" register "PcieRpAdvancedErrorReporting[7]" = "1" @@ -134,20 +134,20 @@ end device ref pcie_rp9 on # x4 i350 LAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "0" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpClkSrcNumber[8]" = "2" end device ref pcie_rp10 off - register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[9]" = "false" end device ref pcie_rp11 off - register "PcieRpEnable[10]" = "0" + register "PcieRpEnable[10]" = "false" end device ref pcie_rp12 off - register "PcieRpEnable[11]" = "0" + register "PcieRpEnable[11]" = "false" end end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 7ae5255..1de2833 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -78,7 +78,7 @@ device ref uart2 on end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0b4558b..54dc960 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -162,7 +162,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN # Enable Root port 9(x4) for NVMe. - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" @@ -170,7 +170,7 @@ register "PcieClkSrcClkReq[1]" = "1" # PCIe port 14 for M.2 E-key WLAN - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 3a624d9..09a95df 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -20,7 +20,7 @@ }" # No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 691e51f..8e7c0b0 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -20,7 +20,7 @@ }" # Enable Root port 9(x2) for NVMe. - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" @@ -28,7 +28,7 @@ register "PcieClkSrcClkReq[1]" = "1" # Enable Root port 11(x2) for NVMe. - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "10" @@ -36,7 +36,7 @@ register "PcieClkSrcClkReq[2]" = "1" # No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index d6f5f60..656cd6b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -20,7 +20,7 @@ }" # No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false" # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 43801bf..27d642d 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -71,14 +71,14 @@ }" # PCIe port 7 for M.2 E-key WLAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # RP 7 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" # Enable Root port 13 (x4) for dGPU - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "12" diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index b1df825..bcdcd52 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -20,7 +20,7 @@ }" # No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false" # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index bac387d..45c364b 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -23,7 +23,7 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD # No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 5f81bec..e143327 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -310,7 +310,7 @@ end device ref pcie_rp1 on # WLAN - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 51ba199..4f5e543 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -323,7 +323,7 @@ end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index c93cc4b..d9238b8 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -366,7 +366,7 @@ device ref pcie_rp1 on end device ref pcie_rp4 on # x1 - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" @@ -379,7 +379,7 @@ end device ref pcie_rp5 on # x4 - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -388,7 +388,7 @@ end device ref pcie_rp9 on # x2 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 1187636..b3eabfd 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -361,7 +361,7 @@ end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 289cc72..c1c0b20 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -325,7 +325,7 @@ end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" @@ -338,7 +338,7 @@ end device ref pcie_rp9 on # x2 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 7869dc5..0c40c92 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -314,7 +314,7 @@ end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index f9edf26..676b331 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -305,7 +305,7 @@ end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 724d2ad..199a63c 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -184,10 +184,10 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 2eee315..6482682 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -162,7 +162,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN # Enable Root port 9(x4) for NVMe. - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" @@ -170,7 +170,7 @@ register "PcieClkSrcClkReq[1]" = "1" # PCIe port 14 for M.2 E-key WLAN - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index 073222b..81fac90 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -173,7 +173,7 @@ }" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index eec6189..2db0b63 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -245,10 +245,10 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 3bfb9b4..0bd90ee 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -253,10 +253,10 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index 0595df2..ec19352 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -177,45 +177,45 @@ }" # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5" # PCIe root port 9 for SSD (PCIe Lanes 11, 12) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" # PCIe root port 10 disabled - register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[9]" = "false" # PCIe root port 11 TPU1 - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4" # PCIe root port 12 TPU0 - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" register "PcieRpLtrEnable[11]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2" # PCIe port 13 for i350 NIC (x4) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" @@ -224,9 +224,9 @@ # effectively "not connected" register "PcieClkSrcClkReq[3]" = "0xFF" # Disable the remaining ports 14-16 - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index a3e15c4..88f98ef 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -245,10 +245,10 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index 09a473c..6e6a869 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -177,45 +177,45 @@ }" # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5" # PCIe root port 9 for SSD (PCIe Lanes 11, 12) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" # PCIe root port 10 disabled - register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[9]" = "false" # PCIe root port 11 TPU1 - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4" # PCIe root port 12 TPU0 - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" register "PcieRpLtrEnable[11]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2" # PCIe port 13 for i350 NIC (x4) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" @@ -224,9 +224,9 @@ # effectively "not connected" register "PcieClkSrcClkReq[3]" = "0xFF" # Disable the remaining ports 14-16 - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 9754826..7e43c2b 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -168,10 +168,10 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index de0e8a2..859da99 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -178,10 +178,10 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 4309ec7..7125c40 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -184,47 +184,47 @@ }" # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" # PCIe root port 9 for SSD (PCIe Lanes 9-12) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" # PCIe root port 10-12 disabled - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" # PCIe root port 13 TPU0 - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" # PCIe root port 14 TPU1 - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 4 register "PcieClkSrcUsage[4]" = "13" register "PcieClkSrcClkReq[4]" = "4" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 04604c4..df25e86 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -179,10 +179,10 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index d245844..e09e861 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -182,18 +182,18 @@ }" # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" # PCIe port 11 for card reader - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 569abe5..e0f052f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -182,23 +182,23 @@ }" # PCIe port 8 for Card Reader - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4" # PCIe port 9 for LAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[3]" = "3" # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieClkSrcUsage[1]" = "9" register "PcieClkSrcClkReq[1]" = "1" # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 304b4d5..049859a 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -42,30 +42,30 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieRpEnable[16]" = "0" - register "PcieRpEnable[17]" = "0" - register "PcieRpEnable[18]" = "0" - register "PcieRpEnable[19]" = "0" - register "PcieRpEnable[20]" = "0" - register "PcieRpEnable[21]" = "0" - register "PcieRpEnable[22]" = "0" - register "PcieRpEnable[23]" = "0" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "true" + register "PcieRpEnable[10]" = "true" + register "PcieRpEnable[11]" = "true" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" + register "PcieRpEnable[16]" = "false" + register "PcieRpEnable[17]" = "false" + register "PcieRpEnable[18]" = "false" + register "PcieRpEnable[19]" = "false" + register "PcieRpEnable[20]" = "false" + register "PcieRpEnable[21]" = "false" + register "PcieRpEnable[22]" = "false" + register "PcieRpEnable[23]" = "false" register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index cfccfc9..266c698 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -40,30 +40,30 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieRpEnable[16]" = "1" - register "PcieRpEnable[17]" = "1" - register "PcieRpEnable[18]" = "1" - register "PcieRpEnable[19]" = "1" - register "PcieRpEnable[20]" = "1" - register "PcieRpEnable[21]" = "1" - register "PcieRpEnable[22]" = "1" - register "PcieRpEnable[23]" = "1" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" + register "PcieRpEnable[16]" = "true" + register "PcieRpEnable[17]" = "true" + register "PcieRpEnable[18]" = "true" + register "PcieRpEnable[19]" = "true" + register "PcieRpEnable[20]" = "true" + register "PcieRpEnable[21]" = "true" + register "PcieRpEnable[22]" = "true" + register "PcieRpEnable[23]" = "true" register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index e49c102..0133a11 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -3,22 +3,22 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 50bff81..157a465 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -41,22 +41,22 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 2265d64..8df9851 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -26,22 +26,22 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 20ea0c1..cd17307 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -75,37 +75,37 @@ end device ref i2c4 off end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" register "PcieRpClkSrcNumber[6]" = "2" end device ref pcie_rp8 on - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" register "PcieRpClkSrcNumber[7]" = "3" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" end device ref pcie_rp14 on - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" register "PcieRpClkSrcNumber[13]" = "5" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" register "PcieRpClkSrcNumber[16]" = "7" diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 6bca121..7dae329 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -77,35 +77,35 @@ device ref cio on end device ref pcie_rp1 on # PCIE x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" register "PcieRpClkSrcNumber[0]" = "2" end device ref pcie_rp5 on # PCIE x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" end device ref pcie_rp6 on # PCIE x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp9 on # PCIE x1 -> WLAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" end device ref pcie_rp10 on # PCIE x1 -> WiGig - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" register "PcieRpClkSrcNumber[9]" = "4" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 29aea40..a030fe7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -124,31 +124,31 @@ }" end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "5" register "PcieRpClkSrcNumber[2]" = "5" end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "2" register "PcieRpClkSrcNumber[3]" = "2" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "1" register "PcieRpClkSrcNumber[8]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index a2d2459..1b8e391 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -148,22 +148,22 @@ device ref pcie_rp1 off end device ref pcie_rp3 on end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "2" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "1" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "6" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 1a565e5..08eb965 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -210,7 +210,7 @@ end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic @@ -219,7 +219,7 @@ end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "2" end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 74a183b..2aae0d0 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -186,24 +186,24 @@ device ref i2c4 on end device ref pcie_rp1 on end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "0" end device ref pcie_rp8 on # x1 - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" end device ref pcie_rp9 on # x4 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpClkReqSupport[12]" = "1" register "PcieRpClkReqNumber[12]" = "1" end diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index f5d05b8..9fb1429 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -86,13 +86,13 @@ }" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" end device ref pcie_rp10 on - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index 9cf710f..5624d6b 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -22,23 +22,23 @@ end device ref pcie_rp1 on # COMe 4 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" end device ref pcie_rp2 on # COMe 5 - register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[1]" = "true" end device ref pcie_rp3 on # COMe 6 - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" end device ref pcie_rp4 on # COMe 7 - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" end device ref pcie_rp12 on # COMe 3 - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" end device ref smbus on chip drivers/i2c/nct7802y diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 3b440a0b..771ea06 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -165,11 +165,11 @@ register "PcieRpClkSrcNumber[9]" = "3" end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpClkSrcNumber[10]" = "3" end device ref pcie_rp12 on - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" register "PcieRpClkSrcNumber[11]" = "3" end device ref lpc_espi on diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 6e1ecfd..e097123 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -171,7 +171,7 @@ device ref uart2 hidden end # in ACPI mode device ref pcie_rp21 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieRpSlotImplemented[20]" = "1" register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" @@ -180,7 +180,7 @@ end device ref pcie_rp1 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "1" register "PcieRpSlotImplemented[0]" = "1" register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" @@ -188,28 +188,28 @@ register "PcieRpAspm[0]" = "AspmDisabled" end device ref pcie_rp5 on # PHY 3 - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" device pci 00.0 on smbios_dev_info 3 end end device ref pcie_rp6 on # PHY 4 - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "1" device pci 00.0 on smbios_dev_info 4 end end device ref pcie_rp7 on # PHY 2 - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" device pci 00.0 on smbios_dev_info 2 end end device ref pcie_rp8 on # PHY 1 - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" device pci 00.0 on smbios_dev_info 1 @@ -217,12 +217,12 @@ end device ref pcie_rp9 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieRpSlotImplemented[8]" = "1" end device ref pcie_rp14 on # PHY 0 - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" device pci 00.0 on smbios_dev_info 0 @@ -232,13 +232,13 @@ device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2500 VGA end - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieRpSlotImplemented[14]" = "1" end device ref pcie_rp16 on # M.2 E/CNVi # Disabled when CNVi is present - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[15]" = "true" register "PcieRpLtrEnable[15]" = "1" register "PcieRpSlotImplemented[15]" = "1" end diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 01c5df7..f2c75f3 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -52,14 +52,14 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" # LAN1 - register "PcieRpEnable[5]" = "1" # LAN2 - register "PcieRpEnable[6]" = "1" # LAN3 - register "PcieRpEnable[7]" = "1" # LAN4 - register "PcieRpEnable[8]" = "1" # LAN5 - register "PcieRpEnable[9]" = "1" # LAN6 - register "PcieRpEnable[11]" = "1" # M.2 WiFi - register "PcieRpEnable[12]" = "1" # M.2 NVMe x4 + register "PcieRpEnable[4]" = "true" # LAN1 + register "PcieRpEnable[5]" = "true" # LAN2 + register "PcieRpEnable[6]" = "true" # LAN3 + register "PcieRpEnable[7]" = "true" # LAN4 + register "PcieRpEnable[8]" = "true" # LAN5 + register "PcieRpEnable[9]" = "true" # LAN6 + register "PcieRpEnable[11]" = "true" # M.2 WiFi + register "PcieRpEnable[12]" = "true" # M.2 NVMe x4 # Enable Advanced Error Reporting for RP 5-10, 12, 13 register "PcieRpAdvancedErrorReporting[4]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index fd20b15..ef1c1a9 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -142,49 +142,49 @@ end device ref pcie_rp1 on # LAN - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpClkSrcNumber[0]" = "0" end device ref pcie_rp2 on # LAN - register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[1]" = "true" register "PcieRpAdvancedErrorReporting[1]" = "1" register "PcieRpLtrEnable[1]" = "1" register "PcieRpClkSrcNumber[1]" = "1" end device ref pcie_rp3 on # LAN - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpAdvancedErrorReporting[2]" = "1" register "PcieRpLtrEnable[2]" = "1" register "PcieRpClkSrcNumber[2]" = "2" end device ref pcie_rp4 on # LAN - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "1" register "PcieRpClkSrcNumber[3]" = "3" end device ref pcie_rp5 on # LAN - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpClkSrcNumber[4]" = "4" end device ref pcie_rp6 on # LAN - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieRpClkSrcNumber[5]" = "5" end device ref pcie_rp9 on # mPCIe WIFI - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index f522e66..9bd8e4f 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -125,7 +125,7 @@ register "SataPortsDevSlp[2]" = "1" end device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN) - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieRpHotPlug[6]" = "1" @@ -135,12 +135,12 @@ end device ref pcie_rp8 on device pci 00.0 on end # x1 (LAN) - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpSlotImplemented[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" @@ -148,7 +148,7 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpSlotImplemented[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[1]" = "12" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index d2f1a83..a043006 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -118,7 +118,7 @@ end device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN) register "PcieRpSlotImplemented[7]" = "1" - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" @@ -126,13 +126,13 @@ end device ref pcie_rp10 on device pci 00.0 on end # x1 (LAN) - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieClkSrcUsage[3]" = "9" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[1]" = "12" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index cf1a8b8..e10e41a 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -210,20 +210,20 @@ end device ref pcie_rp21 on register "PcieRpSlotImplemented[20]" = "1" - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[10]" = "20" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X" end device ref pcie_rp1 on register "PcieRpSlotImplemented[0]" = "1" - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "1" register "PcieClkSrcUsage[1]" = "0x80" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end device ref pcie_rp9 on # GbE #1 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[14]" = "8" # Type indexes are needed for systemd to use "onboard" names by default @@ -236,12 +236,12 @@ end end device ref pcie_rp10 on # BMC video - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "1" register "PcieClkSrcUsage[8]" = "9" end device ref pcie_rp11 on # GbE #2 - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[11]" = "10" device pci 00.0 on diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 18ffb1b..0b912c6 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -144,10 +144,10 @@ }" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" end device ref lpc_espi on # EC/KBC requires continuous mode diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 13ca6e7..00b5ea6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -157,16 +157,16 @@ device ref uart2 on end device ref pcie_rp1 on end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpLtrEnable[2]" = "1" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" end device ref lpc_espi on diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 3b8343b..851a8bf 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -38,25 +38,25 @@ end device ref pcie_rp5 on device pci 00.0 on end # x1 i219 - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieClkSrcUsage[4]" = "0x70" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "0" end device ref pcie_rp6 on device pci 00.0 on end # x1 i210 - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[5]" = "0" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index d8bad2e..c5121f9a 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -81,39 +81,39 @@ end end device ref pcie_rp1 off - register "PcieRpEnable[0]" = "0" # Debug (x1) + register "PcieRpEnable[0]" = "false" # Debug (x1) register "PcieClkSrcUsage[2]" = "0" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" # CORE (x1) + register "PcieRpEnable[4]" = "true" # CORE (x1) register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "1" end device ref pcie_rp6 on device pci 00.0 on end # i210 (x1) - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[5]" = "0" end device ref pcie_rp7 on device pci 00.0 on end # VL805 Front Rack/UIB (x1) - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[6]" = "0" end device ref pcie_rp8 on device pci 00.0 on end # VL805 Back MB (x1) - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieClkSrcUsage[0]" = "7" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[7]" = "0" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "1" # NVMe (x4) + register "PcieRpEnable[16]" = "true" # NVMe (x4) register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 8a28ca1..15d217b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -49,34 +49,34 @@ end device ref igpu on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp2 on - register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[1]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end device ref pcie_rp9 on # Slot JPCIE1 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 97f995d..14dbb0f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -41,12 +41,12 @@ device ref peg0 on end # unused device ref peg1 on # Slot JPCIE1 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end device ref pcie_rp1 on # Slot JPCIE1 - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end device ref pcie_rp3 on @@ -55,12 +55,12 @@ end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 7993383..b53a01f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -44,20 +44,20 @@ end device ref pcie_rp1 on # Slot JPCIE4 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp5 on # Slot JPCIE5 - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieRpAdvancedErrorReporting[8]" = "1" device pci 00.0 on # GbE 1 @@ -65,7 +65,7 @@ end end device ref pcie_rp10 on - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "1" register "PcieRpAdvancedErrorReporting[9]" = "1" device pci 00.0 on # GbE 2 @@ -73,7 +73,7 @@ end end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" register "PcieRpAdvancedErrorReporting[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index 1d0dc7f..eec01fb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -45,24 +45,24 @@ smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp2 on - register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[1]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref pcie_rp9 on # Slot JSXB2 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index f5b7a1f..f951aae 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -98,7 +98,7 @@ end device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 0 (Thunderbolt) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpLtrEnable[16]" = "1" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" @@ -106,7 +106,7 @@ end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 10 (SSD2) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[10]" = "20" register "PcieClkSrcClkReq[10]" = "10" @@ -114,7 +114,7 @@ end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 9 (SSD1) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" @@ -122,7 +122,7 @@ end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 5 (GLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[5]" = "13" register "PcieClkSrcClkReq[5]" = "5" @@ -130,7 +130,7 @@ end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 7 (Card Reader) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[7]" = "14" register "PcieClkSrcClkReq[7]" = "7" @@ -138,7 +138,7 @@ end device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 6 (WLAN) - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[15]" = "true" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index 3a99ab4..afdc264 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -113,21 +113,21 @@ end device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 14 (SSD2) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpLtrEnable[16]" = "1" register "PcieClkSrcUsage[14]" = "16" register "PcieClkSrcClkReq[14]" = "14" end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 15 (SSD3) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[15]" = "20" register "PcieClkSrcClkReq[15]" = "15" end device ref pcie_rp1 on # PCI Express root port #1 x4, Clock 6 (Thunderbolt) - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "1" register "PcieRpHotPlug[0]" = "1" register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED @@ -135,35 +135,35 @@ end device ref pcie_rp5 on # PCI Express root port #5 x4, Clock 10 (USB 3.2) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[10]" = "4" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 8 (SSD) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[8]" = "8" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp13 on # PCI Express root port #13 x1, Clock 0 (WLAN) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[0]" = "12" register "PcieClkSrcClkReq[0]" = "0" end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 1 (GLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[1]" = "13" register "PcieClkSrcClkReq[1]" = "1" end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 4 (Card Reader) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[4]" = "14" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index 36744e9..630d669 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -40,7 +40,7 @@ end device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -48,21 +48,21 @@ end device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index 9170671..132272d 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -33,7 +33,7 @@ end device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -41,21 +41,21 @@ end device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb index effe280..7d2beab 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -41,7 +41,7 @@ end device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" @@ -49,7 +49,7 @@ end device ref pcie_rp8 on device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -61,7 +61,7 @@ end device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" @@ -70,7 +70,7 @@ end device ref pcie_rp13 on device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 5760e669..d0a79806 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -96,7 +96,7 @@ device ref uart2 on end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" @@ -104,7 +104,7 @@ end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 10 (SSD) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" @@ -112,7 +112,7 @@ end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 6 (WLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[6]" = "13" register "PcieClkSrcClkReq[6]" = "6" @@ -120,7 +120,7 @@ end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 5 (LAN) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[5]" = "14" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 9251440..291cb45 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -133,7 +133,7 @@ end device ref pcie_rp1 on # Root port #1 x4 (TBT) - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" @@ -143,7 +143,7 @@ end device ref pcie_rp5 on # Root port #5 x1 (LAN) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -152,7 +152,7 @@ end device ref pcie_rp6 on # Root port #6 x1 (WLAN) - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" @@ -161,7 +161,7 @@ end device ref pcie_rp9 on # Root port #9 x4 (NVMe) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index cc3c619..6dd4eb3 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -109,35 +109,35 @@ device ref uart2 on end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 12 (SSD) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 13 (WLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[13]" = "13" register "PcieClkSrcClkReq[13]" = "13" end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 14 (GLAN) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[14]" = "14" register "PcieClkSrcClkReq[14]" = "14" end device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 15 (Card Reader) - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[15]" = "true" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[15]" = "15" register "PcieClkSrcClkReq[15]" = "15" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 7e3ef0c..bb49da9 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -106,7 +106,7 @@ end device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 0 (Thunderbolt) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpLtrEnable[16]" = "1" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" @@ -115,7 +115,7 @@ end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" @@ -123,7 +123,7 @@ end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 12 (SSD1) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" @@ -131,7 +131,7 @@ end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 7 (GLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[7]" = "13" register "PcieClkSrcClkReq[7]" = "7" @@ -139,7 +139,7 @@ end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 9 (Card Reader) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[9]" = "14" register "PcieClkSrcClkReq[9]" = "9" @@ -147,7 +147,7 @@ end device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 6 (WLAN) - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[15]" = "true" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 1c5d720..05f4f02 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -99,7 +99,7 @@ device ref pcie_rp1 on end device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -107,21 +107,21 @@ end device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index 6712659..7a6033a 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -183,10 +183,10 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" -- To view, visit https://review.coreboot.org/c/coreboot/+/86192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528 Gerrit-Change-Number: 86192 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjoga and pujjogatwin: Modify WWAN EM060 power ...
by Luca Lai (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86249?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/pujjoga and pujjogatwin: Modify WWAN EM060 power on sequence ...................................................................... mb/google/nissa/var/pujjoga and pujjogatwin: Modify WWAN EM060 power on sequence Modify GPP_F12 gpio pin to fit em060 power sequence spec. BUG=b:391066038 TEST=Build and check WWAN EM060 power on sequence. Change-Id: Ic4e7acf41da004d990529f9ddb0fc5a32ba03b3b Signed-off-by: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pujjoga/gpio.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/86249/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4e7acf41da004d990529f9ddb0fc5a32ba03b3b Gerrit-Change-Number: 86249 Gerrit-PatchSet: 2 Gerrit-Owner: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[L] Change in coreboot[main]: mb/google/nissa/var/dirks: Add initial override devicetree
by Ivy Jian (Code Review) 02 Feb '25

02 Feb '25

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86250?usp=email ) Change subject: mb/google/nissa/var/dirks: Add initial override devicetree ...................................................................... mb/google/nissa/var/dirks: Add initial override devicetree Add initial override devicetree for dirks based on the latest schematic (0W4_TWL_A_MB_0120.pdf). - Add eMMC DLL tuning value (copy from riven) - Configure I2C buses - Configure USB ports - Configure audio codec - Configure WIFI6(CNVi) and WIFI7(PCIe) Note : There will be a separate CL to configure the implementation of repurposing the TCSS port to USB Type-A after FSP support is added. BUG=b:389391653 TEST=none. Change-Id: Ic0b80e3121d94ede771ecc30cf0c66a67b9a41d0 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dirks/overridetree.cb 1 file changed, 345 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/86250/1 diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb index 4f2c04a..56afc80 100644 --- a/src/mainboard/google/brya/variants/dirks/overridetree.cb +++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb @@ -1,6 +1,349 @@ chip soc/intel/alderlake - device domain 0 on - end + register "sagv" = "SaGv_Enabled" + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F3C" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0x1" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2_A0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB2_A1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # USB2_A2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB2_A3 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A4 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 5500, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1, + .time_window_max = 1, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref hda on + chip drivers/sof + register "jack_tplg" = "rt5682" + device generic 0 on end + end + end + device ref pcie_rp11 on + # Enable wlan PCIe 11 using clk 2 + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + use usb2_port8 as bluetooth_companion + device pci 00.0 on end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end + device ref emmc on end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A4"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVI Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A4"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0b80e3121d94ede771ecc30cf0c66a67b9a41d0 Gerrit-Change-Number: 86250 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: UPSTREAM: mb/google/nissa/var/pujjoga and pujjogatwin: Modify WWAN EM...
by Luca Lai (Code Review) 02 Feb '25

02 Feb '25

Luca Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86249?usp=email ) Change subject: UPSTREAM: mb/google/nissa/var/pujjoga and pujjogatwin: Modify WWAN EM060 power on sequence ...................................................................... UPSTREAM: mb/google/nissa/var/pujjoga and pujjogatwin: Modify WWAN EM060 power on sequence Modify GPP_F12 gpio pin to fit em060 power sequence spec. BUG=b:391066038 TEST=Build and check WWAN EM060 power on sequence. Change-Id: Ic4e7acf41da004d990529f9ddb0fc5a32ba03b3b Signed-off-by: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pujjoga/gpio.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/86249/1 diff --git a/src/mainboard/google/brya/variants/pujjoga/gpio.c b/src/mainboard/google/brya/variants/pujjoga/gpio.c index 1390e08..6098db9 100644 --- a/src/mainboard/google/brya/variants/pujjoga/gpio.c +++ b/src/mainboard/google/brya/variants/pujjoga/gpio.c @@ -4,8 +4,10 @@ #include <baseboard/variants.h> #include <soc/gpio.h> -/* Pad configuration in ramstage for Sundance */ +/* Pad configuration in ramstage for Pujjoga and Pujjogatwin */ static const struct pad_config override_gpio_table[] = { + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* A8 : WWAN_RF_DISABLE_ODL */ PAD_CFG_GPO(GPP_A8, 1, DEEP), /* A18 : HDMI_HPD */ @@ -34,8 +36,6 @@ PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), /* E21 : NC */ PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), - /* F12 : WWAN_RST_L */ - PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* H12 : NC */ PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : NC */ @@ -84,6 +84,8 @@ /* Pad configuration in romstage for Sundance */ static const struct pad_config romstage_gpio_table[] = { + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), /* Enable touchscreen, hold in reset */ /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ PAD_CFG_GPO(GPP_C0, 1, DEEP), -- To view, visit https://review.coreboot.org/c/coreboot/+/86249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4e7acf41da004d990529f9ddb0fc5a32ba03b3b Gerrit-Change-Number: 86249 Gerrit-PatchSet: 1 Gerrit-Owner: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2
by jason-ch chen (Code Review) 02 Feb '25

02 Feb '25

jason-ch chen has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/86248?usp=email ) Change subject: soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2 ...................................................................... soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2 - Fix error handler for infra timeout in SSPM. The error handler for infra timeout in SSPM was not handled properly, causing the ISR to get stuck. As a result, tasks without ISR would not continue to operate. - Enable SSPM debug configs BUG=b:360756645, b:374015969 TEST=get "MediaTek SSPM firmware: version 2.0.2" by strings sspm.bin | grep version Change-Id: Id9491ecf7dde823f5ec034ae92d4b4bcfcdc6905 Signed-off-by: jason-ch chen <jason-ch.chen(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8186/sspm.bin M soc/mediatek/mt8186/sspm.bin.md5 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/48/86248/1 diff --git a/soc/mediatek/mt8186/sspm.bin b/soc/mediatek/mt8186/sspm.bin index f72c1f1..89cad15 100644 --- a/soc/mediatek/mt8186/sspm.bin +++ b/soc/mediatek/mt8186/sspm.bin Binary files differ diff --git a/soc/mediatek/mt8186/sspm.bin.md5 b/soc/mediatek/mt8186/sspm.bin.md5 index 23130ca..534a51b 100644 --- a/soc/mediatek/mt8186/sspm.bin.md5 +++ b/soc/mediatek/mt8186/sspm.bin.md5 @@ -1 +1 @@ -634e532d6acb98e4b1807944233b8f81 *sspm.bin +c39ba49caff7a4d94c547c391d8ef25b *sspm.bin -- To view, visit https://review.coreboot.org/c/blobs/+/86248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Id9491ecf7dde823f5ec034ae92d4b4bcfcdc6905 Gerrit-Change-Number: 86248 Gerrit-PatchSet: 1 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com>

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[S] Change in coreboot[main]: intel/acpi: Put BSP as the first entry
by Vladimir Serbinenko (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Vladimir Serbinenko. Hello Intel coreboot Reviewers, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86247?usp=email to look at the new patch set (#3). Change subject: intel/acpi: Put BSP as the first entry ...................................................................... intel/acpi: Put BSP as the first entry Linux complains in dmesg as a firmware bug that BSP is not the first entry. NetBSD hangs and OpenBSD panics early on boot. With this patch I was able to boot NetBSD and OpenBSD on darp10-b when loaded in GRUB. Note: vanilla bootloaders for NetBSD and OpenBSD still result in an apparent hang for an unknown reason. Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/86247/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Gerrit-Change-Number: 86247 Gerrit-PatchSet: 3 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com>

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[XS] Change in coreboot[main]: acpi: Zero-out MADT before filling it
by Vladimir Serbinenko (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak, Vladimir Serbinenko. Hello Cliff Huang, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86246?usp=email to look at the new patch set (#3). Change subject: acpi: Zero-out MADT before filling it ...................................................................... acpi: Zero-out MADT before filling it Otherwise flags field is pre-filled with random garbage. Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/86246/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e Gerrit-Change-Number: 86246 Gerrit-PatchSet: 3 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com>

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[XS] Change in coreboot[main]: acpi: Zero-out MADT before filling it
by Vladimir Serbinenko (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak, Vladimir Serbinenko. Hello Cliff Huang, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86246?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: acpi: Zero-out MADT before filling it ...................................................................... acpi: Zero-out MADT before filling it Otherwise flags field is pre-filled with random garbage. Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/86246/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e Gerrit-Change-Number: 86246 Gerrit-PatchSet: 2 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com>

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[S] Change in coreboot[main]: intel/acpi: Put BSP as the first entry
by Vladimir Serbinenko (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Intel coreboot Reviewers. Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86247?usp=email ) Change subject: intel/acpi: Put BSP as the first entry ...................................................................... intel/acpi: Put BSP as the first entry Linux complains in dmesg as a firmware bug that BSP is not the first entry. NetBSD hangs and OpenBSD panics early on boot. With this patch I was able to boot NetBSD and OpenBSD on darp10-b when loaded in GRUB. Note: vanilla bootloaders for NetBSD and OpenBSD still result in an apparent hang for an unknown reason. Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/86247/1 diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index ee4777a..a6b9c21 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -48,10 +48,17 @@ int32_t eff_apic_ids[CONFIG_MAX_CPUS] = {0}; extern struct cpu_info cpu_infos[]; uint32_t i, j = 0; + u32 bsp_lapicid = lapicid(); + + /* As per spec first comes BSP. */ + cpu_apic_info.apic_ids[0] = bsp_lapicid; + perf_core_cnt = 1; for (i = 0; i < ARRAY_SIZE(cpu_apic_info.apic_ids); i++) { if (!cpu_infos[i].cpu) continue; + if (cpu_infos[i].cpu->path.apic.apic_id == bsp_lapicid) + continue; if (cpu_infos[i].cpu->path.apic.core_type == CPU_TYPE_PERF) cpu_apic_info.apic_ids[perf_core_cnt++] = cpu_infos[i].cpu->path.apic.apic_id; @@ -60,8 +67,8 @@ cpu_infos[i].cpu->path.apic.apic_id; } - if (perf_core_cnt > 1) - bubblesort(cpu_apic_info.apic_ids, perf_core_cnt, NUM_ASCENDING); + if (perf_core_cnt > 2) + bubblesort(cpu_apic_info.apic_ids + 1, perf_core_cnt - 1, NUM_ASCENDING); for (i = perf_core_cnt; j < eff_core_cnt; i++, j++) cpu_apic_info.apic_ids[i] = eff_apic_ids[j]; -- To view, visit https://review.coreboot.org/c/coreboot/+/86247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Gerrit-Change-Number: 86247 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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