coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: acpi: Zero-out MADT before filling it
by Vladimir Serbinenko (Code Review) 02 Feb '25

02 Feb '25

Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86246?usp=email ) Change subject: acpi: Zero-out MADT before filling it ...................................................................... acpi: Zero-out MADT before filling it Otherwise flags field is pre-filled with random garbage. Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e --- M 3rdparty/arm-trusted-firmware M 3rdparty/blobs M 3rdparty/fsp M 3rdparty/intel-microcode M 3rdparty/vboot M src/acpi/acpi.c 6 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/86246/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 15e5c6c..48f1bc9 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 15e5c6c91d483aa52908154cc80e48956e234232 +Subproject commit 48f1bc9f52491d51ca92a1d396ccbe6a9d09e780 diff --git a/3rdparty/blobs b/3rdparty/blobs index 14f8fcc..a8db7df 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 14f8fcc1b426cb0884a21a9b715da6e0c1c7f434 +Subproject commit a8db7dfe823def043368857b8fbfbba86f2e9e47 diff --git a/3rdparty/fsp b/3rdparty/fsp index 15c0f7b..cc6399e 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 15c0f7b3f723bcd713e5ab11ebc502f30d9084e7 +Subproject commit cc6399e8c759ad4ed83c2d6ea568fd918fc9bc06 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 8ac9378..5278dfc 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 8ac9378a84879e81c503e09f344560b3dd7f72df +Subproject commit 5278dfcf98e89098326b3eb8a85d07120a8730f8 diff --git a/3rdparty/vboot b/3rdparty/vboot index 3f94e2c..09fcd21 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 3f94e2c7ed58c4e67d6e7dc6052ec615dbbb9bb4 +Subproject commit 09fcd2184f9c714829503e84b8a7dfe7f2584e00 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index ffd9b79..8f5c09f 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -138,6 +138,8 @@ acpi_madt_t *madt = (acpi_madt_t *)header; unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t); + memset(madt, 0, sizeof(*madt)); + if (acpi_fill_header(header, "APIC", MADT, sizeof(acpi_madt_t)) != CB_SUCCESS) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/86246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e Gerrit-Change-Number: 86246 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com>

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Subrata Banik (Code Review) 02 Feb '25

02 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... drivers/soc/cse: Fix overflow in CSE telemetry calculation MSEC_TO_USEC(cse_perf_data.timestamp[i]) does overflow. Here is an example, if cse_perf_data.timestamp[i] value is 4304903 milliseconds. When multiplied by 1000 to convert to microseconds, the value becomes 0x979B58 instead of 0x100979B58. TEST=Boot to OS Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86215 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/cse/telemetry.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/telemetry.c b/src/soc/intel/common/block/cse/telemetry.c index 2c9fb54..62814eb 100644 --- a/src/soc/intel/common/block/cse/telemetry.c +++ b/src/soc/intel/common/block/cse/telemetry.c @@ -4,7 +4,7 @@ #include <intelblocks/cse.h> #include <timestamp.h> -#define MSEC_TO_USEC(x) (x * 1000) +#define MSEC_TO_USEC(x) ((s64)x * 1000) enum cb_err cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brya/var/craaskov: Add/select VBT
by Matt DeVillier (Code Review) 02 Feb '25

02 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86214?usp=email ) Change subject: mb/google/brya/var/craaskov: Add/select VBT ...................................................................... mb/google/brya/var/craaskov: Add/select VBT Add VBT data file for craaskov, and enable its use by selecting INTEL_GMA_HAVE_VBT. VBT extracted from stock firmware image Google_Craaskov.15217.616.0; it has BDB version 2.51, which matches the current FSP binaries. TEST=build/boot craaskov with edk2 payload Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/variants/craaskov/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d32435b..dfa571e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -201,6 +201,7 @@ config BOARD_GOOGLE_CRAASKOV select BOARD_GOOGLE_BASEBOARD_NISSA + select INTEL_GMA_HAVE_VBT select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_CONSTITUTION diff --git a/src/mainboard/google/brya/variants/craaskov/data.vbt b/src/mainboard/google/brya/variants/craaskov/data.vbt new file mode 100644 index 0000000..c47b424 --- /dev/null +++ b/src/mainboard/google/brya/variants/craaskov/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/86214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b Gerrit-Change-Number: 86214 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com>

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[S] Change in coreboot[main]: mb/starlabs/byte_adl: Disconnect unused GPIOs
by Matt DeVillier (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86134?usp=email ) Change subject: mb/starlabs/byte_adl: Disconnect unused GPIOs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4c2c32c0740e2ad763881f3f4d5920387f49c79 Gerrit-Change-Number: 86134 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 02 Feb 2025 22:46:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/amd/birman_plus/ec: Rectify ECRAM register bits
by Ana Carolina Cabral (Code Review) 02 Feb '25

02 Feb '25

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[M] Change in coreboot[main]: mb/amd/birman_plus/ec: Rectify ECRAM register bits
by Ana Carolina Cabral (Code Review) 02 Feb '25

02 Feb '25

Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/86084?usp=email ) Change subject: mb/amd/birman_plus/ec: Rectify ECRAM register bits ...................................................................... Patch Set 14: (6 comments) File src/mainboard/amd/birman_plus/ec.c: https://review.coreboot.org/c/coreboot/+/86084/comment/c0b9a636_ec15bf9c?us… : PS13, Line 11: #define EC_GPIO_0_ADDR 0xA0 > the defines are added, but not used in the code; is this intended? I thought about only enabling 19V if the eval card was present, but when I saw it was configurable I was not so sure. Added it to this patch. https://review.coreboot.org/c/coreboot/+/86084/comment/d923f27d_158ac1e9?us… : PS13, Line 36: _N > i don't think that this one is inverted. sure, the signal on the m. […] Done https://review.coreboot.org/c/coreboot/+/86084/comment/926679f0_853efc80?us… : PS13, Line 127: EC7_WL_RADIO_DIS_N > see my comment on the register bit; i'd expect this one needing to be cleared, not set Done https://review.coreboot.org/c/coreboot/+/86084/comment/bf1796c8_d196ae24?us… : PS13, Line 138: tmp = ECA_MUX1_S0 | ECA_SMBUS1_EN | ECA_SMBUS0_EN; > would probably be good to configure the other muxes here too Done https://review.coreboot.org/c/coreboot/+/86084/comment/17bfa07e_5712fcb1?us… : PS13, Line 142: tmp = ec_read(EC_GPIO_6_ADDR); : tmp |= EC6_TPNL_BUF_EN | EC6_TPAD_BUF_EN; : printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_6_ADDR, tmp); : ec_write(EC_GPIO_6_ADDR, tmp); > i'd move this block between the ones for EC_GPIO_3_ADDR and EC_GPIO_7_ADDR Done https://review.coreboot.org/c/coreboot/+/86084/comment/c8e7d93a_ec4ebeb7?us… : PS13, Line 156: if (CONFIG(DISABLE_WWAN_GBE_BIRMANPLUS)) { // no WWAN, turn off WWAN power > i'd find it a bit easier to read when doing the bit clear/bit set in the if/else branches and not ha […] Well, I personally prefer the default values being set first, but here you go.. -- To view, visit https://review.coreboot.org/c/coreboot/+/86084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471 Gerrit-Change-Number: 86084 Gerrit-PatchSet: 14 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 02 Feb 2025 22:00:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/amd/birman_plus/ec: Rectify ECRAM register bits
by Ana Carolina Cabral (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Ana Carolina Cabral. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86084?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/amd/birman_plus/ec: Rectify ECRAM register bits ...................................................................... mb/amd/birman_plus/ec: Rectify ECRAM register bits Rectify wrong EC module RAM registers bits based on PI source code 1.0.0.1b Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/mainboard/amd/birman_plus/ec.c 1 file changed, 48 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86084/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/86084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471 Gerrit-Change-Number: 86084 Gerrit-PatchSet: 14 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com>

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update PCIe Slot configurations
by Ana Carolina Cabral (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Maximilian Brune, Nick Kochlowski. Hello Felix Held, Maximilian Brune, Nick Kochlowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85493?usp=email to look at the new patch set (#23). The following approvals got outdated and were removed: Code-Review+1 by Nick Kochlowski, Code-Review+2 by Felix Held, Code-Review+2 by Maximilian Brune, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/amd/birman_plus: Update PCIe Slot configurations ...................................................................... mb/amd/birman_plus: Update PCIe Slot configurations Rectify board configuration flags based on the schematics Doc. 105-D99700-00C and User Guide #58168 (NDA). Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/ec.c M src/mainboard/amd/birman_plus/port_descriptors_glinda.c M src/mainboard/amd/birman_plus/port_descriptors_phoenix.c 4 files changed, 81 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85493/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/85493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Gerrit-Change-Number: 85493 Gerrit-PatchSet: 23 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: superio/fintek: Add Fintek F81801
by Felix Singer (Code Review) 02 Feb '25

02 Feb '25

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/86244?usp=email ) Change subject: superio/fintek: Add Fintek F81801 ...................................................................... superio/fintek: Add Fintek F81801 Change-Id: I0ba4ad52878615011bcc162fedf779e6d014d20d Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/superio/fintek/Makefile.mk A src/superio/fintek/f81801/Kconfig A src/superio/fintek/f81801/Makefile.mk A src/superio/fintek/f81801/f81801.h A src/superio/fintek/f81801/superio.c 5 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/86244/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba4ad52878615011bcc162fedf779e6d014d20d Gerrit-Change-Number: 86244 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/up: Add UP Xtreme mainboard
by Felix Singer (Code Review) 02 Feb '25

02 Feb '25

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86245?usp=email ) Change subject: mb/up: Add UP Xtreme mainboard ...................................................................... mb/up: Add UP Xtreme mainboard Change-Id: I0385db8ca798ade5ba90f534134f7fd860fe1aa8 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A src/mainboard/up/xtreme_whl/Kconfig A src/mainboard/up/xtreme_whl/Kconfig.name A src/mainboard/up/xtreme_whl/Makefile.mk A src/mainboard/up/xtreme_whl/board_info.txt A src/mainboard/up/xtreme_whl/bootblock.c A src/mainboard/up/xtreme_whl/data.vbt A src/mainboard/up/xtreme_whl/devicetree.cb A src/mainboard/up/xtreme_whl/dsdt.asl A src/mainboard/up/xtreme_whl/gma-mainboard.ads A src/mainboard/up/xtreme_whl/gpio.c A src/mainboard/up/xtreme_whl/gpio_early.c A src/mainboard/up/xtreme_whl/hda_verb.c A src/mainboard/up/xtreme_whl/include/mainboard/early_stages.h A src/mainboard/up/xtreme_whl/include/mainboard/ramstage.h A src/mainboard/up/xtreme_whl/ramstage.c A src/mainboard/up/xtreme_whl/romstage.c A src/mainboard/up/xtreme_whl/spd/4g.spd.hex A src/mainboard/up/xtreme_whl/spd/8g.spd.hex 18 files changed, 268 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/86245/1 diff --git a/src/mainboard/up/xtreme_whl/Kconfig b/src/mainboard/up/xtreme_whl/Kconfig new file mode 100644 index 0000000..1d1502e --- /dev/null +++ b/src/mainboard/up/xtreme_whl/Kconfig @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_UP_XTREME_WHL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +# select HAVE_CMOS_DEFAULT # TODO +# select HAVE_OPTION_TABLE # TODO + select HAVE_SPD_IN_CBFS # TODO + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NO_UART_ON_SUPERIO + select SOC_INTEL_WHISKEYLAKE + select SUPERIO_FINTEK_F81801 + +config MAINBOARD_DIR + default "up/xtreme_whl" + +config MAINBOARD_PART_NUMBER + default "Xtreme" + +config UART_FOR_CONSOLE + default 0 + +config POST_IO + default n + +config POST_DEVICE + default n + +config CONSOLE_POST + default y + +endif diff --git a/src/mainboard/up/xtreme_whl/Kconfig.name b/src/mainboard/up/xtreme_whl/Kconfig.name new file mode 100644 index 0000000..d22fba4 --- /dev/null +++ b/src/mainboard/up/xtreme_whl/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_UP_XTREME_WHL + bool "Xtreme Whiskey Lake" diff --git a/src/mainboard/up/xtreme_whl/Makefile.mk b/src/mainboard/up/xtreme_whl/Makefile.mk new file mode 100644 index 0000000..986befd --- /dev/null +++ b/src/mainboard/up/xtreme_whl/Makefile.mk @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +SPD_SOURCES += 4g +SPD_SOURCES += 8g diff --git a/src/mainboard/up/xtreme_whl/board_info.txt b/src/mainboard/up/xtreme_whl/board_info.txt new file mode 100644 index 0000000..e361f9f --- /dev/null +++ b/src/mainboard/up/xtreme_whl/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Up +Board name: Xtreme +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/up/xtreme_whl/bootblock.c b/src/mainboard/up/xtreme_whl/bootblock.c new file mode 100644 index 0000000..8cab844 --- /dev/null +++ b/src/mainboard/up/xtreme_whl/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <mainboard/early_stages.h> + +void bootblock_mainboard_early_init(void) +{ + configure_early_gpios(); +} diff --git a/src/mainboard/up/xtreme_whl/data.vbt b/src/mainboard/up/xtreme_whl/data.vbt new file mode 100644 index 0000000..c1b3548 --- /dev/null +++ b/src/mainboard/up/xtreme_whl/data.vbt Binary files differ diff --git a/src/mainboard/up/xtreme_whl/devicetree.cb b/src/mainboard/up/xtreme_whl/devicetree.cb new file mode 100644 index 0000000..cb89335 --- /dev/null +++ b/src/mainboard/up/xtreme_whl/devicetree.cb @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/cannonlake + device domain 0 on + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref xhci on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + end + device ref emmc on end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp14 on end + device ref pcie_rp15 on end + device ref pcie_rp16 on end + device ref uart0 on end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end + end +end diff --git a/src/mainboard/up/xtreme_whl/dsdt.asl b/src/mainboard/up/xtreme_whl/dsdt.asl new file mode 100644 index 0000000..392a79a --- /dev/null +++ b/src/mainboard/up/xtreme_whl/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/up/xtreme_whl/gma-mainboard.ads b/src/mainboard/up/xtreme_whl/gma-mainboard.ads new file mode 100644 index 0000000..e0a166f --- /dev/null +++ b/src/mainboard/up/xtreme_whl/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/up/xtreme_whl/gpio.c b/src/mainboard/up/xtreme_whl/gpio.c new file mode 100644 index 0000000..ac06144 --- /dev/null +++ b/src/mainboard/up/xtreme_whl/gpio.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/gpio.h> +#include <mainboard/ramstage.h> + +static const struct pad_config gpio_table[] = { 0 }; + +void configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/up/xtreme_whl/gpio_early.c b/src/mainboard/up/xtreme_whl/gpio_early.c new file mode 100644 index 0000000..26d87d4 --- /dev/null +++ b/src/mainboard/up/xtreme_whl/gpio_early.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/gpio.h> +#include <mainboard/early_stages.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPI(GPP_A18, NONE, DEEP), /* DDR_ID1 */ + PAD_CFG_GPI(GPP_A23, NONE, DEEP), /* DDR_ID2 */ + PAD_CFG_GPI(GPP_C8, NONE, DEEP), /* BRD_ID0 */ + PAD_CFG_GPI(GPP_C9, NONE, DEEP), /* BRD_ID1 */ + PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* BRD_ID2 */ + PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* DDR_ID0 */ +}; + +void configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/up/xtreme_whl/hda_verb.c b/src/mainboard/up/xtreme_whl/hda_verb.c new file mode 100644 index 0000000..d3619ab --- /dev/null +++ b/src/mainboard/up/xtreme_whl/hda_verb.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { }; + +const u32 pc_beep_verbs[] = { }; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/up/xtreme_whl/include/mainboard/early_stages.h b/src/mainboard/up/xtreme_whl/include/mainboard/early_stages.h new file mode 100644 index 0000000..bc476af --- /dev/null +++ b/src/mainboard/up/xtreme_whl/include/mainboard/early_stages.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +void configure_early_gpios(void); diff --git a/src/mainboard/up/xtreme_whl/include/mainboard/ramstage.h b/src/mainboard/up/xtreme_whl/include/mainboard/ramstage.h new file mode 100644 index 0000000..2029d0f --- /dev/null +++ b/src/mainboard/up/xtreme_whl/include/mainboard/ramstage.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +void configure_gpios(void); diff --git a/src/mainboard/up/xtreme_whl/ramstage.c b/src/mainboard/up/xtreme_whl/ramstage.c new file mode 100644 index 0000000..f0daa93 --- /dev/null +++ b/src/mainboard/up/xtreme_whl/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <mainboard/ramstage.h> + +static void init_mainboard(void *chip_info) +{ + configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/up/xtreme_whl/romstage.c b/src/mainboard/up/xtreme_whl/romstage.c new file mode 100644 index 0000000..73fa78e --- /dev/null +++ b/src/mainboard/up/xtreme_whl/romstage.c @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/up/xtreme_whl/spd/4g.spd.hex b/src/mainboard/up/xtreme_whl/spd/4g.spd.hex new file mode 100644 index 0000000..8642bc1 --- /dev/null +++ b/src/mainboard/up/xtreme_whl/spd/4g.spd.hex @@ -0,0 +1,32 @@ +23 11 0c 03 45 21 00 08 00 60 00 03 02 03 80 00 +00 00 07 0d f8 0f 00 00 6e 6e 6e 11 00 6e f0 0a +20 08 00 05 00 f0 2b 34 28 00 78 00 14 3c 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0b 35 +16 36 0b 35 00 00 16 36 0b 35 16 36 0b 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9c b5 00 00 00 00 e7 d6 b8 4a +0f 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 e2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +08 f7 4b 00 00 00 00 00 00 44 34 53 53 31 32 31 +36 31 53 48 32 34 41 2d 42 20 20 20 20 00 80 ce +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/up/xtreme_whl/spd/8g.spd.hex b/src/mainboard/up/xtreme_whl/spd/8g.spd.hex new file mode 100644 index 0000000..b28d68b --- /dev/null +++ b/src/mainboard/up/xtreme_whl/spd/8g.spd.hex @@ -0,0 +1,32 @@ +23 11 0c 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 07 0d f8 0f 00 00 6e 6e 6e 11 00 6e f0 0a +20 08 00 05 00 a8 1b 28 28 00 78 00 14 3c 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0b 35 +16 36 0b 35 00 00 16 36 0b 35 16 36 0b 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9c b5 00 00 00 00 e7 d6 89 02 +0f 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 e2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 ad 01 00 00 00 00 00 00 48 4d 41 41 35 31 53 +36 41 4d 52 36 4e 2d 55 48 20 20 20 20 00 80 ad +ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 dd 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/86245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0385db8ca798ade5ba90f534134f7fd860fe1aa8 Gerrit-Change-Number: 86245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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