coreboot-gerrit February 2025

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[S] Change in coreboot[main]: intel/acpi: Put BSP as the first entry
by Vladimir Serbinenko (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Intel coreboot Reviewers. Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86247?usp=email ) Change subject: intel/acpi: Put BSP as the first entry ...................................................................... intel/acpi: Put BSP as the first entry Linux complains in dmesg as a firmware bug that BSP is not the first entry. NetBSD hangs and OpenBSD panics early on boot. With this patch I was able to boot NetBSD and OpenBSD on darp10-b when loaded in GRUB. Note: vanilla bootloaders for NetBSD and OpenBSD still result in an apparent hang for an unknown reason. Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/86247/1 diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index ee4777a..a6b9c21 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -48,10 +48,17 @@ int32_t eff_apic_ids[CONFIG_MAX_CPUS] = {0}; extern struct cpu_info cpu_infos[]; uint32_t i, j = 0; + u32 bsp_lapicid = lapicid(); + + /* As per spec first comes BSP. */ + cpu_apic_info.apic_ids[0] = bsp_lapicid; + perf_core_cnt = 1; for (i = 0; i < ARRAY_SIZE(cpu_apic_info.apic_ids); i++) { if (!cpu_infos[i].cpu) continue; + if (cpu_infos[i].cpu->path.apic.apic_id == bsp_lapicid) + continue; if (cpu_infos[i].cpu->path.apic.core_type == CPU_TYPE_PERF) cpu_apic_info.apic_ids[perf_core_cnt++] = cpu_infos[i].cpu->path.apic.apic_id; @@ -60,8 +67,8 @@ cpu_infos[i].cpu->path.apic.apic_id; } - if (perf_core_cnt > 1) - bubblesort(cpu_apic_info.apic_ids, perf_core_cnt, NUM_ASCENDING); + if (perf_core_cnt > 2) + bubblesort(cpu_apic_info.apic_ids + 1, perf_core_cnt - 1, NUM_ASCENDING); for (i = perf_core_cnt; j < eff_core_cnt; i++, j++) cpu_apic_info.apic_ids[i] = eff_apic_ids[j]; -- To view, visit https://review.coreboot.org/c/coreboot/+/86247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Gerrit-Change-Number: 86247 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[S] Change in coreboot[main]: acpi: Zero-out MADT before filling it
by Vladimir Serbinenko (Code Review) 03 Feb '25

03 Feb '25

Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86246?usp=email ) Change subject: acpi: Zero-out MADT before filling it ...................................................................... acpi: Zero-out MADT before filling it Otherwise flags field is pre-filled with random garbage. Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e --- M 3rdparty/arm-trusted-firmware M 3rdparty/blobs M 3rdparty/fsp M 3rdparty/intel-microcode M 3rdparty/vboot M src/acpi/acpi.c 6 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/86246/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 15e5c6c..48f1bc9 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 15e5c6c91d483aa52908154cc80e48956e234232 +Subproject commit 48f1bc9f52491d51ca92a1d396ccbe6a9d09e780 diff --git a/3rdparty/blobs b/3rdparty/blobs index 14f8fcc..a8db7df 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 14f8fcc1b426cb0884a21a9b715da6e0c1c7f434 +Subproject commit a8db7dfe823def043368857b8fbfbba86f2e9e47 diff --git a/3rdparty/fsp b/3rdparty/fsp index 15c0f7b..cc6399e 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 15c0f7b3f723bcd713e5ab11ebc502f30d9084e7 +Subproject commit cc6399e8c759ad4ed83c2d6ea568fd918fc9bc06 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 8ac9378..5278dfc 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 8ac9378a84879e81c503e09f344560b3dd7f72df +Subproject commit 5278dfcf98e89098326b3eb8a85d07120a8730f8 diff --git a/3rdparty/vboot b/3rdparty/vboot index 3f94e2c..09fcd21 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 3f94e2c7ed58c4e67d6e7dc6052ec615dbbb9bb4 +Subproject commit 09fcd2184f9c714829503e84b8a7dfe7f2584e00 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index ffd9b79..8f5c09f 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -138,6 +138,8 @@ acpi_madt_t *madt = (acpi_madt_t *)header; unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t); + memset(madt, 0, sizeof(*madt)); + if (acpi_fill_header(header, "APIC", MADT, sizeof(acpi_madt_t)) != CB_SUCCESS) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/86246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e Gerrit-Change-Number: 86246 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com>

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Subrata Banik (Code Review) 03 Feb '25

03 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... drivers/soc/cse: Fix overflow in CSE telemetry calculation MSEC_TO_USEC(cse_perf_data.timestamp[i]) does overflow. Here is an example, if cse_perf_data.timestamp[i] value is 4304903 milliseconds. When multiplied by 1000 to convert to microseconds, the value becomes 0x979B58 instead of 0x100979B58. TEST=Boot to OS Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86215 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/cse/telemetry.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/telemetry.c b/src/soc/intel/common/block/cse/telemetry.c index 2c9fb54..62814eb 100644 --- a/src/soc/intel/common/block/cse/telemetry.c +++ b/src/soc/intel/common/block/cse/telemetry.c @@ -4,7 +4,7 @@ #include <intelblocks/cse.h> #include <timestamp.h> -#define MSEC_TO_USEC(x) (x * 1000) +#define MSEC_TO_USEC(x) ((s64)x * 1000) enum cb_err cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brya/var/craaskov: Add/select VBT
by Matt DeVillier (Code Review) 02 Feb '25

02 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86214?usp=email ) Change subject: mb/google/brya/var/craaskov: Add/select VBT ...................................................................... mb/google/brya/var/craaskov: Add/select VBT Add VBT data file for craaskov, and enable its use by selecting INTEL_GMA_HAVE_VBT. VBT extracted from stock firmware image Google_Craaskov.15217.616.0; it has BDB version 2.51, which matches the current FSP binaries. TEST=build/boot craaskov with edk2 payload Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/variants/craaskov/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d32435b..dfa571e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -201,6 +201,7 @@ config BOARD_GOOGLE_CRAASKOV select BOARD_GOOGLE_BASEBOARD_NISSA + select INTEL_GMA_HAVE_VBT select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_CONSTITUTION diff --git a/src/mainboard/google/brya/variants/craaskov/data.vbt b/src/mainboard/google/brya/variants/craaskov/data.vbt new file mode 100644 index 0000000..c47b424 --- /dev/null +++ b/src/mainboard/google/brya/variants/craaskov/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/86214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b Gerrit-Change-Number: 86214 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com>

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[S] Change in coreboot[main]: mb/starlabs/byte_adl: Disconnect unused GPIOs
by Matt DeVillier (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86134?usp=email ) Change subject: mb/starlabs/byte_adl: Disconnect unused GPIOs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4c2c32c0740e2ad763881f3f4d5920387f49c79 Gerrit-Change-Number: 86134 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 02 Feb 2025 22:46:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/amd/birman_plus/ec: Rectify ECRAM register bits
by Ana Carolina Cabral (Code Review) 02 Feb '25

02 Feb '25

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[M] Change in coreboot[main]: mb/amd/birman_plus/ec: Rectify ECRAM register bits
by Ana Carolina Cabral (Code Review) 02 Feb '25

02 Feb '25

Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/86084?usp=email ) Change subject: mb/amd/birman_plus/ec: Rectify ECRAM register bits ...................................................................... Patch Set 14: (6 comments) File src/mainboard/amd/birman_plus/ec.c: https://review.coreboot.org/c/coreboot/+/86084/comment/c0b9a636_ec15bf9c?us… : PS13, Line 11: #define EC_GPIO_0_ADDR 0xA0 > the defines are added, but not used in the code; is this intended? I thought about only enabling 19V if the eval card was present, but when I saw it was configurable I was not so sure. Added it to this patch. https://review.coreboot.org/c/coreboot/+/86084/comment/d923f27d_158ac1e9?us… : PS13, Line 36: _N > i don't think that this one is inverted. sure, the signal on the m. […] Done https://review.coreboot.org/c/coreboot/+/86084/comment/926679f0_853efc80?us… : PS13, Line 127: EC7_WL_RADIO_DIS_N > see my comment on the register bit; i'd expect this one needing to be cleared, not set Done https://review.coreboot.org/c/coreboot/+/86084/comment/bf1796c8_d196ae24?us… : PS13, Line 138: tmp = ECA_MUX1_S0 | ECA_SMBUS1_EN | ECA_SMBUS0_EN; > would probably be good to configure the other muxes here too Done https://review.coreboot.org/c/coreboot/+/86084/comment/17bfa07e_5712fcb1?us… : PS13, Line 142: tmp = ec_read(EC_GPIO_6_ADDR); : tmp |= EC6_TPNL_BUF_EN | EC6_TPAD_BUF_EN; : printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_6_ADDR, tmp); : ec_write(EC_GPIO_6_ADDR, tmp); > i'd move this block between the ones for EC_GPIO_3_ADDR and EC_GPIO_7_ADDR Done https://review.coreboot.org/c/coreboot/+/86084/comment/c8e7d93a_ec4ebeb7?us… : PS13, Line 156: if (CONFIG(DISABLE_WWAN_GBE_BIRMANPLUS)) { // no WWAN, turn off WWAN power > i'd find it a bit easier to read when doing the bit clear/bit set in the if/else branches and not ha […] Well, I personally prefer the default values being set first, but here you go.. -- To view, visit https://review.coreboot.org/c/coreboot/+/86084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471 Gerrit-Change-Number: 86084 Gerrit-PatchSet: 14 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 02 Feb 2025 22:00:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/amd/birman_plus/ec: Rectify ECRAM register bits
by Ana Carolina Cabral (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Ana Carolina Cabral. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86084?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/amd/birman_plus/ec: Rectify ECRAM register bits ...................................................................... mb/amd/birman_plus/ec: Rectify ECRAM register bits Rectify wrong EC module RAM registers bits based on PI source code 1.0.0.1b Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/mainboard/amd/birman_plus/ec.c 1 file changed, 48 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86084/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/86084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471 Gerrit-Change-Number: 86084 Gerrit-PatchSet: 14 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com>

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update PCIe Slot configurations
by Ana Carolina Cabral (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Maximilian Brune, Nick Kochlowski. Hello Felix Held, Maximilian Brune, Nick Kochlowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85493?usp=email to look at the new patch set (#23). The following approvals got outdated and were removed: Code-Review+1 by Nick Kochlowski, Code-Review+2 by Felix Held, Code-Review+2 by Maximilian Brune, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/amd/birman_plus: Update PCIe Slot configurations ...................................................................... mb/amd/birman_plus: Update PCIe Slot configurations Rectify board configuration flags based on the schematics Doc. 105-D99700-00C and User Guide #58168 (NDA). Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/ec.c M src/mainboard/amd/birman_plus/port_descriptors_glinda.c M src/mainboard/amd/birman_plus/port_descriptors_phoenix.c 4 files changed, 81 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85493/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/85493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Gerrit-Change-Number: 85493 Gerrit-PatchSet: 23 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: superio/fintek: Add Fintek F81801
by Felix Singer (Code Review) 02 Feb '25

02 Feb '25

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/86244?usp=email ) Change subject: superio/fintek: Add Fintek F81801 ...................................................................... superio/fintek: Add Fintek F81801 Change-Id: I0ba4ad52878615011bcc162fedf779e6d014d20d Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/superio/fintek/Makefile.mk A src/superio/fintek/f81801/Kconfig A src/superio/fintek/f81801/Makefile.mk A src/superio/fintek/f81801/f81801.h A src/superio/fintek/f81801/superio.c 5 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/86244/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba4ad52878615011bcc162fedf779e6d014d20d Gerrit-Change-Number: 86244 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit February 2025