coreboot-gerrit February 2025

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[M] Change in coreboot[main]: superio/fintek: Add Fintek F81801
by Felix Singer (Code Review) 02 Feb '25

02 Feb '25

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86244?usp=email ) Change subject: superio/fintek: Add Fintek F81801 ...................................................................... superio/fintek: Add Fintek F81801 Change-Id: I0ba4ad52878615011bcc162fedf779e6d014d20d Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/superio/fintek/Makefile.mk A src/superio/fintek/f81801/Kconfig A src/superio/fintek/f81801/Makefile.mk A src/superio/fintek/f81801/f81801.h A src/superio/fintek/f81801/superio.c 5 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/86244/1 diff --git a/src/superio/fintek/Makefile.mk b/src/superio/fintek/Makefile.mk index b9cfe4d..ed68135 100644 --- a/src/superio/fintek/Makefile.mk +++ b/src/superio/fintek/Makefile.mk @@ -11,3 +11,4 @@ subdirs-y += f81865f subdirs-y += f81866d subdirs-y += f81803a +subdirs-y += f81801 diff --git a/src/superio/fintek/f81801/Kconfig b/src/superio/fintek/f81801/Kconfig new file mode 100644 index 0000000..d59d641 --- /dev/null +++ b/src/superio/fintek/f81801/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config SUPERIO_FINTEK_F81801 + bool + select SUPERIO_FINTEK_COMMON_PRE_RAM diff --git a/src/superio/fintek/f81801/Makefile.mk b/src/superio/fintek/f81801/Makefile.mk new file mode 100644 index 0000000..63b7339 --- /dev/null +++ b/src/superio/fintek/f81801/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81801) += superio.c diff --git a/src/superio/fintek/f81801/f81801.h b/src/superio/fintek/f81801/f81801.h new file mode 100644 index 0000000..35cef61 --- /dev/null +++ b/src/superio/fintek/f81801/f81801.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_FINTEK_F81801_H +#define SUPERIO_FINTEK_F81801_H + +#define F81801_LDN_UART1 0x01 +#define F81801_LDN_UART2 0x02 +#define F81801_LDN_HWM 0x04 +#define F81801_LDN_KBC 0x05 +#define F81801_LDN_GPIO 0x06 +#define F81801_LDN_WDT 0x07 +#define F81801_LDN_SPI 0x08 +#define F81801_LDN_PME 0x0a + +#endif /* SUPERIO_FINTEK_F81801_H */ diff --git a/src/superio/fintek/f81801/superio.c b/src/superio/fintek/f81801/superio.c new file mode 100644 index 0000000..8cf62db --- /dev/null +++ b/src/superio/fintek/f81801/superio.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <pc80/keyboard.h> + +#include "f81801.h" + +static void f81801_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case F81801_LDN_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81801_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, F81801_LDN_UART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xffff }, + { NULL, F81801_LDN_UART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1, 0xffff }, + { NULL, F81801_LDN_HWM, PNP_IO0 | PNP_IRQ0, 0xffff }, + { NULL, F81801_LDN_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0 | PNP_MSCE, 0xffff }, + { NULL, F81801_LDN_GPIO, PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 }, + { NULL, F81801_LDN_WDT, PNP_IO0 | PNP_MSC0 | PNP_MSC5 | PNP_MSC6 | PNP_MSCA, 0xffff }, + { NULL, F81801_LDN_SPI, PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 | PNP_MSC8 | PNP_MSCA | PNP_MSCB | PNP_MSCC | PNP_MSCD | PNP_MSCE }, + { NULL, F81801_LDN_PME, PNP_MSC0 | PNP_MSC1 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81801_ops = { + CHIP_NAME("Fintek F81801 Super I/O") + .enable_dev = enable_dev +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/86244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba4ad52878615011bcc162fedf779e6d014d20d Gerrit-Change-Number: 86244 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Felix Singer (Code Review) 02 Feb '25

02 Feb '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85851?usp=email ) Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... 3rdparty/fsp: Update submodule to upstream master Updating from commit id 909cf43ad6cc: 2024-12-09 14:08:48 +0800 - (IoT ADL-N IPU25.1 (5354_00)) to commit id 15c0f7b3f723: 2025-01-21 12:24:27 +0800 - (ECG ARL-S PV (4400_43) FSP) This brings in 9 new commits: 15c0f7b3f723 ECG ARL-S PV (4400_43) FSP e542b00a36e7 ECG ARL-S PV (4400_43) FSP 055303ae55d9 Create MemInfoHob.txt 5662d38d8834 ECG ARL-S PV (4400_43) FSP 5cc0b60a8a49 NEX ADL-PS IPU 2025.1 (5401_01) FSP 087dc181a47a IoT ADL-N MR6 (5481_00) fa3362bf4896 Merge branch 'master' of https://github.com/intel/FSP 0a9eafc9737b IoT ADL-N MR6 (5481_00) e276be95bac3 NEX MTL-UH_MTL-PS MR2 (4122_56) FSP Change-Id: I2d04308773ccc99983275355c928cd01b034da26 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85851 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/3rdparty/fsp b/3rdparty/fsp index 909cf43..15c0f7b 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 909cf43ad6ccebb6adee482bc0a4f098c32c9a6d +Subproject commit 15c0f7b3f723bcd713e5ab11ebc502f30d9084e7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85851?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d04308773ccc99983275355c928cd01b034da26 Gerrit-Change-Number: 85851 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[S] Change in coreboot[main]: mb/starlabs/byte_adl: Disconnect unused GPIOs
by Sean Rhodes (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Matt DeVillier, Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86134?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Matt DeVillier, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/starlabs/byte_adl: Disconnect unused GPIOs ...................................................................... mb/starlabs/byte_adl: Disconnect unused GPIOs Change-Id: Ie4c2c32c0740e2ad763881f3f4d5920387f49c79 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/86134/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4c2c32c0740e2ad763881f3f4d5920387f49c79 Gerrit-Change-Number: 86134 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Show ASPM related options in CFR
by Sean Rhodes (Code Review) 02 Feb '25

02 Feb '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86239?usp=email ) Change subject: mb/starlabs/starbook/mtl: Show ASPM related options in CFR ...................................................................... mb/starlabs/starbook/mtl: Show ASPM related options in CFR Meteor Lake uses the same helper functon as Alder Lake, so it can be configured via the opton API. Change-Id: I6d1dc802e672431aa643e318a7cb045f7d6eaa06 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86239 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/cfr.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c index 7316f2a..82488fe 100644 --- a/src/mainboard/starlabs/starbook/cfr.c +++ b/src/mainboard/starlabs/starbook/cfr.c @@ -200,7 +200,7 @@ }); #endif -#if CONFIG(SOC_INTEL_ALDERLAKE) +#if CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_METEORLAKE) static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({ .opt_name = "pciexp_aspm", .ui_name = "PCI ASPM", @@ -351,7 +351,7 @@ #if CONFIG(BOARD_STARLABS_STARBOOK_ADL) &pci_hot_plug, #endif - #if CONFIG(SOC_INTEL_ALDERLAKE) + #if CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_METEORLAKE) &pciexp_clk_pm, &pciexp_aspm, &pciexp_l1ss, -- To view, visit https://review.coreboot.org/c/coreboot/+/86239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d1dc802e672431aa643e318a7cb045f7d6eaa06 Gerrit-Change-Number: 86239 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Allow controlling the power LED brightness
by Sean Rhodes (Code Review) 02 Feb '25

02 Feb '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86240?usp=email ) Change subject: mb/starlabs/starlite_adl: Allow controlling the power LED brightness ...................................................................... mb/starlabs/starlite_adl: Allow controlling the power LED brightness Add an option to selected a reduced brightness for the power LED. The EC code will use this option to write to the relavant offset accordingly. Change-Id: I4796e0572a48bca5f9c59e96466416e975cfe8ca Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86240 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starlite_adl/cfr.c 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c index 69635bb..58a09a3 100644 --- a/src/mainboard/starlabs/starlite_adl/cfr.c +++ b/src/mainboard/starlabs/starlite_adl/cfr.c @@ -193,6 +193,18 @@ }); #endif +static const struct sm_object power_led = SM_DECLARE_ENUM({ + .opt_name = "power_led", + .ui_name = "Power LED Brightness", + .ui_helptext = "Control the maximum brightness of the power LED", + .default_value = 0, + .values = (const struct sm_enum_value[]) { + { "Normal", 0 }, + { "Reduced", 1 }, + SM_ENUM_VALUE_END, + }, +}); + static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({ .opt_name = "reboot_counter", .ui_name = "Reboot Counter", @@ -254,6 +266,7 @@ #if CONFIG(EC_STARLABS_CHARGING_SPEED) &charging_speed, #endif + &power_led, &power_on_after_fail, NULL }, -- To view, visit https://review.coreboot.org/c/coreboot/+/86240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4796e0572a48bca5f9c59e96466416e975cfe8ca Gerrit-Change-Number: 86240 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brya/var/craaskov: Add/select VBT
by Kapil Porwal (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Matt DeVillier, Maxim Polyakov, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86214?usp=email ) Change subject: mb/google/brya/var/craaskov: Add/select VBT ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b Gerrit-Change-Number: 86214 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 02 Feb 2025 18:28:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Kapil Porwal (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Bora Guvendik, Dinesh Gehlot, Intel coreboot Reviewers. Kapil Porwal has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Sun, 02 Feb 2025 18:23:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: tree: Use true, false for DspEnable
by Maxim Polyakov (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Elyes Haouas, Jonathon Hall, Michał Żygowski, Piotr Król. Maxim Polyakov has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86189?usp=email ) Change subject: tree: Use true, false for DspEnable ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5bab9db3632848f92732160bb821dda8cdb14281 Gerrit-Change-Number: 86189 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Sun, 02 Feb 2025 16:08:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: tree: Use boolean for PchHdaDspEnable
by Maxim Polyakov (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Angel Pons, Christian Walter, Elyes Haouas, Intel coreboot Reviewers, Jonathon Hall, Nick Vaccaro, Patrick Rudolph, Subrata Banik, Werner Zeh. Maxim Polyakov has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86190?usp=email ) Change subject: tree: Use boolean for PchHdaDspEnable ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47852c9b023cc4839000019b8a932b6e471fa839 Gerrit-Change-Number: 86190 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 02 Feb 2025 16:07:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: tree: Use true false for PcieRpEnable[]
by Maxim Polyakov (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Angel Pons, Christian Walter, Elyes Haouas, Frans Hendriks, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Subrata Banik, Tim Crawford. Maxim Polyakov has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86192?usp=email ) Change subject: tree: Use true false for PcieRpEnable[] ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528 Gerrit-Change-Number: 86192 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 02 Feb 2025 16:05:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit February 2025