coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: include/commonlib/sot.h: Add SOT structs
by Patrick Rudolph (Code Review) 02 Feb '25

02 Feb '25

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77882?usp=email ) Change subject: include/commonlib/sot.h: Add SOT structs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/77882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f006318a15556f97da286dc032c58ccb7993e4 Gerrit-Change-Number: 77882 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com>

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[L] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers from 2431.00 to 2454.00
by Jayvik Desai (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Alok Agarwal, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik, Vikrant L Jadeja. Jayvik Desai has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/85750?usp=email ) The change is no longer submittable: Code-Review is unsatisfied now. Change subject: vc/intel/fsp: Update PTL FSP headers from 2431.00 to 2454.00 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85750?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788a0d2373593bc7bd447dd37150ec4fda6d6bb4 Gerrit-Change-Number: 85750 Gerrit-PatchSet: 4 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 02 Feb 2025 12:00:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers from 2431.00 to 2454.00
by Jayvik Desai (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Alok Agarwal, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik, Vikrant L Jadeja. Jayvik Desai has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/85750?usp=email ) Change subject: vc/intel/fsp: Update PTL FSP headers from 2431.00 to 2454.00 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85750?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788a0d2373593bc7bd447dd37150ec4fda6d6bb4 Gerrit-Change-Number: 85750 Gerrit-PatchSet: 4 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 02 Feb 2025 12:00:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Elyes Haouas (Code Review) 02 Feb '25

02 Feb '25

Attention is currently required from: Felix Singer. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85851?usp=email ) Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85851?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d04308773ccc99983275355c928cd01b034da26 Gerrit-Change-Number: 85851 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Sun, 02 Feb 2025 08:58:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Nicholas Chin (Code Review) 01 Feb '25

01 Feb '25

Attention is currently required from: Angel Pons, Keith Hui. Nicholas Chin has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > I see that the ASM1061 is detected in the PS 4 log. […] Looks like GPIO 5 is reset by either RSMRST# (pin 101) or SLPS5# (pin 84) depending on the setting in LDN 0xA (ACPI) register 0xE9[5] (default 0=RSMRST#). Calling `system_reset()` `#include <cf9_reset.h>` should cause the PCH to assert PLTRST# which is connected to pin 26 LRESET# on the SuperIO, so GPIO5 should maintain its values after calling that funciton. The SuperIO also buffers the LRESET# signal to those reset outputs on GPIO bank 7, of which RSTOUT2# (pin 77) goes to the PCIe slots. I guess some logic in `early_init.c` would need to be added to check the configuration of the SuperIO GPIOs and reset the system after changing them, otherwise continue booting if they are already at the desired values. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Feb 2025 06:48:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Nicholas Chin (Code Review) 01 Feb '25

01 Feb '25

Attention is currently required from: Angel Pons, Keith Hui. Nicholas Chin has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > After rebuilding PS 6 and reprogramming the flash with an external programmer, PS 6 becomes stabler, […] I see that the ASM1061 is detected in the PS 4 log. In the log for PS 6, the chipset does seem to know that something is connected to root port 3, but isn't able to enumerate it: ``` [DEBUG] PCI: 00:00:1c.3 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 03 [INFO ] POST: 0x24 [INFO ] POST: 0x25 [INFO ] PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port [WARN ] PCI: 00:00:1c.3: Has a slow downstream device. Enumeration failed. [DEBUG] scan_bus: bus PCI: 00:00:1c.3 finished in 26 msecs ``` As far as I can tell the GPIO 5 levels for each mode are correct, and setting them to push pull is also correct. The only other thing I can think is doing some sort of soft reset of the system after setting the GPIOs such that the SuperIO doesn't get reset and maintains the output states. Perhaps switching the PCIe muxes at runtime makes the chipset or card unhappy without resetting the bus. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Feb 2025 06:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Bill XIE (Code Review) 01 Feb '25

01 Feb '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Which really carries the key fix. […] After rebuilding PS 6 and reprogramming the flash with an external programmer, PS 6 becomes stabler, except that it still failed to boot Linux kernel occasionally (about once within six trials). The card on PCIEX1_2 remains not well detected. The corresponding autoport dump (including cbmem log) is at https://send.aslaets.be/download/33957009a165153f/#9EcjFk2dlN9HUreIZkv93A , downloadable 10 times in 10 days, and the console log of PS 4 is at https://0bin.net/paste/c7pN6Mle#b4dbLyg54j3UrAb9DqV761gg7ioUbZ60CvbAkDkrttO -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Feb 2025 04:50:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 31 Jan '25

31 Jan '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > > Since which patch set did it start to fail? […] Which really carries the key fix. I'll need to see a console log again with latest patch set and PS 4 if you can. I cannot reproduce from my end, because on my P8Z77-V LE+ it's a PCH GPIO that's doing the job, and my Sabertooth suffered trace damage and is a bust. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Feb 2025 06:31:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/denverton_ns: Remove unused memcpy_s function
by Elyes Haouas (Code Review) 31 Jan '25

31 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86233?usp=email ) Change subject: soc/intel/denverton_ns: Remove unused memcpy_s function ...................................................................... soc/intel/denverton_ns: Remove unused memcpy_s function Remove the memcpy_s function as it is not used. Additionally, the function did not return the expected values: 0: If the memory copy is successful. EINVAL: If dest or src is a null pointer, or if count is greater than RSIZE_MAX. ERANGE: If count is greater than destsz. Change-Id: I0d32c838e94ae760907efe55ed00bab3faaaa8c5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86233 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/intel/denverton_ns/include/soc/soc_util.h M src/soc/intel/denverton_ns/soc_util.c 2 files changed, 0 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Maximilian Brune: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h index 5b7a75d..d38737d 100644 --- a/src/soc/intel/denverton_ns/include/soc/soc_util.h +++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h @@ -35,11 +35,6 @@ uint16_t get_pmbase(void); uint16_t get_tcobase(void); -/* -* Secure functions. -*/ -void *memcpy_s(void *dest, const void *src, size_t n); - void mmio_andthenor32(void *addr, uint32_t val2and, uint32_t val2or); uint8_t silicon_stepping(void); diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index dbe924b..22e9471 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -238,52 +238,3 @@ return revision_id; } - -void *memcpy_s(void *dest, const void *src, size_t n) -{ - uint8_t *dp; - const uint8_t *sp; - - dp = (uint8_t *)dest; - sp = (uint8_t *)src; - - if (!n) - return dest; - - if (n > UINT32_MAX) - return dest; - - if (!dp) - return dest; - - if (!sp) - return dest; - - /* - * overlap is undefined behavior, do not allow - */ - if (((dp > sp) && (dp < (sp + n))) || ((sp > dp) && (sp < (dp + n)))) - return dest; - - /* - * now perform the copy - */ - - /* Original memcpy() function */ - unsigned long d0, d1, d2; - - asm volatile( -#if ENV_X86_64 - "rep ; movsd\n\t" - "mov %4,%%rcx\n\t" -#else - "rep ; movsl\n\t" - "movl %4,%%ecx\n\t" -#endif - "rep ; movsb\n\t" - : "=&c"(d0), "=&D"(d1), "=&S"(d2) - : "0"(n >> 2), "g"(n & 3), "1"(dest), "2"(src) - : "memory"); - - return dest; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/86233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d32c838e94ae760907efe55ed00bab3faaaa8c5 Gerrit-Change-Number: 86233 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Bill XIE (Code Review) 31 Jan '25

31 Jan '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Since which patch set did it start to fail? patch set 5. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Feb 2025 03:12:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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coreboot-gerrit February 2025