coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/adl: Display low battery message on screen
by Karthik Ramasubramanian (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86224?usp=email ) Change subject: soc/intel/adl: Display low battery message on screen ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > BTW why is all this code in `intel/alderlake`? Shouldn't it be in `intel/common` instead? It doesn't […] For alderlake platforms alone, libgfxinit is used for early (pre-ram stages) notification. On subsequent Intel platforms, I think Intel stopped supporting libgfxinit and instead ugop is used. Also the plan is to start with Alderlake programs (eg. Brox). Hence the changes are done in alderlake. As this feature gets rolled out to subsequent programs, I think any common code will go to intel/common. -- To view, visit https://review.coreboot.org/c/coreboot/+/86224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b24d2c89ade8cc62b7e47c487d52d47b7f3376d Gerrit-Change-Number: 86224 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Feb 2025 17:15:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: intel/acpi: Put BSP as the first entry
by Vladimir Serbinenko (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Patrick Rudolph. Vladimir Serbinenko has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/86247?usp=email ) Change subject: intel/acpi: Put BSP as the first entry ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86247/comment/e8cc51b8_49db7eeb?us… : PS4, Line 9: Linux complains in dmesg as a firmware bug that BSP is not the first entry. > Could you include requirement link? Added in the comment so it's preserved for posterity File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/86247/comment/5a603f6d_036f7fe1?us… : PS4, Line 22: * then followed by Efficeint Cores's APIC IDs. > Could you please fix the typo on Efficient since you are editing this comment? Done https://review.coreboot.org/c/coreboot/+/86247/comment/c9b9111c_d8aedcad?us… : PS4, Line 30: * This will be used > Please fill paragraph. Line length limit is 96-character. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Gerrit-Change-Number: 86247 Gerrit-PatchSet: 4 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 03 Feb 2025 17:12:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: intel/acpi: Put BSP as the first entry
by Vladimir Serbinenko (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Patrick Rudolph, Vladimir Serbinenko. Hello Intel coreboot Reviewers, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86247?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: intel/acpi: Put BSP as the first entry ...................................................................... intel/acpi: Put BSP as the first entry Linux complains in dmesg as a firmware bug that BSP is not the first entry. NetBSD hangs and OpenBSD panics early on boot. With this patch I was able to boot NetBSD and OpenBSD on darp10-b when loaded in GRUB. Note: vanilla bootloaders for NetBSD and OpenBSD still result in an apparent hang for an unknown reason. Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 28 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/86247/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Gerrit-Change-Number: 86247 Gerrit-PatchSet: 5 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com>

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[S] Change in coreboot[main]: vc/google/chromeos: Add low battery indicator screen
by Karthik Ramasubramanian (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86225?usp=email ) Change subject: vc/google/chromeos: Add low battery indicator screen ...................................................................... Patch Set 2: (1 comment) File src/vendorcode/google/chromeos/Kconfig: https://review.coreboot.org/c/coreboot/+/86225/comment/c1cd8d40_c56366d6?us… : PS2, Line 124: and defer the firmware update. > How is this related to updates? This refers to deferring the CSE FW Sync that happens in romstage on certain platforms. This also refers to deferring the memory training when FSP-M is updated as part of firmware update. -- To view, visit https://review.coreboot.org/c/coreboot/+/86225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Gerrit-Change-Number: 86225 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 03 Feb 2025 17:08:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: payloads/external/iPXE: introduce support for named configurations
by Filip Lewiński (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Felix Singer, Filip Lewiński, Krystian Hebel, Martin L Roth, Michał Kopeć. Hello Krystian Hebel, Martin L Roth, Michał Kopeć, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82041?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review-1 by Krystian Hebel, Verified+1 by build bot (Jenkins) Change subject: payloads/external/iPXE: introduce support for named configurations ...................................................................... payloads/external/iPXE: introduce support for named configurations This commit adds support for iPXE's named configuration mechanism, allowing for optional customization of configuration headers without modifying iPXE source files directly. Named configurations align with iPXE's documented practices and provide a structured way to apply customizations, while keeping the source tree clean. - A new `payloads/external/iPXE/named-configs` directory was introduced to hold named configuration files (e.g., `general.h`, `console.h`, `serial.h`) for specific use cases. - The `Makefile` was updated to: - Copy named configuration files into `src/config/local/<name>` within the iPXE build directory during the build process, if a named configuration is explicitly enabled via `CONFIG_IPXE_NAMED_CONFIG`. - Retain the existing `sed`-based modifications to configuration files for legacy and default workflows. - A new Kconfig option (`CONFIG_IPXE_NAMED_CONFIG`) was added to allow users to specify a named configuration. If unset, the named configuration logic is skipped entirely, ensuring no impact on existing builds. The previous workflow relied entirely on `sed` commands to modify iPXE header files during the build. While this approach works, it directly modifies the source tree, which: - Can complicate branch switching or repository updates. - Does not utilize iPXE's native named configuration mechanism, which provides a cleaner and more maintainable way to handle customizations. Named configurations offer an alternative that avoids directly altering iPXE's source files. This is particularly useful for maintaining reproducible and isolated builds. While the existing `sed` logic is preserved, named configurations could potentially replace it in the future. - No changes were made to the default workflow. Builds that do not specify `CONFIG_IPXE_NAMED_CONFIG` continue to rely on the existing `sed` logic. - The named configuration mechanism is entirely optional and will only apply if explicitly enabled by setting `CONFIG_IPXE_NAMED_CONFIG` in the platform's defconfig. To use a named configuration: 1. Create a directory under `payloads/external/iPXE/named-configs/<name>` with custom header files (e.g., `general.h`, `console.h`). 2. Set `CONFIG_IPXE_NAMED_CONFIG="<name>"` in the platform's defconfig. 3. Build as usual. If no named configuration is specified, the build process remains unchanged. Change-Id: Ibf7c2d9e4407035bfdf0115f4628f23b38272656 Signed-off-by: Filip Lewiński <filip.lewinski(a)3mdeb.com> --- M payloads/external/Makefile.mk M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile A payloads/external/iPXE/named-configs/.gitkeep 4 files changed, 40 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/82041/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/82041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibf7c2d9e4407035bfdf0115f4628f23b38272656 Gerrit-Change-Number: 82041 Gerrit-PatchSet: 8 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[S] Change in coreboot[main]: intel/acpi: Put BSP as the first entry
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Patrick Rudolph, Vladimir Serbinenko. Jérémy Compostella has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/86247?usp=email ) Change subject: intel/acpi: Put BSP as the first entry ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86247/comment/7d10ce88_b67d3133?us… : PS4, Line 9: Linux complains in dmesg as a firmware bug that BSP is not the first entry. Could you include requirement link? File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/86247/comment/c2e1dd3b_05ba15d8?us… : PS4, Line 22: * then followed by Efficeint Cores's APIC IDs. Could you please fix the typo on Efficient since you are editing this comment? https://review.coreboot.org/c/coreboot/+/86247/comment/bfd99c51_5cd0460a?us… : PS4, Line 30: * This will be used Please fill paragraph. Line length limit is 96-character. -- To view, visit https://review.coreboot.org/c/coreboot/+/86247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Gerrit-Change-Number: 86247 Gerrit-PatchSet: 4 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Feb 2025 17:03:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/adl: Handle critical low battery early in romstage
by Karthik Ramasubramanian (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86227?usp=email ) Change subject: soc/intel/adl: Handle critical low battery early in romstage ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/86227/comment/f03fc3fb_7f8dd273?us… : PS3, Line 446: early_shutdown_if_battery_below_critical_threshold(); > Why is this inserted here? Isn't this the code path that only happens when MRC cache data was not fo […] I think the motivation is to inform the user as much as possible through Graphical UI than text. That is why the text based notification is limited only when the memory training is required. If we do it in romstage entry, then we will most likely end with the text based notification all the time. -- To view, visit https://review.coreboot.org/c/coreboot/+/86227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2 Gerrit-Change-Number: 86227 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Feb 2025 17:03:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: intel/acpi: Put BSP as the first entry
by Vladimir Serbinenko (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Patrick Rudolph. Vladimir Serbinenko has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/86247?usp=email ) Change subject: intel/acpi: Put BSP as the first entry ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/86247/comment/fe221f61_338ab608?us… : PS3, Line 40: The > Changed the comment and changed the code that relied on it Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Gerrit-Change-Number: 86247 Gerrit-PatchSet: 4 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 03 Feb 2025 16:49:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Vladimir Serbinenko <phcoder(a)gmail.com>

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[XS] Change in coreboot[main]: acpi: Zero-out MADT before filling it
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak, Vladimir Serbinenko. Jérémy Compostella has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/86246?usp=email ) Change subject: acpi: Zero-out MADT before filling it ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e Gerrit-Change-Number: 86246 Gerrit-PatchSet: 3 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Feb 2025 16:48:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: vc/google/chromeos: Refactor Makefile to use a macro for CBFS logo
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86237?usp=email ) Change subject: vc/google/chromeos: Refactor Makefile to use a macro for CBFS logo ...................................................................... vc/google/chromeos: Refactor Makefile to use a macro for CBFS logo This commit introduces a new macro, cbfs_add_bmp_file, to the ChromeOS vendor code Makefile. The macro simplifies the process of adding BMP files to the CBFS (coreboot Filesystem) by encapsulating the repetitive tasks of specifying file attributes such as file path, type, and compression flag. TEST:Both 'cb_logo.bmp' and 'cb_plus_logo.bmp' files are included with the same properties, within the coreboot firmware image. Change-Id: I827451da79931c09768965c3ad071ecdd918d367 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86237 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/google/chromeos/Makefile.mk 1 file changed, 10 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/vendorcode/google/chromeos/Makefile.mk b/src/vendorcode/google/chromeos/Makefile.mk index 44d4d2b..67b50f6b 100644 --- a/src/vendorcode/google/chromeos/Makefile.mk +++ b/src/vendorcode/google/chromeos/Makefile.mk @@ -30,12 +30,14 @@ BMP_LOGO_COMPRESS_FLAG := LZ4 endif -cbfs-files-$(CONFIG_CHROMEOS_FW_SPLASH_SCREEN) += cb_logo.bmp -cb_logo.bmp-file := $(call strip_quotes,$(CONFIG_CHROMEOS_LOGO_PATH)) -cb_logo.bmp-type := raw -cb_logo.bmp-compression := $(BMP_LOGO_COMPRESS_FLAG) +define add_bmp_logo_file_to_cbfs +cbfs-files-$$($(1)) += $(2) +$(2)-file := $$(call strip_quotes,$$($(3))) +$(2)-type := raw +$(2)-compression := $$(BMP_LOGO_COMPRESS_FLAG) +endef -cbfs-files-$(CONFIG_CHROMEOS_FW_SPLASH_SCREEN) += cb_plus_logo.bmp -cb_plus_logo.bmp-file := $(call strip_quotes,$(CONFIG_CHROMEBOOK_PLUS_LOGO_PATH)) -cb_plus_logo.bmp-type := raw -cb_plus_logo.bmp-compression := $(BMP_LOGO_COMPRESS_FLAG) +$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_CHROMEOS_FW_SPLASH_SCREEN, \ + cb_logo.bmp,CONFIG_CHROMEOS_LOGO_PATH)) +$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_CHROMEOS_FW_SPLASH_SCREEN, \ + cb_plus_logo.bmp,CONFIG_CHROMEBOOK_PLUS_LOGO_PATH)) -- To view, visit https://review.coreboot.org/c/coreboot/+/86237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I827451da79931c09768965c3ad071ecdd918d367 Gerrit-Change-Number: 86237 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit February 2025