coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[XS] Change in coreboot[main]: mb/asus/p8z77-m: Hide peg11 to squelch warning
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Elyes Haouas, Keith Hui. Matt DeVillier has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82633?usp=email ) Change subject: mb/asus/p8z77-m: Hide peg11 to squelch warning ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I75402d338e64f477f40682f796477e8fcb94a4e8 Gerrit-Change-Number: 82633 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 03 Feb 2025 19:00:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Hide nonexistent IVB devices
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86185?usp=email ) Change subject: mb/asus/p8x7x-series: Hide nonexistent IVB devices ...................................................................... mb/asus/p8x7x-series: Hide nonexistent IVB devices Hide peg12, dev4, and peg60 devices to squelch leftover devices warning seen with p8z77-m, p8z77-v and p8z77-v_le_plus: [WARN ] PCI: Leftover static devices: [WARN ] PCI: 00:00:01.1 [WARN ] PCI: 00:00:01.2 [WARN ] PCI: 00:00:04.0 [WARN ] PCI: 00:00:06.0 [WARN ] PCI: Check your devicetree.cb. No board in this family can do the 8/4/4 PCIe lane split to require the peg12 bridge, or implemented dev4 at all. Only p8c_ws wired up the 4 extra Xeon PCIe lanes peg60 is supposed to cover, and its overridetree already enables it. Therefore, be proactive and hide these from the rest of the family. Change-Id: I24234e6b77a9effc577c8e22c77bb9896b983b7f Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86185 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/asus/p8x7x-series/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index fbff870..eb7a243 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -9,7 +9,10 @@ device domain 0 on device ref peg10 on end # PCIEX16_1 + device ref peg12 hidden end device ref igd on end + device ref dev4 hidden end + device ref peg60 hidden end chip southbridge/intel/bd82x6x register "sata_interface_speed_support" = "0x3" -- To view, visit https://review.coreboot.org/c/coreboot/+/86185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24234e6b77a9effc577c8e22c77bb9896b983b7f Gerrit-Change-Number: 86185 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/bostentech/gbyt4: Increase default CBFS size to cover BIOS region
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86219?usp=email ) Change subject: mb/bostentech/gbyt4: Increase default CBFS size to cover BIOS region ...................................................................... mb/bostentech/gbyt4: Increase default CBFS size to cover BIOS region There is no reason to default to a 1MB CBFS when the descriptor gives us 5MB to work with. Signed-off-by: Mate Kukri <km(a)mkukri.xyz> Change-Id: I65a8b161c522a2da58420397aae6c7ff2b5cf30d Reviewed-on: https://review.coreboot.org/c/coreboot/+/86219 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/bostentech/gbyt4/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig index 3027273..acfa313 100644 --- a/src/mainboard/bostentech/gbyt4/Kconfig +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -12,6 +12,9 @@ select SOC_INTEL_BAYTRAIL select SUPERIO_ITE_IT8728F +config CBFS_SIZE + default 0x500000 + config MAINBOARD_DIR default "bostentech/gbyt4" -- To view, visit https://review.coreboot.org/c/coreboot/+/86219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65a8b161c522a2da58420397aae6c7ff2b5cf30d Gerrit-Change-Number: 86219 Gerrit-PatchSet: 2 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/bostentech/gbyt4: Add VBT
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86218?usp=email ) Change subject: mb/bostentech/gbyt4: Add VBT ...................................................................... mb/bostentech/gbyt4: Add VBT This is useful when booted with the (not yet mainline) libgfxinit for Bay Trail. Signed-off-by: Mate Kukri <km(a)mkukri.xyz> Change-Id: I73d54c73a12430074f4f3880caf842b3491b5170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86218 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/data.vbt 2 files changed, 3 insertions(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig index 51e9209..3027273 100644 --- a/src/mainboard/bostentech/gbyt4/Kconfig +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -4,11 +4,12 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SOC_INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_BAYTRAIL select SUPERIO_ITE_IT8728F config MAINBOARD_DIR diff --git a/src/mainboard/bostentech/gbyt4/data.vbt b/src/mainboard/bostentech/gbyt4/data.vbt new file mode 100644 index 0000000..ed02d64 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/86218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73d54c73a12430074f4f3880caf842b3491b5170 Gerrit-Change-Number: 86218 Gerrit-PatchSet: 2 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: soc/intel/baytrail: Add microcode for '06-37-08' SOCs
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86217?usp=email ) Change subject: soc/intel/baytrail: Add microcode for '06-37-08' SOCs ...................................................................... soc/intel/baytrail: Add microcode for '06-37-08' SOCs Previously only the '06-37-03' and '06-37-09' microcode files were provided but '06-37-08' was missing. Linux on my '06-37-08' SOC was segfaulting in various unpredictable ways without this patch. Signed-off-by: Mate Kukri <km(a)mkukri.xyz> Change-Id: I1a66a8ba980f4fd43f5f54d446edbcd5029e33a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86217 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/intel/baytrail/Makefile.mk 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 281175c..bef8c0e 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -65,6 +65,7 @@ postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin \ + 3rdparty/intel-microcode/intel-ucode/06-37-08 \ 3rdparty/intel-microcode/intel-ucode/06-37-09 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include -- To view, visit https://review.coreboot.org/c/coreboot/+/86217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a66a8ba980f4fd43f5f54d446edbcd5029e33a0 Gerrit-Change-Number: 86217 Gerrit-PatchSet: 2 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: mb/amd/birman_plus: Update phoenix port descriptors
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86232?usp=email ) Change subject: mb/amd/birman_plus: Update phoenix port descriptors ...................................................................... mb/amd/birman_plus: Update phoenix port descriptors Update dxio descriptors based on PI source code 1.2.0.0a. Change-Id: I54d35060c34043f9d97658ab84b9b1bb2e62ba60 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86232 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/birman_plus/port_descriptors_phoenix.c 1 file changed, 19 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c b/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c index dc23790..e36e579 100644 --- a/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c @@ -21,7 +21,7 @@ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ } -#define ssd0_dxio_descriptor { \ +#define phx_ssd0_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ .start_lane = 16, \ @@ -36,10 +36,10 @@ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ } -#define wlan_dxio_descriptor { \ +#define phx_wlan_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = true, \ - .start_lane = 15, \ + .port_present = !CONFIG(DISABLE_WLAN_SD_BIRMANPLUS), \ + .start_lane = CONFIG(ENABLE_WLAN02_BIRMANPLUS) ? 14 : 15, \ .end_lane = 15, \ .device_number = 2, \ .function_number = 2, \ @@ -65,11 +65,11 @@ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ } -#define wwan_dxio_descriptor { \ +#define phx_wwan_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = true, \ + .port_present = !CONFIG(DISABLE_WWAN_GBE_BIRMANPLUS), \ .start_lane = 12, \ - .end_lane = 12, \ + .end_lane = CONFIG(ENABLE_WWAN02_BIRMANPLUS) ? 13 : 12, \ .device_number = 2, \ .function_number = 3, \ .link_speed_capability = GEN_MAX, \ @@ -80,7 +80,7 @@ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ } -#define gbe_dxio_descriptor { \ +#define phx_gbe_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ .start_lane = 13, \ @@ -95,7 +95,7 @@ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ } -#define sd_dxio_descriptor { \ +#define phx_sd_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = false, \ .start_lane = 14, \ @@ -105,7 +105,7 @@ .link_speed_capability = GEN_MAX, \ .turn_off_unused_lanes = true, \ .link_aspm = ASPM_L1, \ - .link_hotplug = HOTPLUG_DISABLED, \ + .link_hotplug = HOTPLUG_BASIC, \ .clk_req = CLK_REQ5, \ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ } @@ -186,12 +186,16 @@ printk(BIOS_DEBUG, "Using Birmanplus PHX DXIO\n"); static const fsp_dxio_descriptor birmanplus_phx_dxio_descriptors[] = { phx_mxm_dxio_descriptor, - ssd0_dxio_descriptor, - wlan_dxio_descriptor, + phx_ssd0_dxio_descriptor, + phx_wlan_dxio_descriptor, phx_ssd1_dxio_descriptor, - wwan_dxio_descriptor, - gbe_dxio_descriptor, - sd_dxio_descriptor, + phx_wwan_dxio_descriptor, +#if CONFIG(ENABLE_GBE_BIRMANPLUS) + phx_gbe_dxio_descriptor, +#endif +#if CONFIG(ENABLE_SDCARD_BIRMANPLUS) + phx_sd_dxio_descriptor, +#endif }; *dxio_descs = birmanplus_phx_dxio_descriptors; -- To view, visit https://review.coreboot.org/c/coreboot/+/86232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54d35060c34043f9d97658ab84b9b1bb2e62ba60 Gerrit-Change-Number: 86232 Gerrit-PatchSet: 2 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
by Sergii Dmytruk (Code Review) 03 Feb '25

03 Feb '25

Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/67065?usp=email ) Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER ...................................................................... Patch Set 43: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67065/comment/b82e45e5_0a4be06e?us… : PS43, Line 17: will be done in a follow-up change > Is it still active? I believe it hasn't been implemented yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/67065?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Gerrit-Change-Number: 67065 Gerrit-PatchSet: 43 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Feb 2025 18:16:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[S] Change in coreboot[main]: intel/acpi: Put BSP as the first entry
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Patrick Rudolph, Vladimir Serbinenko. Jérémy Compostella has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/86247?usp=email ) Change subject: intel/acpi: Put BSP as the first entry ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/86247/comment/7eb88d34_72db9f24?us… : PS5, Line 68: cpu_apic_info.is_bsp_perf = cpu_infos[i].cpu->path.apic.core_type == CPU_TYPE_PERF; Break the line to meet coding style guidelines. Similarly to line 72. -- To view, visit https://review.coreboot.org/c/coreboot/+/86247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691 Gerrit-Change-Number: 86247 Gerrit-PatchSet: 5 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Feb 2025 17:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: payloads/external/iPXE: introduce support for named configurations
by Filip Lewiński (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Felix Singer, Krystian Hebel, Martin L Roth, Michał Kopeć. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82041?usp=email ) Change subject: payloads/external/iPXE: introduce support for named configurations ...................................................................... Patch Set 9: (1 comment) Patchset: PS7: > Doesn't build without specifying named config: […] Right, [improved](https://review.coreboot.org/c/coreboot/+/82041/9/payloads/externa… the logic -- To view, visit https://review.coreboot.org/c/coreboot/+/82041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibf7c2d9e4407035bfdf0115f4628f23b38272656 Gerrit-Change-Number: 82041 Gerrit-PatchSet: 9 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Mon, 03 Feb 2025 17:28:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com>

1 0

[S] Change in coreboot[main]: payloads/external/iPXE: introduce support for named configurations
by Filip Lewiński (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Felix Singer, Filip Lewiński, Krystian Hebel, Martin L Roth, Michał Kopeć. Hello Krystian Hebel, Martin L Roth, Michał Kopeć, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82041?usp=email to look at the new patch set (#9). Change subject: payloads/external/iPXE: introduce support for named configurations ...................................................................... payloads/external/iPXE: introduce support for named configurations This commit adds support for iPXE's named configuration mechanism, allowing for optional customization of configuration headers without modifying iPXE source files directly. Named configurations align with iPXE's documented practices and provide a structured way to apply customizations, while keeping the source tree clean. - A new `payloads/external/iPXE/named-configs` directory was introduced to hold named configuration files (e.g., `general.h`, `console.h`, `serial.h`) for specific use cases. - The `Makefile` was updated to: - Copy named configuration files into `src/config/local/<name>` within the iPXE build directory during the build process, if a named configuration is explicitly enabled via `CONFIG_IPXE_NAMED_CONFIG`. - Retain the existing `sed`-based modifications to configuration files for legacy and default workflows. - A new Kconfig option (`CONFIG_IPXE_NAMED_CONFIG`) was added to allow users to specify a named configuration. If unset, the named configuration logic is skipped entirely, ensuring no impact on existing builds. The previous workflow relied entirely on `sed` commands to modify iPXE header files during the build. While this approach works, it directly modifies the source tree, which: - Can complicate branch switching or repository updates. - Does not utilize iPXE's native named configuration mechanism, which provides a cleaner and more maintainable way to handle customizations. Named configurations offer an alternative that avoids directly altering iPXE's source files. This is particularly useful for maintaining reproducible and isolated builds. While the existing `sed` logic is preserved, named configurations could potentially replace it in the future. - No changes were made to the default workflow. Builds that do not specify `CONFIG_IPXE_NAMED_CONFIG` continue to rely on the existing `sed` logic. - The named configuration mechanism is entirely optional and will only apply if explicitly enabled by setting `CONFIG_IPXE_NAMED_CONFIG` in the platform's defconfig. To use a named configuration: 1. Create a directory under `payloads/external/iPXE/named-configs/<name>` with custom header files (e.g., `general.h`, `console.h`). 2. Set `CONFIG_IPXE_NAMED_CONFIG="<name>"` in the platform's defconfig. 3. Build as usual. If no named configuration is specified, the build process remains unchanged. Change-Id: Ibf7c2d9e4407035bfdf0115f4628f23b38272656 Signed-off-by: Filip Lewiński <filip.lewinski(a)3mdeb.com> --- M payloads/external/Makefile.mk M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile A payloads/external/iPXE/named-configs/.gitkeep 4 files changed, 40 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/82041/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/82041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibf7c2d9e4407035bfdf0115f4628f23b38272656 Gerrit-Change-Number: 82041 Gerrit-PatchSet: 9 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025