coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[S] Change in blobs[main]: soc/mediatek/mt8196: Add mtk_fsp_ramstage version v1.0
by Jarried Lin (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Jarried Lin. Hello Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/86253?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8196: Add mtk_fsp_ramstage version v1.0 ...................................................................... soc/mediatek/mt8196: Add mtk_fsp_ramstage version v1.0 The initialization of mtk_fsp_ramstage in the ramstage includes: - UFS mphy settings. - DPAC (Device Access Permission Control) settings. - MMinfra (Multimedia Infrastrucutre) settings. - SMPU (Security Memory Protection Unit) settings. - Advanced CPU frequency control. BRANCH=rauru BUG=b:373797027 TEST=Build pass Change-Id: I92479085a5a688b3fde241568bd06005a52e8dc1 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/mtk_fsp_ramstage.elf A soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 A soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt 4 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/53/86253/3 -- To view, visit https://review.coreboot.org/c/blobs/+/86253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I92479085a5a688b3fde241568bd06005a52e8dc1 Gerrit-Change-Number: 86253 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[M] Change in coreboot[main]: soc/amd/common: Support sbin ucode files
by Maximilian Brune (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, Patrick Rudolph, Raul Rangel. Maximilian Brune has posted comments on this change by Fred Reitberger. ( https://review.coreboot.org/c/coreboot/+/68122?usp=email ) Change subject: soc/amd/common: Support sbin ucode files ...................................................................... Patch Set 9: (1 comment) File src/soc/amd/common/block/cpu/Makefile.mk: https://review.coreboot.org/c/coreboot/+/68122/comment/3e091794_c75a824f?us… : PS9, Line 32: # if there is both a sbin and bin microcode only include the bin one to keep the old behaviour > When I last worked on this, the releases would be in '. […] This only covers the case if there is both an sbin and bin (like currently in mendocino). In this case I chose to prefer the bin over sbin, because that would keep the current behaviour on mendocino. But on newer releases I assume we will only get sbin microcodes. In that case the sbin microcode will be used (since there is no identical bin microcode present). I just wanted to make sure that downstream (for example in case of google downstream forks that include the binaries) doesn't suddenly use an sbin instead of bin in case both are present. -- To view, visit https://review.coreboot.org/c/coreboot/+/68122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae Gerrit-Change-Number: 68122 Gerrit-PatchSet: 9 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Feb 2025 01:26:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com>

1 0

[M] Change in coreboot[main]: mb/cwwk/adl: Various device tree fixes
by Brandon Weeks (Code Review) 03 Feb '25

03 Feb '25

Brandon Weeks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86260?usp=email ) Change subject: mb/cwwk/adl: Various device tree fixes ...................................................................... mb/cwwk/adl: Various device tree fixes - Set pmc_gpe0_dw{0-3} to resolve a warning - Set CLKREQ# based on register value from vendor firmware - Enable ITE environment controller Change-Id: I9365e76c593b7e4a334dcdc5ecd46da253e14716 Signed-off-by: Brandon Weeks <bweeks(a)google.com> --- M src/mainboard/cwwk/adl/devicetree.cb 1 file changed, 33 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/86260/1 diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb index 72a1a98..1284ddf 100644 --- a/src/mainboard/cwwk/adl/devicetree.cb +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -1,6 +1,8 @@ chip soc/intel/alderlake - register "s0ix_enable" = "true" + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" @@ -14,37 +16,40 @@ register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_CLK_REQ_DETECT, }" register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_L0S, }" register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 2, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_L0S, }" register "pch_pcie_rp[PCH_RP(10)]" = "{ .clk_src = 3, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_L0S, }" register "pch_pcie_rp[PCH_RP(11)]" = "{ .clk_src = 4, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, + .flags = PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_L0S, }" register "pch_pcie_rp[PCH_RP(12)]" = "{ .clk_src = 4, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, - .pcie_rp_aspm = ASPM_DISABLE, + .flags = PCIE_RP_CLK_REQ_UNUSED, + .pcie_rp_aspm = ASPM_L0S, }" # Enable EDP in PortA @@ -52,7 +57,6 @@ device domain 0 on device ref igpu on end - device ref dtt on end device ref crashlog off end device ref xhci on end device ref shared_sram on end @@ -63,18 +67,28 @@ device ref pcie_rp11 on end device ref pcie_rp12 on end # M.2 E key port device ref pch_espi on + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c0081" chip superio/ite/it8613e + register "FAN2.mode" = "FAN_SMART_SOFTWARE" # CPU_FAN + register "FAN3.mode" = "FAN_SMART_SOFTWARE" # SYS_FAN device pnp 2e.0 off end - device pnp 2e.1 on # COM 1 + device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 irq 0x70 = 0x4 irq 0xf0 = 0x1 end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 off end # Keyboard - device pnp 2e.6 off end # Mouse - device pnp 2e.7 off end # GPIO - device pnp 2e.a off end # CIR + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + irq 0x70 = 0x00 + irq 0x71 = 0x80 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR end end device ref hda on end -- To view, visit https://review.coreboot.org/c/coreboot/+/86260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9365e76c593b7e4a334dcdc5ecd46da253e14716 Gerrit-Change-Number: 86260 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: Add missing min sleep state for SMBUS device
by Brandon Weeks (Code Review) 03 Feb '25

03 Feb '25

Brandon Weeks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86259?usp=email ) Change subject: soc/intel/alderlake: Add missing min sleep state for SMBUS device ...................................................................... soc/intel/alderlake: Add missing min sleep state for SMBUS device Fixes: Unknown min d_state for PCI: 00:1f.4 Change-Id: I8050c8d574ea5908d5ad3f1e5a034257fabb72c5 Signed-off-by: Brandon Weeks <bweeks(a)google.com> --- M src/soc/intel/alderlake/acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/86259/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 463112f..4c5a515 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -217,6 +217,7 @@ { PCH_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, { PCH_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_SMBUS, ACPI_DEVICE_SLEEP_D0 }, { PCH_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, { PCH_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/86259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8050c8d574ea5908d5ad3f1e5a034257fabb72c5 Gerrit-Change-Number: 86259 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com>

1 0

[XS] Change in blobs[main]: soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2
by jason-ch chen (Code Review) 03 Feb '25

03 Feb '25

jason-ch chen has posted comments on this change by jason-ch chen. ( https://review.coreboot.org/c/blobs/+/86248?usp=email ) Change subject: soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/86248/comment/8099c3a1_10776583?usp=e… : PS2, Line 14: > BRANCH=corsola Done -- To view, visit https://review.coreboot.org/c/blobs/+/86248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Id9491ecf7dde823f5ec034ae92d4b4bcfcdc6905 Gerrit-Change-Number: 86248 Gerrit-PatchSet: 3 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 04 Feb 2025 00:53:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

[XS] Change in blobs[main]: soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2
by jason-ch chen (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: jason-ch chen. Hello Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/86248?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2 ...................................................................... soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2 - Fix error handler for infra timeout in SSPM. The error handler for infra timeout in SSPM was not handled properly, causing the ISR to get stuck. As a result, tasks without ISR would not continue to operate. - Enable SSPM debug configs BRANCH=corsola BUG=b:360756645, b:374015969 TEST=get "MediaTek SSPM firmware: version 2.0.2" by strings sspm.bin | grep version Change-Id: Id9491ecf7dde823f5ec034ae92d4b4bcfcdc6905 Signed-off-by: jason-ch chen <jason-ch.chen(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8186/sspm.bin M soc/mediatek/mt8186/sspm.bin.md5 M soc/mediatek/mt8186/sspm_release_notes.txt 3 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/48/86248/3 -- To view, visit https://review.coreboot.org/c/blobs/+/86248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Id9491ecf7dde823f5ec034ae92d4b4bcfcdc6905 Gerrit-Change-Number: 86248 Gerrit-PatchSet: 3 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com>

1 0

[XS] Change in coreboot[main]: soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik. Jérémy Compostella has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86256?usp=email ) Change subject: soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bd62d113455fab7fcb272d85f70e6a185e53b74 Gerrit-Change-Number: 86256 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Feb 2025 00:03:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik. Jérémy Compostella has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86257?usp=email ) Change subject: soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib31018173126737b36a6e0d822eba2ebc9c42306 Gerrit-Change-Number: 86257 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Feb 2025 00:03:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik. Jérémy Compostella has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86256?usp=email ) Change subject: soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bd62d113455fab7fcb272d85f70e6a185e53b74 Gerrit-Change-Number: 86256 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Feb 2025 00:01:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik. Jérémy Compostella has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86257?usp=email ) Change subject: soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib31018173126737b36a6e0d822eba2ebc9c42306 Gerrit-Change-Number: 86257 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Feb 2025 00:01:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025