coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add fw_config probe for touchscreen
by Jayvik Desai (Code Review) 04 Feb '25

04 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, John Su, Kapil Porwal, Nick Vaccaro. Jayvik Desai has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86144?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add fw_config probe for touchscreen ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63512e85052bce974ffb0b738164bea440bd413c Gerrit-Change-Number: 86144 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Feb 2025 10:07:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Enable CNVi wifi core
by Subrata Banik (Code Review) 04 Feb '25

04 Feb '25

Attention is currently required from: Ian Feng, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/86262?usp=email ) Change subject: mb/google/fatcat/var/francka: Enable CNVi wifi core ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: note if you have FW config for WIFI with different models then you can handle this using FW config.c as well like we did in fatcat -- To view, visit https://review.coreboot.org/c/coreboot/+/86262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c38882aab801dedb05355774e5b930a8528fed Gerrit-Change-Number: 86262 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 04 Feb 2025 10:06:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Enable CNVi wifi core
by Jayvik Desai (Code Review) 04 Feb '25

04 Feb '25

Attention is currently required from: Ian Feng, Kapil Porwal, Pranava Y N. Jayvik Desai has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/86262?usp=email ) Change subject: mb/google/fatcat/var/francka: Enable CNVi wifi core ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c38882aab801dedb05355774e5b930a8528fed Gerrit-Change-Number: 86262 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 04 Feb 2025 10:05:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Enable CNVi wifi core
by Subrata Banik (Code Review) 04 Feb '25

04 Feb '25

Attention is currently required from: Ian Feng, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/86262?usp=email ) Change subject: mb/google/fatcat/var/francka: Enable CNVi wifi core ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c38882aab801dedb05355774e5b930a8528fed Gerrit-Change-Number: 86262 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 04 Feb 2025 10:04:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Paul Menzel (Code Review) 04 Feb '25

04 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Vikrant L Jadeja. Paul Menzel has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 11: (4 comments) Patchset: PS11: What’s the difference to the implementation for other SoC types? Commit Message: https://review.coreboot.org/c/coreboot/+/85454/comment/64935157_9b7f4fb4?us… : PS11, Line 12: initialization Fits on the line above. https://review.coreboot.org/c/coreboot/+/85454/comment/95bb9ffc_61dd8ee3?us… : PS11, Line 47: The SOC_INTEL_PANTHERLAKE_SIGN_OF_LIFE flag also selects the LZ4 : compression algorithm for the Video BIOS Tables (VBT), as LZMA : decompression is not available by default during the romstage : phase. Integrating LZMA support would increase the romstage binary : size by an amount greater than the reduction achieved by compressing : the VBT binary using LZMA. Please reflow for 72 characters per line. https://review.coreboot.org/c/coreboot/+/85454/comment/ddc6d275_97fa3b05?us… : PS11, Line 53: Add a TEST= line and mention the new log messages. -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Tue, 04 Feb 2025 09:24:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable s0ix
by Paul Menzel (Code Review) 04 Feb '25

04 Feb '25

Paul Menzel has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/84923?usp=email ) Change subject: mb/google/fatcat: Enable s0ix ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84923/comment/e35f1cac_79159a62?us… : PS1, Line 8: > s0ix is verified with the latest CPFE and fatcat OS. Please update the commit message with this information next time. -- To view, visit https://review.coreboot.org/c/coreboot/+/84923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c65782830a2a22a9e8bb39615717a11183d30f Gerrit-Change-Number: 84923 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 04 Feb 2025 09:21:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable s0ix
by Subrata Banik (Code Review) 04 Feb '25

04 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84923?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat: Enable s0ix ...................................................................... mb/google/fatcat: Enable s0ix BUG=b:392235839 TEST=Build fatcat and boot to OS. Run suspend_stress_test to ensure s0ix entry and exit working. Change-Id: I80c65782830a2a22a9e8bb39615717a11183d30f Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84923 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 92ea38d..342c534 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -34,7 +34,7 @@ register "sagv" = "SAGV_ENABLED" # Enable s0ix - register "s0ix_enable" = "false" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/84923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c65782830a2a22a9e8bb39615717a11183d30f Gerrit-Change-Number: 84923 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Subrata Banik (Code Review) 04 Feb '25

04 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Vikrant L Jadeja. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 11: (2 comments) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/85454/comment/b1fb2688_f732281e?us… : PS11, Line 420: SOC_INTEL_PANTHERLAKE_SIGN_OF_LIFE can you please rely on https://review.coreboot.org/c/coreboot/+/83770 Kconfig. File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/1ac73feb_e653dae4?us… : PS11, Line 375: how about someone still using CSE sync in romstage ? (like non-CrOS usecase). we might still support there workflow ? can you please take a look at MTL flow ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Tue, 04 Feb 2025 08:38:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31
by Yidi Lin (Code Review) 04 Feb '25

04 Feb '25

Attention is currently required from: Gavin Liu, Hung-Te Lin. Yidi Lin has posted comments on this change by Gavin Liu. ( https://review.coreboot.org/c/coreboot/+/86252?usp=email ) Change subject: soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I858686ede3730fb70f71565ca3593e7eb4c460d2 Gerrit-Change-Number: 86252 Gerrit-PatchSet: 3 Gerrit-Owner: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Feb 2025 08:15:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Eliminate mt6685_hw.h and mt6685_rtc_hw.h
by Yidi Lin (Code Review) 04 Feb '25

04 Feb '25

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86264?usp=email ) Change subject: soc/mediatek/mt8196: Eliminate mt6685_hw.h and mt6685_rtc_hw.h ...................................................................... soc/mediatek/mt8196: Eliminate mt6685_hw.h and mt6685_rtc_hw.h Utilize the constants in rtc_reg_common.h and rtc_common.h. 1. Maintain minimum defines in mt6685_rtc.h. 2. Remove mt6685_hw.h and mt6685_rtc_hw.h. 3. Remove redundant definitions. The constains in mt6685_rtc.h are determined by below command, aarch64-cros-linux-gnu-gcc -E src/soc/mediatek/mt8196/mt6685_rtc.c \ -I src/commonlib/bsd/include/ -I src/include/ -I src/commonlib/include/ \ -I src/soc/mediatek/mt8196/include/ -I src/soc/mediatek/common/include/ \ -I src/arch/arm64/include/armv8/ -I ./src/arch/arm64/include/ BRANCH=rauru BUG=b:391067089 TEST=compare macro expansion result before and after applying the patch TEST=boot to kernel without RTC error Change-Id: I69ee165df6a1c9ea5853173f46f0aafc382153c1 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- D src/soc/mediatek/mt8196/include/soc/mt6685_hw.h M src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h D src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h M src/soc/mediatek/mt8196/include/soc/rtc.h M src/soc/mediatek/mt8196/mt6685_rtc.c 5 files changed, 123 insertions(+), 1,373 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/86264/1 diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h b/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h deleted file mode 100644 index dce7a07..0000000 --- a/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h +++ /dev/null @@ -1,942 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -/* - * This file is created based on MT8196 Functional Specification - * Chapter number: 14.2.4 - */ - -#ifndef SOC_MEDIATEK_MT8196_MT6685_HW_H -#define SOC_MEDIATEK_MT8196_MT6685_HW_H - -#define MT6685_HWCID_L 0x8 - -#define MT6685_RG_OCT1_IO_0 0xa7 -#define MT6685_RG_OCT1_IO_1 0xa8 -#define MT6685_TOP_CON 0x18 -#define MT6685_TOP_CKPDN_CON0 0x10b -#define MT6685_TOP_CKPDN_CON0_SET 0x10c -#define MT6685_TOP_CKPDN_CON0_CLR 0x10d -#define MT6685_TOP_CKSEL_CON0 0x111 -#define MT6685_TOP_CKSEL_CON0_SET 0x112 -#define MT6685_TOP_CKSEL_CON0_CLR 0x113 -#define MT6685_TOP_RST_MISC_CLR 0x129 -#define MT6685_RG_SEQ_OFF 0x12f -#define MT6685_RG_OCTL_SDAT 0x131 -#define MT6685_TOP_TMA_KEY 0x39e -#define MT6685_TOP_TMA_KEY_H 0x39f -#define MT6685_TOP_DIG_WPK 0x3a8 -#define MT6685_TOP_DIG_WPK_H 0x3a9 -#define MT6685_SPMI_PWR_CMD 0x408 -#define MT6685_SCK_TOP_CON0_L 0x50c -#define MT6685_SCK_TOP_CON0_H 0x50d -#define MT6685_SCK_TOP_CKPDN_CON0_L 0x514 -#define MT6685_SCK_TOP_CKPDN_CON0_L_SET 0x515 -#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR 0x516 -#define MT6685_SCK_TOP_RST_CON0 0x522 -#define MT6685_FQMTR_CON0_L 0x546 -#define MT6685_FQMTR_CON0_H 0x547 -#define MT6685_FQMTR_CON1_L 0x548 -#define MT6685_FQMTR_CON2_L 0x54a -#define MT6685_SCK_TOP_CKSEL_CON 0x568 -#define MT6685_RTC_SPAR_RELOAD 0x56a -#define MT6685_RTC_ANA_ID 0x580 -#define MT6685_RTC_DIG_ID 0x581 -#define MT6685_RTC_ANA_REV 0x582 -#define MT6685_RTC_DIG_REV 0x583 -#define MT6685_RTC_DBI 0x584 -#define MT6685_RTC_ESP 0x585 -#define MT6685_RTC_FPI 0x586 -#define MT6685_RTC_DXI 0x587 -#define MT6685_RTC_BBPU_L 0x588 -#define MT6685_RTC_BBPU_H 0x589 -#define MT6685_RTC_IRQ_STA 0x58a -#define MT6685_RTC_IRQ_EN 0x58c -#define MT6685_RTC_CII_EN_L 0x58e -#define MT6685_RTC_CII_EN_H 0x58f -#define MT6685_RTC_AL_MASK 0x590 -#define MT6685_RTC_TC_SEC 0x592 -#define MT6685_RTC_TC_MIN 0x594 -#define MT6685_RTC_TC_HOU 0x596 -#define MT6685_RTC_TC_DOM 0x598 -#define MT6685_RTC_TC_DOW 0x59a -#define MT6685_RTC_TC_MTH_L 0x59c -#define MT6685_RTC_TC_MTH_H 0x59d -#define MT6685_RTC_TC_YEA 0x59e -#define MT6685_RTC_AL_SEC_L 0x5a0 -#define MT6685_RTC_AL_SEC_H 0x5a1 -#define MT6685_RTC_AL_MIN 0x5a2 -#define MT6685_RTC_AL_HOU_L 0x5a4 -#define MT6685_RTC_AL_HOU_H 0x5a5 -#define MT6685_RTC_AL_DOM_L 0x5a6 -#define MT6685_RTC_AL_DOM_H 0x5a7 -#define MT6685_RTC_AL_DOW_L 0x5a8 -#define MT6685_RTC_AL_DOW_H 0x5a9 -#define MT6685_RTC_AL_MTH_L 0x5aa -#define MT6685_RTC_AL_MTH_H 0x5ab -#define MT6685_RTC_AL_YEA_L 0x5ac -#define MT6685_RTC_AL_YEA_H 0x5ad -#define MT6685_RTC_OSC32CON_L 0x5ae -#define MT6685_RTC_OSC32CON_H 0x5af -#define MT6685_RTC_POWERKEY1_L 0x5b0 -#define MT6685_RTC_POWERKEY1_H 0x5b1 -#define MT6685_RTC_POWERKEY2_L 0x5b2 -#define MT6685_RTC_POWERKEY2_H 0x5b3 -#define MT6685_RTC_PDN1_L 0x5b4 -#define MT6685_RTC_PDN1_H 0x5b5 -#define MT6685_RTC_PDN2_L 0x5b6 -#define MT6685_RTC_PDN2_H 0x5b7 -#define MT6685_RTC_SPAR0_L 0x5b8 -#define MT6685_RTC_SPAR0_H 0x5b9 -#define MT6685_RTC_SPAR1_L 0x5ba -#define MT6685_RTC_SPAR1_H 0x5bb -#define MT6685_RTC_PROT_L 0x5bc -#define MT6685_RTC_PROT_H 0x5bd -#define MT6685_RTC_DIFF_L 0x5be -#define MT6685_RTC_DIFF_H 0x5bf -#define MT6685_RTC_CALI_L 0x5c0 -#define MT6685_RTC_CALI_H 0x5c1 -#define MT6685_RTC_WRTGR 0x5c2 -#define MT6685_RTC_CON_L 0x5c4 -#define MT6685_RTC_CON_H 0x5c5 -#define MT6685_RTC_SEC_CTRL 0x5c6 -#define MT6685_RTC_INT_CNT_L 0x5c8 -#define MT6685_RTC_INT_CNT_H 0x5c9 -#define MT6685_RTC_SEC_DAT0_L 0x5ca -#define MT6685_RTC_SEC_DAT0_H 0x5cb -#define MT6685_RTC_SEC_DAT1_L 0x5cc -#define MT6685_RTC_SEC_DAT1_H 0x5cd -#define MT6685_RTC_SEC_DAT2_L 0x5ce -#define MT6685_RTC_SEC_DAT2_H 0x5cf -#define MT6685_RTC_RG_FG0 0x5d0 -#define MT6685_RTC_RG_FG1 0x5d2 -#define MT6685_RTC_RG_FG2 0x5d4 -#define MT6685_RTC_RG_FG3 0x5d6 -#define MT6685_RTC_SPAR_MACRO 0x5d8 -#define MT6685_RTC_SPAR_CORE 0x5e0 -#define MT6685_RTC_EOSC_CALI 0x5e2 -#define MT6685_RTC_SEC_ANA_ID 0x600 -#define MT6685_RTC_SEC_DIG_ID 0x601 -#define MT6685_RTC_SEC_ANA_REV 0x602 -#define MT6685_RTC_SEC_DIG_REV 0x603 -#define MT6685_RTC_SEC_DBI 0x604 -#define MT6685_RTC_SEC_ESP 0x605 -#define MT6685_RTC_SEC_FPI 0x606 -#define MT6685_RTC_SEC_DXI 0x607 -#define MT6685_RTC_TC_SEC_SEC 0x608 -#define MT6685_RTC_TC_MIN_SEC 0x60a -#define MT6685_RTC_TC_HOU_SEC 0x60c -#define MT6685_RTC_TC_DOM_SEC 0x60e -#define MT6685_RTC_TC_DOW_SEC 0x610 -#define MT6685_RTC_TC_MTH_SEC 0x612 -#define MT6685_RTC_TC_YEA_SEC 0x614 -#define MT6685_RTC_SEC_CK_PDN 0x616 -#define MT6685_RTC_SEC_WRTGR 0x618 -#define MT6685_DCXO_DIG_MODE_CW0 0x789 - -#define MT6685_RG_SRCLKEN_IN0_HW_MODE_ADDR \ - MT6685_TOP_CON -#define MT6685_RG_SRCLKEN_IN0_HW_MODE_MASK 0x1 -#define MT6685_RG_SRCLKEN_IN0_HW_MODE_SHIFT 1 -#define MT6685_RG_SRCLKEN_IN1_HW_MODE_ADDR \ - MT6685_TOP_CON -#define MT6685_RG_SRCLKEN_IN1_HW_MODE_MASK 0x1 -#define MT6685_RG_FQMTR_32K_CK_PDN_ADDR \ - MT6685_TOP_CKPDN_CON0 -#define MT6685_RG_FQMTR_32K_CK_PDN_MASK 0x1 -#define MT6685_RG_FQMTR_32K_CK_PDN_SHIFT 4 -#define MT6685_RG_SRCLKEN_IN1_HW_MODE_SHIFT 2 -#define MT6685_RG_FQMTR_CK_PDN_ADDR \ - MT6685_TOP_CKPDN_CON0 -#define MT6685_RG_FQMTR_CK_PDN_MASK 0x1 -#define MT6685_RG_FQMTR_CK_PDN_SHIFT 5 -#define MT6685_RG_INTRP_CK_PDN_ADDR \ - MT6685_TOP_CKPDN_CON0 -#define MT6685_RG_INTRP_CK_PDN_MASK 0x1 -#define MT6685_RG_INTRP_CK_PDN_SHIFT 6 -#define MT6685_TOP_CKPDN_CON0_SET_ADDR \ - MT6685_TOP_CKPDN_CON0_SET -#define MT6685_TOP_CKPDN_CON0_SET_MASK 0xFF -#define MT6685_TOP_CKPDN_CON0_SET_SHIFT 0 -#define MT6685_TOP_CKPDN_CON0_CLR_ADDR \ - MT6685_TOP_CKPDN_CON0_CLR -#define MT6685_TOP_CKPDN_CON0_CLR_MASK 0xFF -#define MT6685_TOP_CKPDN_CON0_CLR_SHIFT 0 -#define MT6685_RG_FQMTR_CK_CKSEL_ADDR \ - MT6685_TOP_CKSEL_CON0 -#define MT6685_RG_FQMTR_CK_CKSEL_MASK 0x7 -#define MT6685_RG_FQMTR_CK_CKSEL_SHIFT 0 -#define MT6685_RG_PMU32K_CK_CKSEL_ADDR \ - MT6685_TOP_CKSEL_CON0 -#define MT6685_RG_PMU32K_CK_CKSEL_MASK 0x1 -#define MT6685_RG_PMU32K_CK_CKSEL_SHIFT 3 -#define MT6685_TOP_CKSEL_CON0_SET_ADDR \ - MT6685_TOP_CKSEL_CON0_SET -#define MT6685_TOP_CKSEL_CON0_SET_MASK 0xFF -#define MT6685_TOP_CKSEL_CON0_SET_SHIFT 0 -#define MT6685_TOP_CKSEL_CON0_CLR_ADDR \ - MT6685_TOP_CKSEL_CON0_CLR -#define MT6685_TOP_CKSEL_CON0_CLR_MASK 0xFF -#define MT6685_TOP_CKSEL_CON0_CLR_SHIFT 0 -#define MT6685_TOP_RST_MISC_CLR_ADDR \ - MT6685_TOP_RST_MISC_CLR -#define MT6685_TOP_RST_MISC_CLR_MASK 0xFF -#define MT6685_TOP_RST_MISC_CLR_SHIFT 0 - -#define MT6685_RG_SEQ_OFF_ADDR \ - MT6685_RG_SEQ_OFF -#define MT6685_RG_SEQ_OFF_MASK 0x1 -#define MT6685_RG_SEQ_OFF_SHIFT 0 -#define MT6685_TMA_KEY_ADDR \ - MT6685_TOP_TMA_KEY -#define MT6685_TMA_KEY_MASK 0xFF -#define MT6685_TMA_KEY_SHIFT 0 -#define MT6685_TMA_KEY_H_ADDR \ - MT6685_TOP_TMA_KEY_H -#define MT6685_TMA_KEY_H_MASK 0xFF -#define MT6685_TMA_KEY_H_SHIFT 0 -#define MT6685_DIG_WPK_KEY_ADDR \ - MT6685_TOP_DIG_WPK -#define MT6685_DIG_WPK_KEY_MASK 0xFF -#define MT6685_DIG_WPK_KEY_SHIFT 0 -#define MT6685_DIG_WPK_KEY_H_ADDR \ - MT6685_TOP_DIG_WPK_H -#define MT6685_DIG_WPK_KEY_H_MASK 0xFF -#define MT6685_DIG_WPK_KEY_H_SHIFT 0 -#define MT6685_SCK_TOP_XTAL_SEL_ADDR \ - MT6685_SCK_TOP_CON0_L -#define MT6685_SCK_TOP_XTAL_SEL_MASK 0x1 -#define MT6685_SCK_TOP_XTAL_SEL_SHIFT 0 -#define MT6685_RG_RTC_SEC_MCLK_PDN_ADDR \ - MT6685_SCK_TOP_CKPDN_CON0_L -#define MT6685_RG_RTC_SEC_MCLK_PDN_MASK 0x1 -#define MT6685_RG_RTC_SEC_MCLK_PDN_SHIFT 0 -#define MT6685_RG_RTC_EOSC32_CK_PDN_ADDR \ - MT6685_SCK_TOP_CKPDN_CON0_L -#define MT6685_RG_RTC_EOSC32_CK_PDN_MASK 0x1 -#define MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT 2 -#define MT6685_RG_RTC_SEC_32K_CK_PDN_ADDR \ - MT6685_SCK_TOP_CKPDN_CON0_L -#define MT6685_RG_RTC_SEC_32K_CK_PDN_MASK 0x1 -#define MT6685_RG_RTC_SEC_32K_CK_PDN_SHIFT 3 -#define MT6685_RG_RTC_MCLK_PDN_ADDR \ - MT6685_SCK_TOP_CKPDN_CON0_L -#define MT6685_RG_RTC_MCLK_PDN_MASK 0x1 -#define MT6685_RG_RTC_MCLK_PDN_SHIFT 4 -#define MT6685_RG_SHUTDOWN_SRC_SEL_ADDR \ - MT6685_SPMI_PWR_CMD -#define MT6685_RG_SHUTDOWN_SRC_SEL_MASK 0x1 -#define MT6685_RG_SHUTDOWN_SRC_SEL_SHIFT 1 -#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_ADDR \ - MT6685_SCK_TOP_CKPDN_CON0_L_SET -#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_MASK 0xFF -#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_SHIFT 0 -#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_ADDR \ - MT6685_SCK_TOP_CKPDN_CON0_L_CLR -#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_MASK 0xFF -#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_SHIFT 0 -#define MT6685_RG_BANK_FQMTR_RST_ADDR \ - MT6685_SCK_TOP_RST_CON0 -#define MT6685_RG_BANK_FQMTR_RST_MASK 0x1 -#define MT6685_RG_BANK_FQMTR_RST_SHIFT 6 -#define MT6685_RG_RTC_DIG_TEST_MODE_ADDR \ - MT6685_RTC_DIG_CON0_H -#define MT6685_RG_RTC_DIG_TEST_MODE_MASK 0x1 -#define MT6685_RG_RTC_DIG_TEST_MODE_SHIFT 7 -#define MT6685_FQMTR_TCKSEL_ADDR \ - MT6685_FQMTR_CON0_L -#define MT6685_FQMTR_TCKSEL_MASK 0x7 -#define MT6685_FQMTR_TCKSEL_SHIFT 0 -#define MT6685_FQMTR_BUSY_ADDR \ - MT6685_FQMTR_CON0_L -#define MT6685_FQMTR_BUSY_MASK 0x1 -#define MT6685_FQMTR_BUSY_SHIFT 3 -#define MT6685_FQMTR_DCXO26M_EN_ADDR \ - MT6685_FQMTR_CON0_L -#define MT6685_FQMTR_DCXO26M_EN_MASK 0x1 -#define MT6685_FQMTR_DCXO26M_EN_SHIFT 4 -#define MT6685_FQMTR_EN_ADDR \ - MT6685_FQMTR_CON0_H -#define MT6685_FQMTR_EN_MASK 0x1 -#define MT6685_FQMTR_EN_SHIFT 7 -#define MT6685_FQMTR_WINSET_L_ADDR \ - MT6685_FQMTR_CON1_L -#define MT6685_FQMTR_WINSET_L_MASK 0xFF -#define MT6685_FQMTR_WINSET_L_SHIFT 0 -#define MT6685_FQMTR_WINSET_H_ADDR \ - MT6685_FQMTR_CON1_H -#define MT6685_FQMTR_WINSET_H_MASK 0xFF -#define MT6685_FQMTR_WINSET_H_SHIFT 0 -#define MT6685_FQMTR_DATA_L_ADDR \ - MT6685_FQMTR_CON2_L -#define MT6685_FQMTR_DATA_L_MASK 0xFF -#define MT6685_FQMTR_DATA_L_SHIFT 0 -#define MT6685_RG_RTC_32K1V8_0_SEL_ADDR \ - MT6685_SCK_TOP_CKSEL_CON -#define MT6685_RG_RTC_32K1V8_0_SEL_MASK 0x3 -#define MT6685_RG_RTC_32K1V8_0_SEL_SHIFT 0 -#define MT6685_SPAR_SW_RELOAD_ADDR \ - MT6685_RTC_SPAR_RELOAD -#define MT6685_SPAR_SW_RELOAD_MASK 0x1 -#define MT6685_SPAR_SW_RELOAD_SHIFT 0 -#define MT6685_RTC_ANA_ID_ADDR \ - MT6685_RTC_ANA_ID -#define MT6685_RTC_ANA_ID_MASK 0xFF -#define MT6685_RTC_ANA_ID_SHIFT 0 -#define MT6685_RTC_DIG_ID_ADDR \ - MT6685_RTC_DIG_ID -#define MT6685_RTC_DIG_ID_MASK 0xFF -#define MT6685_RTC_DIG_ID_SHIFT 0 -#define MT6685_RTC_ANA_MINOR_REV_ADDR \ - MT6685_RTC_ANA_REV -#define MT6685_RTC_ANA_MINOR_REV_MASK 0xF -#define MT6685_RTC_ANA_MINOR_REV_SHIFT 0 -#define MT6685_RTC_ANA_MAJOR_REV_ADDR \ - MT6685_RTC_ANA_REV -#define MT6685_RTC_ANA_MAJOR_REV_MASK 0xF -#define MT6685_RTC_ANA_MAJOR_REV_SHIFT 4 -#define MT6685_RTC_DIG_MINOR_REV_ADDR \ - MT6685_RTC_DIG_REV -#define MT6685_RTC_DIG_MINOR_REV_MASK 0xF -#define MT6685_RTC_DIG_MINOR_REV_SHIFT 0 -#define MT6685_RTC_DIG_MAJOR_REV_ADDR \ - MT6685_RTC_DIG_REV -#define MT6685_RTC_DIG_MAJOR_REV_MASK 0xF -#define MT6685_RTC_DIG_MAJOR_REV_SHIFT 4 -#define MT6685_RTC_CBS_ADDR \ - MT6685_RTC_DBI -#define MT6685_RTC_CBS_MASK 0x3 -#define MT6685_RTC_CBS_SHIFT 0 -#define MT6685_RTC_BIX_ADDR \ - MT6685_RTC_DBI -#define MT6685_RTC_BIX_MASK 0x3 -#define MT6685_RTC_BIX_SHIFT 2 -#define MT6685_RTC_ESP_ADDR \ - MT6685_RTC_ESP -#define MT6685_RTC_ESP_MASK 0xFF -#define MT6685_RTC_ESP_SHIFT 0 -#define MT6685_RTC_FPI_ADDR \ - MT6685_RTC_FPI -#define MT6685_RTC_FPI_MASK 0xFF -#define MT6685_RTC_FPI_SHIFT 0 -#define MT6685_RTC_DXI_ADDR \ - MT6685_RTC_DXI -#define MT6685_RTC_DXI_MASK 0xFF -#define MT6685_RTC_DXI_SHIFT 0 -#define MT6685_BBPU_ADDR \ - MT6685_RTC_BBPU_L -#define MT6685_BBPU_MASK 0xF -#define MT6685_BBPU_SHIFT 0 -#define MT6685_CLRPKY_ADDR \ - MT6685_RTC_BBPU_L -#define MT6685_CLRPKY_MASK 0x1 -#define MT6685_CLRPKY_SHIFT 4 -#define MT6685_RELOAD_ADDR \ - MT6685_RTC_BBPU_L -#define MT6685_RELOAD_MASK 0x1 -#define MT6685_RELOAD_SHIFT 5 -#define MT6685_CBUSY_ADDR \ - MT6685_RTC_BBPU_L -#define MT6685_CBUSY_MASK 0x1 -#define MT6685_CBUSY_SHIFT 6 -#define MT6685_ALARM_STATUS_ADDR \ - MT6685_RTC_BBPU_L -#define MT6685_ALARM_STATUS_MASK 0x1 -#define MT6685_ALARM_STATUS_SHIFT 7 -#define MT6685_KEY_BBPU_ADDR \ - MT6685_RTC_BBPU_H -#define MT6685_KEY_BBPU_MASK 0xFF -#define MT6685_KEY_BBPU_SHIFT 0 -#define MT6685_ALSTA_ADDR \ - MT6685_RTC_IRQ_STA -#define MT6685_ALSTA_MASK 0x1 -#define MT6685_ALSTA_SHIFT 0 -#define MT6685_TCSTA_ADDR \ - MT6685_RTC_IRQ_STA -#define MT6685_TCSTA_MASK 0x1 -#define MT6685_TCSTA_SHIFT 1 -#define MT6685_LPSTA_ADDR \ - MT6685_RTC_IRQ_STA -#define MT6685_LPSTA_MASK 0x1 -#define MT6685_LPSTA_SHIFT 3 -#define MT6685_AL_EN_ADDR \ - MT6685_RTC_IRQ_EN -#define MT6685_AL_EN_MASK 0x1 -#define MT6685_AL_EN_SHIFT 0 -#define MT6685_TC_EN_ADDR \ - MT6685_RTC_IRQ_EN -#define MT6685_TC_EN_MASK 0x1 -#define MT6685_TC_EN_SHIFT 1 -#define MT6685_ONESHOT_ADDR \ - MT6685_RTC_IRQ_EN -#define MT6685_ONESHOT_MASK 0x1 -#define MT6685_ONESHOT_SHIFT 2 -#define MT6685_LP_EN_ADDR \ - MT6685_RTC_IRQ_EN -#define MT6685_LP_EN_MASK 0x1 -#define MT6685_LP_EN_SHIFT 3 -#define MT6685_SECCII_ADDR \ - MT6685_RTC_CII_EN_L -#define MT6685_SECCII_MASK 0x1 -#define MT6685_SECCII_SHIFT 0 -#define MT6685_MINCII_ADDR \ - MT6685_RTC_CII_EN_L -#define MT6685_MINCII_MASK 0x1 -#define MT6685_MINCII_SHIFT 1 -#define MT6685_HOUCII_ADDR \ - MT6685_RTC_CII_EN_L -#define MT6685_HOUCII_MASK 0x1 -#define MT6685_HOUCII_SHIFT 2 -#define MT6685_DOMCII_ADDR \ - MT6685_RTC_CII_EN_L -#define MT6685_DOMCII_MASK 0x1 -#define MT6685_DOMCII_SHIFT 3 -#define MT6685_DOWCII_ADDR \ - MT6685_RTC_CII_EN_L -#define MT6685_DOWCII_MASK 0x1 -#define MT6685_DOWCII_SHIFT 4 -#define MT6685_MTHCII_ADDR \ - MT6685_RTC_CII_EN_L -#define MT6685_MTHCII_MASK 0x1 -#define MT6685_MTHCII_SHIFT 5 -#define MT6685_YEACII_ADDR \ - MT6685_RTC_CII_EN_L -#define MT6685_YEACII_MASK 0x1 -#define MT6685_YEACII_SHIFT 6 -#define MT6685_SECCII_1_2_ADDR \ - MT6685_RTC_CII_EN_L -#define MT6685_SECCII_1_2_MASK 0x1 -#define MT6685_SECCII_1_2_SHIFT 7 -#define MT6685_SECCII_1_4_ADDR \ - MT6685_RTC_CII_EN_H -#define MT6685_SECCII_1_4_MASK 0x1 -#define MT6685_SECCII_1_4_SHIFT 0 -#define MT6685_SECCII_1_8_ADDR \ - MT6685_RTC_CII_EN_H -#define MT6685_SECCII_1_8_MASK 0x1 -#define MT6685_SECCII_1_8_SHIFT 1 -#define MT6685_SEC_MSK_ADDR \ - MT6685_RTC_AL_MASK -#define MT6685_SEC_MSK_MASK 0x1 -#define MT6685_SEC_MSK_SHIFT 0 -#define MT6685_MIN_MSK_ADDR \ - MT6685_RTC_AL_MASK -#define MT6685_MIN_MSK_MASK 0x1 -#define MT6685_MIN_MSK_SHIFT 1 -#define MT6685_HOU_MSK_ADDR \ - MT6685_RTC_AL_MASK -#define MT6685_HOU_MSK_MASK 0x1 -#define MT6685_HOU_MSK_SHIFT 2 -#define MT6685_DOM_MSK_ADDR \ - MT6685_RTC_AL_MASK -#define MT6685_DOM_MSK_MASK 0x1 -#define MT6685_DOM_MSK_SHIFT 3 -#define MT6685_DOW_MSK_ADDR \ - MT6685_RTC_AL_MASK -#define MT6685_DOW_MSK_MASK 0x1 -#define MT6685_DOW_MSK_SHIFT 4 -#define MT6685_MTH_MSK_ADDR \ - MT6685_RTC_AL_MASK -#define MT6685_MTH_MSK_MASK 0x1 -#define MT6685_MTH_MSK_SHIFT 5 -#define MT6685_YEA_MSK_ADDR \ - MT6685_RTC_AL_MASK -#define MT6685_YEA_MSK_MASK 0x1 -#define MT6685_YEA_MSK_SHIFT 6 -#define MT6685_TC_SECOND_ADDR \ - MT6685_RTC_TC_SEC -#define MT6685_TC_SECOND_MASK 0x3F -#define MT6685_TC_SECOND_SHIFT 0 -#define MT6685_TC_MINUTE_ADDR \ - MT6685_RTC_TC_MIN -#define MT6685_TC_MINUTE_MASK 0x3F -#define MT6685_TC_MINUTE_SHIFT 0 -#define MT6685_TC_HOUR_ADDR \ - MT6685_RTC_TC_HOU -#define MT6685_TC_HOUR_MASK 0x1F -#define MT6685_TC_HOUR_SHIFT 0 -#define MT6685_TC_DOM_ADDR \ - MT6685_RTC_TC_DOM -#define MT6685_TC_DOM_MASK 0x1F -#define MT6685_TC_DOM_SHIFT 0 -#define MT6685_TC_DOW_ADDR \ - MT6685_RTC_TC_DOW -#define MT6685_TC_DOW_MASK 0x7 -#define MT6685_TC_DOW_SHIFT 0 -#define MT6685_TC_MONTH_ADDR \ - MT6685_RTC_TC_MTH_L -#define MT6685_TC_MONTH_MASK 0xF -#define MT6685_TC_MONTH_SHIFT 0 -#define MT6685_RTC_MACRO_ID_L_ADDR \ - MT6685_RTC_TC_MTH_L -#define MT6685_RTC_MACRO_ID_L_MASK 0xF -#define MT6685_RTC_MACRO_ID_L_SHIFT 4 -#define MT6685_RTC_MACRO_ID_H_ADDR \ - MT6685_RTC_TC_MTH_H -#define MT6685_RTC_MACRO_ID_H_MASK 0xFF -#define MT6685_RTC_MACRO_ID_H_SHIFT 0 -#define MT6685_TC_YEAR_ADDR \ - MT6685_RTC_TC_YEA -#define MT6685_TC_YEAR_MASK 0x7F -#define MT6685_TC_YEAR_SHIFT 0 -#define MT6685_AL_SECOND_ADDR \ - MT6685_RTC_AL_SEC_L -#define MT6685_AL_SECOND_MASK 0x3F -#define MT6685_AL_SECOND_SHIFT 0 -#define MT6685_BBPU_AUTO_PDN_SEL_ADDR \ - MT6685_RTC_AL_SEC_L -#define MT6685_BBPU_AUTO_PDN_SEL_MASK 0x1 -#define MT6685_BBPU_AUTO_PDN_SEL_SHIFT 6 -#define MT6685_BBPU_2SEC_CK_SEL_ADDR \ - MT6685_RTC_AL_SEC_L -#define MT6685_BBPU_2SEC_CK_SEL_MASK 0x1 -#define MT6685_BBPU_2SEC_CK_SEL_SHIFT 7 -#define MT6685_BBPU_2SEC_EN_ADDR \ - MT6685_RTC_AL_SEC_H -#define MT6685_BBPU_2SEC_EN_MASK 0x1 -#define MT6685_BBPU_2SEC_EN_SHIFT 0 -#define MT6685_BBPU_2SEC_MODE_ADDR \ - MT6685_RTC_AL_SEC_H -#define MT6685_BBPU_2SEC_MODE_MASK 0x3 -#define MT6685_BBPU_2SEC_MODE_SHIFT 1 -#define MT6685_BBPU_2SEC_STAT_CLEAR_ADDR \ - MT6685_RTC_AL_SEC_H -#define MT6685_BBPU_2SEC_STAT_CLEAR_MASK 0x1 -#define MT6685_BBPU_2SEC_STAT_CLEAR_SHIFT 3 -#define MT6685_BBPU_2SEC_STAT_STA_ADDR \ - MT6685_RTC_AL_SEC_H -#define MT6685_BBPU_2SEC_STAT_STA_MASK 0x1 -#define MT6685_BBPU_2SEC_STAT_STA_SHIFT 4 -#define MT6685_RTC_LPD_OPT_ADDR \ - MT6685_RTC_AL_SEC_H -#define MT6685_RTC_LPD_OPT_MASK 0x3 -#define MT6685_RTC_LPD_OPT_SHIFT 5 -#define MT6685_K_EOSC32_VTCXO_ON_SEL_ADDR \ - MT6685_RTC_AL_SEC_H -#define MT6685_K_EOSC32_VTCXO_ON_SEL_MASK 0x1 -#define MT6685_K_EOSC32_VTCXO_ON_SEL_SHIFT 7 - -#define MT6685_AL_MINUTE_ADDR \ - MT6685_RTC_AL_MIN -#define MT6685_AL_MINUTE_MASK 0x3F -#define MT6685_AL_MINUTE_SHIFT 0 -#define MT6685_AL_HOUR_ADDR \ - MT6685_RTC_AL_HOU_L -#define MT6685_AL_HOUR_MASK 0x1F -#define MT6685_AL_HOUR_SHIFT 0 -#define MT6685_NEW_SPARE0_ADDR \ - MT6685_RTC_AL_HOU_H -#define MT6685_NEW_SPARE0_MASK 0xFF -#define MT6685_NEW_SPARE0_SHIFT 0 -#define MT6685_AL_DOM_ADDR \ - MT6685_RTC_AL_DOM_L -#define MT6685_AL_DOM_MASK 0x1F -#define MT6685_AL_DOM_SHIFT 0 -#define MT6685_NEW_SPARE1_ADDR \ - MT6685_RTC_AL_DOM_H -#define MT6685_NEW_SPARE1_MASK 0xFF -#define MT6685_NEW_SPARE1_SHIFT 0 -#define MT6685_AL_DOW_ADDR \ - MT6685_RTC_AL_DOW_L -#define MT6685_AL_DOW_MASK 0x7 -#define MT6685_AL_DOW_SHIFT 0 -#define MT6685_RG_EOSC_CALI_TD_ADDR \ - MT6685_RTC_AL_DOW_L -#define MT6685_RG_EOSC_CALI_TD_MASK 0x7 -#define MT6685_RG_EOSC_CALI_TD_SHIFT 5 -#define MT6685_NEW_SPARE2_ADDR \ - MT6685_RTC_AL_DOW_H -#define MT6685_NEW_SPARE2_MASK 0xFF -#define MT6685_NEW_SPARE2_SHIFT 0 -#define MT6685_AL_MONTH_ADDR \ - MT6685_RTC_AL_MTH_L -#define MT6685_AL_MONTH_MASK 0xF -#define MT6685_AL_MONTH_SHIFT 0 -#define MT6685_NEW_SPARE3_ADDR \ - MT6685_RTC_AL_MTH_H -#define MT6685_NEW_SPARE3_MASK 0xFF -#define MT6685_NEW_SPARE3_SHIFT 0 -#define MT6685_AL_YEAR_ADDR \ - MT6685_RTC_AL_YEA_L -#define MT6685_AL_YEAR_MASK 0x7F -#define MT6685_AL_YEAR_SHIFT 0 -#define MT6685_RTC_K_EOSC_RSV_ADDR \ - MT6685_RTC_AL_YEA_H -#define MT6685_RTC_K_EOSC_RSV_MASK 0xFF -#define MT6685_RTC_K_EOSC_RSV_SHIFT 0 -#define MT6685_XOSCCALI_ADDR \ - MT6685_RTC_OSC32CON_L -#define MT6685_XOSCCALI_MASK 0x1F -#define MT6685_XOSCCALI_SHIFT 0 -#define MT6685_RTC_XOSC32_ENB_ADDR \ - MT6685_RTC_OSC32CON_L -#define MT6685_RTC_XOSC32_ENB_MASK 0x1 -#define MT6685_RTC_XOSC32_ENB_SHIFT 5 -#define MT6685_RTC_EMBCK_SEL_MODE_ADDR \ - MT6685_RTC_OSC32CON_L -#define MT6685_RTC_EMBCK_SEL_MODE_MASK 0x3 -#define MT6685_RTC_EMBCK_SEL_MODE_SHIFT 6 -#define MT6685_RTC_EMBCK_SRC_SEL_ADDR \ - MT6685_RTC_OSC32CON_H - -#define MT6685_RTC_EMBCK_SRC_SEL_MASK 0x1 -#define MT6685_RTC_EMBCK_SRC_SEL_SHIFT 0 -#define MT6685_RTC_EMBCK_SEL_OPTION_ADDR \ - MT6685_RTC_OSC32CON_H -#define MT6685_RTC_EMBCK_SEL_OPTION_MASK 0x1 -#define MT6685_RTC_EMBCK_SEL_OPTION_SHIFT 1 -#define MT6685_RTC_GPS_CKOUT_EN_ADDR \ - MT6685_RTC_OSC32CON_H -#define MT6685_RTC_GPS_CKOUT_EN_MASK 0x1 -#define MT6685_RTC_GPS_CKOUT_EN_SHIFT 2 -#define MT6685_RTC_EOSC32_VCT_EN_ADDR \ - MT6685_RTC_OSC32CON_H -#define MT6685_RTC_EOSC32_VCT_EN_MASK 0x1 -#define MT6685_RTC_EOSC32_VCT_EN_SHIFT 3 -#define MT6685_RTC_EOSC32_CHOP_EN_ADDR \ - MT6685_RTC_OSC32CON_H -#define MT6685_RTC_EOSC32_CHOP_EN_MASK 0x1 -#define MT6685_RTC_EOSC32_CHOP_EN_SHIFT 4 -#define MT6685_RTC_GP_OSC32_CON_ADDR \ - MT6685_RTC_OSC32CON_H -#define MT6685_RTC_GP_OSC32_CON_MASK 0x3 -#define MT6685_RTC_GP_OSC32_CON_SHIFT 5 -#define MT6685_RTC_REG_XOSC32_ENB_ADDR \ - MT6685_RTC_OSC32CON_H -#define MT6685_RTC_REG_XOSC32_ENB_MASK 0x1 -#define MT6685_RTC_REG_XOSC32_ENB_SHIFT 7 -#define MT6685_RTC_POWERKEY1_L_ADDR \ - MT6685_RTC_POWERKEY1_L -#define MT6685_RTC_POWERKEY1_L_MASK 0xFF -#define MT6685_RTC_POWERKEY1_L_SHIFT 0 -#define MT6685_RTC_POWERKEY1_H_ADDR \ - MT6685_RTC_POWERKEY1_H -#define MT6685_RTC_POWERKEY1_H_MASK 0xFF -#define MT6685_RTC_POWERKEY1_H_SHIFT 0 -#define MT6685_RTC_POWERKEY2_L_ADDR \ - MT6685_RTC_POWERKEY2_L -#define MT6685_RTC_POWERKEY2_L_MASK 0xFF -#define MT6685_RTC_POWERKEY2_L_SHIFT 0 -#define MT6685_RTC_POWERKEY2_H_ADDR \ - MT6685_RTC_POWERKEY2_H -#define MT6685_RTC_POWERKEY2_H_MASK 0xFF -#define MT6685_RTC_POWERKEY2_H_SHIFT 0 -#define MT6685_RTC_PDN1_L_ADDR \ - MT6685_RTC_PDN1_L -#define MT6685_RTC_PDN1_L_MASK 0xFF -#define MT6685_RTC_PDN1_L_SHIFT 0 -#define MT6685_RTC_PDN1_H_ADDR \ - MT6685_RTC_PDN1_H -#define MT6685_RTC_PDN1_H_MASK 0xFF -#define MT6685_RTC_PDN1_H_SHIFT 0 -#define MT6685_RTC_PDN2_L_ADDR \ - MT6685_RTC_PDN2_L -#define MT6685_RTC_PDN2_L_MASK 0xFF -#define MT6685_RTC_PDN2_L_SHIFT 0 -#define MT6685_RTC_PDN2_H_ADDR \ - MT6685_RTC_PDN2_H -#define MT6685_RTC_PDN2_H_MASK 0xFF -#define MT6685_RTC_PDN2_H_SHIFT 0 -#define MT6685_RTC_SPAR0_L_ADDR \ - MT6685_RTC_SPAR0_L -#define MT6685_RTC_SPAR0_L_MASK 0xFF -#define MT6685_RTC_SPAR0_L_SHIFT 0 -#define MT6685_RTC_SPAR0_H_ADDR \ - MT6685_RTC_SPAR0_H -#define MT6685_RTC_SPAR0_H_MASK 0xFF -#define MT6685_RTC_SPAR0_H_SHIFT 0 -#define MT6685_RTC_SPAR1_L_ADDR \ - MT6685_RTC_SPAR1_L -#define MT6685_RTC_SPAR1_L_MASK 0xFF -#define MT6685_RTC_SPAR1_L_SHIFT 0 -#define MT6685_RTC_SPAR1_H_ADDR \ - MT6685_RTC_SPAR1_H -#define MT6685_RTC_SPAR1_H_MASK 0xFF -#define MT6685_RTC_SPAR1_H_SHIFT 0 -#define MT6685_RTC_PROT_L_ADDR \ - MT6685_RTC_PROT_L -#define MT6685_RTC_PROT_L_MASK 0xFF -#define MT6685_RTC_PROT_L_SHIFT 0 -#define MT6685_RTC_PROT_H_ADDR \ - MT6685_RTC_PROT_H -#define MT6685_RTC_PROT_H_MASK 0xFF -#define MT6685_RTC_PROT_H_SHIFT 0 -#define MT6685_RTC_DIFF_L_ADDR \ - MT6685_RTC_DIFF_L -#define MT6685_RTC_DIFF_L_MASK 0xFF -#define MT6685_RTC_DIFF_L_SHIFT 0 -#define MT6685_RTC_DIFF_H_ADDR \ - MT6685_RTC_DIFF_H -#define MT6685_RTC_DIFF_H_MASK 0xF -#define MT6685_RTC_DIFF_H_SHIFT 0 -#define MT6685_POWER_DETECTED_ADDR \ - MT6685_RTC_DIFF_H -#define MT6685_POWER_DETECTED_MASK 0x1 -#define MT6685_POWER_DETECTED_SHIFT 4 -#define MT6685_K_EOSC32_RSV_ADDR \ - MT6685_RTC_DIFF_H -#define MT6685_K_EOSC32_RSV_MASK 0x1 -#define MT6685_K_EOSC32_RSV_SHIFT 6 -#define MT6685_CALI_RD_SEL_ADDR \ - MT6685_RTC_DIFF_H -#define MT6685_CALI_RD_SEL_MASK 0x1 -#define MT6685_CALI_RD_SEL_SHIFT 7 -#define MT6685_RTC_CALI_L_ADDR \ - MT6685_RTC_CALI_L -#define MT6685_RTC_CALI_L_MASK 0xFF -#define MT6685_RTC_CALI_L_SHIFT 0 -#define MT6685_RTC_CALI_H_ADDR \ - MT6685_RTC_CALI_H -#define MT6685_RTC_CALI_H_MASK 0x3F -#define MT6685_RTC_CALI_H_SHIFT 0 -#define MT6685_CALI_WR_SEL_ADDR \ - MT6685_RTC_CALI_H -#define MT6685_CALI_WR_SEL_MASK 0x1 -#define MT6685_CALI_WR_SEL_SHIFT 6 -#define MT6685_K_EOSC32_OVERFLOW_ADDR \ - MT6685_RTC_CALI_H -#define MT6685_K_EOSC32_OVERFLOW_MASK 0x1 -#define MT6685_K_EOSC32_OVERFLOW_SHIFT 7 -#define MT6685_WRTGR_ADDR \ - MT6685_RTC_WRTGR -#define MT6685_WRTGR_MASK 0x1 -#define MT6685_WRTGR_SHIFT 0 -#define MT6685_VBAT_LPSTA_RAW_ADDR \ - MT6685_RTC_CON_L -#define MT6685_VBAT_LPSTA_RAW_MASK 0x1 -#define MT6685_VBAT_LPSTA_RAW_SHIFT 0 -#define MT6685_EOSC32_LPEN_ADDR \ - MT6685_RTC_CON_L -#define MT6685_EOSC32_LPEN_MASK 0x1 -#define MT6685_EOSC32_LPEN_SHIFT 1 -#define MT6685_XOSC32_LPEN_ADDR \ - MT6685_RTC_CON_L -#define MT6685_XOSC32_LPEN_MASK 0x1 -#define MT6685_XOSC32_LPEN_SHIFT 2 -#define MT6685_LPRST_ADDR \ - MT6685_RTC_CON_L -#define MT6685_LPRST_MASK 0x1 -#define MT6685_LPRST_SHIFT 3 -#define MT6685_CDBO_ADDR \ - MT6685_RTC_CON_L - -#define MT6685_CDBO_MASK 0x1 -#define MT6685_CDBO_SHIFT 4 -#define MT6685_F32KOB_ADDR \ - MT6685_RTC_CON_L -#define MT6685_F32KOB_MASK 0x1 -#define MT6685_F32KOB_SHIFT 5 -#define MT6685_GPO_ADDR \ - MT6685_RTC_CON_L -#define MT6685_GPO_MASK 0x1 -#define MT6685_GPO_SHIFT 6 -#define MT6685_GOE_ADDR \ - MT6685_RTC_CON_L -#define MT6685_GOE_MASK 0x1 -#define MT6685_GOE_SHIFT 7 -#define MT6685_GSR_ADDR \ - MT6685_RTC_CON_H -#define MT6685_GSR_MASK 0x1 -#define MT6685_GSR_SHIFT 0 -#define MT6685_GSMT_ADDR \ - MT6685_RTC_CON_H -#define MT6685_GSMT_MASK 0x1 -#define MT6685_GSMT_SHIFT 1 -#define MT6685_GPEN_ADDR \ - MT6685_RTC_CON_H -#define MT6685_GPEN_MASK 0x1 -#define MT6685_GPEN_SHIFT 2 -#define MT6685_GPU_ADDR \ - MT6685_RTC_CON_H -#define MT6685_GPU_MASK 0x1 -#define MT6685_GPU_SHIFT 3 -#define MT6685_GE4_ADDR \ - MT6685_RTC_CON_H -#define MT6685_GE4_MASK 0x1 -#define MT6685_GE4_SHIFT 4 -#define MT6685_GE8_ADDR \ - MT6685_RTC_CON_H -#define MT6685_GE8_MASK 0x1 -#define MT6685_GE8_SHIFT 5 -#define MT6685_GPI_ADDR \ - MT6685_RTC_CON_H -#define MT6685_GPI_MASK 0x1 -#define MT6685_GPI_SHIFT 6 -#define MT6685_LPSTA_RAW_ADDR \ - MT6685_RTC_CON_H -#define MT6685_LPSTA_RAW_MASK 0x1 -#define MT6685_LPSTA_RAW_SHIFT 7 -#define MT6685_DAT0_LOCK_ADDR \ - MT6685_RTC_SEC_CTRL -#define MT6685_DAT0_LOCK_MASK 0x1 -#define MT6685_DAT0_LOCK_SHIFT 0 -#define MT6685_DAT1_LOCK_ADDR \ - MT6685_RTC_SEC_CTRL -#define MT6685_DAT1_LOCK_MASK 0x1 -#define MT6685_DAT1_LOCK_SHIFT 1 -#define MT6685_DAT2_LOCK_ADDR \ - MT6685_RTC_SEC_CTRL -#define MT6685_DAT2_LOCK_MASK 0x1 -#define MT6685_DAT2_LOCK_SHIFT 2 -#define MT6685_RTC_INT_CNT_L_ADDR \ - MT6685_RTC_INT_CNT_L -#define MT6685_RTC_INT_CNT_L_MASK 0xFF -#define MT6685_RTC_INT_CNT_L_SHIFT 0 -#define MT6685_RTC_INT_CNT_H_ADDR \ - MT6685_RTC_INT_CNT_H -#define MT6685_RTC_INT_CNT_H_MASK 0x7F -#define MT6685_RTC_INT_CNT_H_SHIFT 0 -#define MT6685_RTC_SEC_DAT0_L_ADDR \ - MT6685_RTC_SEC_DAT0_L -#define MT6685_RTC_SEC_DAT0_L_MASK 0xFF -#define MT6685_RTC_SEC_DAT0_L_SHIFT 0 -#define MT6685_RTC_SEC_DAT0_H_ADDR \ - MT6685_RTC_SEC_DAT0_H -#define MT6685_RTC_SEC_DAT0_H_MASK 0xFF -#define MT6685_RTC_SEC_DAT0_H_SHIFT 0 -#define MT6685_RTC_SEC_DAT1_L_ADDR \ - MT6685_RTC_SEC_DAT1_L -#define MT6685_RTC_SEC_DAT1_L_MASK 0xFF -#define MT6685_RTC_SEC_DAT1_L_SHIFT 0 -#define MT6685_RTC_SEC_DAT1_H_ADDR \ - MT6685_RTC_SEC_DAT1_H -#define MT6685_RTC_SEC_DAT1_H_MASK 0xFF -#define MT6685_RTC_SEC_DAT1_H_SHIFT 0 -#define MT6685_RTC_SEC_DAT2_L_ADDR \ - MT6685_RTC_SEC_DAT2_L -#define MT6685_RTC_SEC_DAT2_L_MASK 0xFF -#define MT6685_RTC_SEC_DAT2_L_SHIFT 0 -#define MT6685_RTC_SEC_DAT2_H_ADDR \ - MT6685_RTC_SEC_DAT2_H -#define MT6685_RTC_SEC_DAT2_H_MASK 0xFF -#define MT6685_RTC_SEC_DAT2_H_SHIFT 0 -#define MT6685_RTC_RG_FG0_ADDR \ - MT6685_RTC_RG_FG0 -#define MT6685_RTC_RG_FG0_MASK 0xFF -#define MT6685_RTC_RG_FG0_SHIFT 0 -#define MT6685_RTC_RG_FG1_ADDR \ - MT6685_RTC_RG_FG1 -#define MT6685_RTC_RG_FG1_MASK 0xFF -#define MT6685_RTC_RG_FG1_SHIFT 0 -#define MT6685_RTC_RG_FG2_ADDR \ - MT6685_RTC_RG_FG2 -#define MT6685_RTC_RG_FG2_MASK 0xFF -#define MT6685_RTC_RG_FG2_SHIFT 0 -#define MT6685_RTC_RG_FG3_ADDR \ - MT6685_RTC_RG_FG3 -#define MT6685_RTC_RG_FG3_MASK 0xFF -#define MT6685_RTC_RG_FG3_SHIFT a - -#define MT6685_RTC_UVLO_WAIT_ADDR \ - MT6685_RTC_SPAR_MACRO -#define MT6685_RTC_UVLO_WAIT_MASK 0x3 -#define MT6685_RTC_UVLO_WAIT_SHIFT 0 -#define MT6685_RTC_SPAR_THRE_SEL_ADDR \ - MT6685_RTC_SPAR_MACRO -#define MT6685_RTC_SPAR_THRE_SEL_MASK 0x1 -#define MT6685_RTC_SPAR_THRE_SEL_SHIFT 2 -#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_ADDR \ - MT6685_RTC_SPAR_MACRO -#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_MASK 0x1 -#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_SHIFT 4 -#define MT6685_RTC_SPAR_PWRKEY_MATCH_ADDR \ - MT6685_RTC_SPAR_MACRO -#define MT6685_RTC_SPAR_PWRKEY_MATCH_MASK 0x1 -#define MT6685_RTC_SPAR_PWRKEY_MATCH_SHIFT 5 -#define MT6685_SPAR_PROT_STAT_ADDR \ - MT6685_RTC_SPAR_MACRO -#define MT6685_RTC_SPAR_PROT_STAT_MASK 0x3 -#define MT6685_RTC_SPAR_PROT_STAT_SHIFT 6 -#define MT6685_RTC_SPAR_CORE_ADDR \ - MT6685_RTC_SPAR_CORE -#define MT6685_RTC_SPAR_CORE_MASK 0xFF -#define MT6685_RTC_SPAR_CORE_SHIFT 0 -#define MT6685_RTC_RG_EOSC_CALI_ADDR \ - MT6685_RTC_EOSC_CALI -#define MT6685_RTC_RG_EOSC_CALI_MASK 0x1F -#define MT6685_RTC_RG_EOSC_CALI_SHIFT 0 -#define MT6685_RTC_SEC_ANA_ID_ADDR \ - MT6685_RTC_SEC_ANA_ID -#define MT6685_RTC_SEC_ANA_ID_MASK 0xFF -#define MT6685_RTC_SEC_ANA_ID_SHIFT 0 -#define MT6685_RTC_SEC_DIG_ID_ADDR \ - MT6685_RTC_SEC_DIG_ID -#define MT6685_RTC_SEC_DIG_ID_MASK 0xFF -#define MT6685_RTC_SEC_DIG_ID_SHIFT 0 -#define MT6685_RTC_SEC_ANA_MINOR_REV_ADDR \ - MT6685_RTC_SEC_ANA_REV -#define MT6685_RTC_SEC_ANA_MINOR_REV_MASK 0xF -#define MT6685_RTC_SEC_ANA_MINOR_REV_SHIFT 0 -#define MT6685_RTC_SEC_ANA_MAJOR_REV_ADDR \ - MT6685_RTC_SEC_ANA_REV -#define MT6685_RTC_SEC_ANA_MAJOR_REV_MASK 0xF -#define MT6685_RTC_SEC_ANA_MAJOR_REV_SHIFT 4 -#define MT6685_RTC_SEC_DIG_MINOR_REV_ADDR \ - MT6685_RTC_SEC_DIG_REV -#define MT6685_RTC_SEC_DIG_MINOR_REV_MASK 0xF -#define MT6685_RTC_SEC_DIG_MINOR_REV_SHIFT 0 -#define MT6685_RTC_SEC_DIG_MAJOR_REV_ADDR \ - MT6685_RTC_SEC_DIG_REV -#define MT6685_RTC_SEC_DIG_MAJOR_REV_MASK 0xF -#define MT6685_RTC_SEC_DIG_MAJOR_REV_SHIFT 4 -#define MT6685_RTC_SEC_CBS_ADDR \ - MT6685_RTC_SEC_DBI -#define MT6685_RTC_SEC_CBS_MASK 0x3 -#define MT6685_RTC_SEC_CBS_SHIFT 0 -#define MT6685_RTC_SEC_BIX_ADDR \ - MT6685_RTC_SEC_DBI -#define MT6685_RTC_SEC_BIX_MASK 0x3 -#define MT6685_RTC_SEC_BIX_SHIFT 2 -#define MT6685_RTC_SEC_ESP_ADDR \ - MT6685_RTC_SEC_ESP -#define MT6685_RTC_SEC_ESP_MASK 0xFF -#define MT6685_RTC_SEC_ESP_SHIFT 0 -#define MT6685_RTC_SEC_FPI_ADDR \ - MT6685_RTC_SEC_FPI -#define MT6685_RTC_SEC_FPI_MASK 0xFF -#define MT6685_RTC_SEC_FPI_SHIFT 0 -#define MT6685_RTC_SEC_DXI_ADDR \ - MT6685_RTC_SEC_DXI -#define MT6685_RTC_SEC_DXI_MASK 0xFF -#define MT6685_RTC_SEC_DXI_SHIFT 0 -#define MT6685_TC_SECOND_SEC_ADDR \ - MT6685_RTC_TC_SEC_SEC -#define MT6685_TC_SECOND_SEC_MASK 0x3F -#define MT6685_TC_SECOND_SEC_SHIFT 0 -#define MT6685_TC_MINUTE_SEC_ADDR \ - MT6685_RTC_TC_MIN_SEC -#define MT6685_TC_MINUTE_SEC_MASK 0x3F -#define MT6685_TC_MINUTE_SEC_SHIFT 0 -#define MT6685_TC_HOUR_SEC_ADDR \ - MT6685_RTC_TC_HOU_SEC -#define MT6685_TC_HOUR_SEC_MASK 0x1F -#define MT6685_TC_HOUR_SEC_SHIFT 0 -#define MT6685_TC_DOM_SEC_ADDR \ - MT6685_RTC_TC_DOM_SEC -#define MT6685_TC_DOM_SEC_MASK 0x1F -#define MT6685_TC_DOM_SEC_SHIFT 0 -#define MT6685_TC_DOW_SEC_ADDR \ - MT6685_RTC_TC_DOW_SEC -#define MT6685_TC_DOW_SEC_MASK 0x7 -#define MT6685_TC_DOW_SEC_SHIFT 0 -#define MT6685_TC_MONTH_SEC_ADDR \ - MT6685_RTC_TC_MTH_SEC -#define MT6685_TC_MONTH_SEC_MASK 0xF -#define MT6685_TC_MONTH_SEC_SHIFT 0 -#define MT6685_TC_YEAR_SEC_ADDR \ - MT6685_RTC_TC_YEA_SEC -#define MT6685_TC_YEAR_SEC_MASK 0x7F -#define MT6685_TC_YEAR_SEC_SHIFT 0 -#define MT6685_RTC_SEC_CK_PDN_ADDR \ - MT6685_RTC_SEC_CK_PDN -#define MT6685_RTC_SEC_CK_PDN_MASK 0x1 -#define MT6685_RTC_SEC_CK_PDN_SHIFT 0 -#define MT6685_RTC_SEC_WRTGR_ADDR \ - MT6685_RTC_SEC_WRTGR -#define MT6685_RTC_SEC_WRTGR_MASK 0x1 -#define MT6685_RTC_SEC_WRTGR_SHIFT 0 -#define MT6685_XO_EN32K_MAN_ADDR \ - MT6685_DCXO_DIG_MODE_CW0 -#define MT6685_XO_EN32K_MAN_MASK 0x1 -#define MT6685_XO_EN32K_MAN_SHIFT 1 - -#endif /* SOC_MEDIATEK_MT8196_MT6685_HW_H */ diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h index ddae65e..cc9e3bf 100644 --- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h +++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h @@ -8,78 +8,141 @@ #ifndef SOC_MEDIATEK_MT8196_MT6685_RTC_H #define SOC_MEDIATEK_MT8196_MT6685_RTC_H -#include <commonlib/bsd/bcd.h> -#include <console/console.h> -#include <rtc.h> -#include <stdbool.h> -#include <timer.h> +#define RG_BANK_FQMTR_RST 0x522 +#define RG_BANK_FQMTR_RST_MASK 0x1 +#define RG_BANK_FQMTR_RST_SHIFT 6 -/* frequency meter related */ -#define RG_BANK_FQMTR_RST MT6685_RG_BANK_FQMTR_RST_ADDR -#define RG_BANK_FQMTR_RST_MASK MT6685_RG_BANK_FQMTR_RST_MASK -#define RG_BANK_FQMTR_RST_SHIFT MT6685_RG_BANK_FQMTR_RST_SHIFT -#define RG_FQMTR_TCKSEL MT6685_FQMTR_TCKSEL_ADDR -#define RG_FQMTR_WINSET MT6685_FQMTR_WINSET_L_ADDR -#define RG_FQMTR_BUSY MT6685_FQMTR_BUSY_ADDR -#define RG_FQMTR_DCXO26M_EN MT6685_FQMTR_DCXO26M_EN_ADDR -#define RG_FQMTR_DCXO26M_MASK MT6685_FQMTR_DCXO26M_EN_MASK -#define RG_FQMTR_DCXO26M_SHIFT MT6685_FQMTR_DCXO26M_EN_SHIFT -#define RG_FQMTR_DATA MT6685_FQMTR_DATA_L_ADDR -#define RG_FQMTR_EN MT6685_FQMTR_EN_ADDR -#define RG_FQMTR_EN_MASK MT6685_FQMTR_EN_MASK -#define RG_FQMTR_EN_SHIFT MT6685_FQMTR_EN_SHIFT +#define TOP_DIG_WPK 0x3a8 +#define DIG_WPK_KEY_MASK 0xFF +#define DIG_WPK_KEY_SHIFT 0 -#define RG_FQMTR_32K_CK_PDN_SET MT6685_TOP_CKPDN_CON0_SET_ADDR -#define RG_FQMTR_32K_CK_PDN_CLR MT6685_TOP_CKPDN_CON0_CLR_ADDR -#define RG_FQMTR_32K_CK_PDN_MASK MT6685_RG_FQMTR_32K_CK_PDN_MASK -#define RG_FQMTR_32K_CK_PDN_SHIFT MT6685_RG_FQMTR_32K_CK_PDN_SHIFT +#define TOP_DIG_WPK_H 0x3a9 +#define DIG_WPK_KEY_H_MASK 0xFF +#define DIG_WPK_KEY_H_SHIFT 0 -#define RG_FQMTR_CLK_CK_PDN_SET MT6685_TOP_CKPDN_CON0_SET_ADDR -#define RG_FQMTR_CLK_CK_PDN_CLR MT6685_TOP_CKPDN_CON0_CLR_ADDR -#define RG_FQMTR_CLK_CK_PDN_MASK MT6685_RG_FQMTR_CK_PDN_MASK -#define RG_FQMTR_CLK_CK_PDN_SHIFT MT6685_RG_FQMTR_CK_PDN_SHIFT +#define RG_FQMTR_CLK_CK_PDN_CLR 0x10d +#define RG_FQMTR_CLK_CK_PDN_MASK 0x1 +#define RG_FQMTR_CLK_CK_PDN_SHIFT 5 -#define RG_FQMTR_CKSEL MT6685_RG_FQMTR_CK_CKSEL_ADDR -#define RG_FQMTR_CKSEL_SET MT6685_TOP_CKSEL_CON0_SET_ADDR -#define RG_FQMTR_CKSEL_CLR MT6685_TOP_CKSEL_CON0_CLR_ADDR -#define RG_FQMTR_CKSEL_MASK MT6685_RG_FQMTR_CK_CKSEL_MASK -#define RG_FQMTR_CKSEL_SHIFT MT6685_RG_FQMTR_CK_CKSEL_SHIFT -#define RG_FQMTR_TCKSEL_MASK MT6685_FQMTR_TCKSEL_MASK -#define RG_FQMTR_TCKSEL_SHIFT MT6685_FQMTR_TCKSEL_SHIFT +#define RG_FQMTR_32K_CK_PDN_CLR 0x10d +#define RG_FQMTR_32K_CK_PDN_MASK 0x1 +#define RG_FQMTR_32K_CK_PDN_SHIFT 4 -#define FQMTR_FIX_CLK_26M (0 << RG_FQMTR_CKSEL_SHIFT) -#define FQMTR_FIX_CLK_XOSC_32K_DET (1 << RG_FQMTR_CKSEL_SHIFT) -#define FQMTR_FIX_CLK_EOSC_32K (2 << RG_FQMTR_CKSEL_SHIFT) -#define FQMTR_FIX_CLK_RTC_32K (3 << RG_FQMTR_CKSEL_SHIFT) -#define FQMTR_FIX_CLK_SMPS_CK (4 << RG_FQMTR_CKSEL_SHIFT) -#define FQMTR_FIX_CLK_TCK_SEC (5 << RG_FQMTR_CKSEL_SHIFT) -#define FQMTR_FIX_CLK_PMU_75K (6 << RG_FQMTR_CKSEL_SHIFT) +#define RG_FQMTR_DCXO26M_EN 0x546 +#define RG_FQMTR_DCXO26M_MASK 0x1 +#define RG_FQMTR_DCXO26M_SHIFT 4 -#define BANK_FQMTR_RST BIT(6) -#define FQMTR_EN BIT(7) -#define FQMTR_BUSY BIT(3) -#define FQMTR_DCXO26M_EN BIT(4) -#define FQMTR_XOSC32_CK 0 -#define FQMTR_DCXO_F32K_CK 1 -#define FQMTR_EOSC32_CK 2 -#define FQMTR_XOSC32_CK_DETECTON 3 +#define RG_FQMTR_WINSET 0x548 + +#define RG_FQMTR_TCKSEL 0x546 +#define RG_FQMTR_TCKSEL_MASK 0x7 +#define RG_FQMTR_TCKSEL_SHIFT 0 + +#define FQMTR_DCXO26M_EN (1 << 4) + +#define RG_FQMTR_EN 0x547 +#define RG_FQMTR_EN_MASK 0x1 +#define RG_FQMTR_EN_SHIFT 7 + +#define RG_FQMTR_BUSY 0x546 +#define FQMTR_BUSY (1 << 3) + +#define RG_FQMTR_DATA 0x54a + +#define RG_FQMTR_CLK_CK_PDN_SET 0x10c +#define RG_FQMTR_CLK_CK_PDN_MASK 0x1 +#define RG_FQMTR_CLK_CK_PDN_SHIFT 5 + +#define RG_FQMTR_32K_CK_PDN_SET 0x10c +#define RG_FQMTR_32K_CK_PDN_MASK 0x1 +#define RG_FQMTR_32K_CK_PDN_SHIFT 4 + +#define RG_FQMTR_CKSEL 0x111 +#define FQMTR_FIX_CLK_26M 0 +#define RG_FQMTR_CKSEL_MASK 0x7 +#define RG_FQMTR_CKSEL_SHIFT 0 + #define FQMTR_FQM26M_CK 4 -#define FQMTR_FQM32K_CK 5 -#define FQMTR_TEST_CK 6 -#define FQMTR_WINSET 0x0000 +#define FQMTR_DCXO_F32K_CK 1 +#define FQMTR_FIX_CLK_EOSC_32K 2 -#define RG_75K_32K_SEL MT6685_TOP_CKSEL_CON0_CLR_ADDR -#define RTC_75K_TO_32K BIT(0) +#define OSC32CON_ANALOG_SETTING (RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | \ + RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | \ + RTC_EMBCK_SEL_OPTION | RTC_EMBCK_SEL_K_EOSC) +#define RTC_GP_OSC32_CON (2U << (5 + 8)) +#define RTC_EOSC32_CHOP_EN (1 << (4 + 8)) +#define RTC_EOSC32_VCT_EN (1 << (3 + 8)) +#define RTC_EMBCK_SEL_K_EOSC (1U << 6) -#define RG_OCT1_RTC32K_1V8_0 MT6685_RG_OCT1_IO_0 + +#define RTC_XOSC32_LPEN (1 << 2) +#define RTC_EOSC32_LPEN (1 << 1) + +#define RTC_BBPU_RESET_ALARM (1 << 3) +#define RTC_BBPU_RESET_SPAR (1 << 2) +#define RTC_BBPU_SPAR_SW (1 << 1) + +#define RTC_XOSC32_LPEN (1 << 2) + +#define RTC_PDN1_PWRON_TIME (1 << 7) + +#define RTC_WRTGR_SEC 0x618 + +#define RG_RTC_SEC_MCLK_PDN_MASK 0x1 +#define RG_RTC_SEC_32K_CK_PDN_MASK 0x1 +#define RG_RTC_SEC_32K_CK_PDN_SHIFT 3 + +#define RTC_SEC_CK_PDN 0x616 +#define SCK_TOP_CKPDN_CON0_L 0x514 +#define RTC_SEC_DSN_ID 0x600 +#define RTC_SEC_DSN_REV0 0x602 + +#define RTC_TC_YEA_SEC 0x614 +#define RTC_TC_MTH_SEC 0x612 +#define RTC_TC_DOM_SEC 0x60e +#define RTC_TC_DOW_SEC 0x610 +#define RTC_TC_HOU_SEC 0x60c +#define RTC_TC_MIN_SEC 0x60a +#define RTC_TC_SEC_SEC 0x608 + +#define RTC_K_EOSC32_VTCXO_ON_SEL (1 << (7 + 8)) +#define RTC_AL_YEA_MASK (0x7F << 0) +#define RTC_K_EOSC_RSV_7 (1 << 15) +#define RTC_K_EOSC_RSV_6 (1 << 14) + +#define RTC_POWER_DETECTED (1 << (4 + 8)) + +#define RTC_K_EOSC_RSV_0 (1 << 8) +#define RTC_K_EOSC_RSV_1 (1 << 9) +#define RTC_K_EOSC_RSV_2 (1 << 10) + +#define TMA_KEY 0x39e +#define TMA_KEY_MASK 0xFF +#define TMA_KEY_SHIFT 0 +#define TMA_KEY_H 0x39f +#define TMA_KEY_H_MASK 0xFF +#define TMA_KEY_H_SHIFT 0 + +#define RG_OCT1_RTC32K_1V8_0 0xa7 #define RG_OCT1_RTC32K_1V8_0_MASK 0x3 #define RG_OCT1_RTC32K_1V8_0_SHIFT 5 -#define RG_OCT1_RTC32K_1V8_F MT6685_RG_OCT1_IO_1 +#define RG_OCT1_RTC32K_1V8_F 0xa8 #define RG_OCT1_RTC32K_1V8_F_MASK 0x3 #define RG_OCT1_RTC32K_1V8_F_SHIFT 1 -#define HWCID_L MT6685_HWCID_L +#define SCK_TOP_CKSEL_CON 0x568 +#define R_SCK32K_CK_MASK 0x1 +#define R_SCK32K_CK_SHIFT 0 + +#define SCK_TOP_CKPDN_CON0_L_SET 0x515 +#define RG_RTC_EOSC32_CK_PDN_MASK 0x1 +#define RG_RTC_EOSC32_CK_PDN_SHIFT 2 + +#define RTC_TC_MTH_MASK 0xF + +#define SCK_TOP_CKPDN_CON0_L_CLR 0x516 +#define SCK_TOP_CKPDN_CON0_L_CLR_SHIFT 0 /* Complete the RTC initialization process and register settings. */ void rtc_boot(void); diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h deleted file mode 100644 index d2152c8..0000000 --- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h +++ /dev/null @@ -1,372 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -/* - * This file is created based on MT8196 Functional Specification - * Chapter number: 14.2.4 - */ - -#ifndef SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H -#define SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H - -#include <soc/mt6685_hw.h> -#include <soc/rtc.h> - -/* RTC_BBPU bit field */ -#define MT6685_PWREN_SHIFT 0 -#define MT6685_PWREN_MASK 0x1 -#define MT6685_SPAR_SW_SHIFT 1 -#define MT6685_SPAR_SW_MASK 0x1 -#define MT6685_RESET_SPAR_SHIFT 2 -#define MT6685_RESET_SPAR_MASK 0x1 -#define MT6685_RESET_ALARM_SHIFT 3 -#define MT6685_RESET_ALARM_MASK 0x1 - -/* RTC registers */ -#define RTC_BBPU MT6685_BBPU_ADDR -#define RTC_BBPU_PWREN (MT6685_PWREN_MASK << MT6685_PWREN_SHIFT) -#define RTC_BBPU_SPAR_SW (MT6685_SPAR_SW_MASK << MT6685_SPAR_SW_SHIFT) -#define RTC_BBPU_RESET_SPAR (MT6685_RESET_SPAR_MASK << MT6685_RESET_SPAR_SHIFT) -#define RTC_BBPU_RESET_ALARM (MT6685_RESET_ALARM_MASK << MT6685_RESET_ALARM_SHIFT) -#define RTC_BBPU_CLRPKY (MT6685_CLRPKY_MASK << MT6685_CLRPKY_SHIFT) -#define RTC_BBPU_RELOAD (MT6685_RELOAD_MASK << MT6685_RELOAD_SHIFT) -#define RTC_BBPU_CBUSY (MT6685_CBUSY_MASK << MT6685_CBUSY_SHIFT) -#define RTC_BBPU_ALARM_STATUS (MT6685_ALARM_STATUS_MASK << MT6685_ALARM_STATUS_SHIFT) -#define RTC_BBPU_KEY (0x43 << (MT6685_KEY_BBPU_SHIFT + 8)) - -#define RTC_IRQ_STA MT6685_ALSTA_ADDR -#define RTC_IRQ_STA_AL (MT6685_ALSTA_MASK << MT6685_ALSTA_SHIFT) -#define RTC_IRQ_STA_TC (MT6685_TCSTA_MASK << MT6685_TCSTA_SHIFT) -#define RTC_IRQ_STA_LP (MT6685_LPSTA_MASK << MT6685_LPSTA_SHIFT) - -#define RTC_IRQ_EN MT6685_AL_EN_ADDR -#define RTC_IRQ_EN_AL (MT6685_AL_EN_MASK << MT6685_AL_EN_SHIFT) -#define RTC_IRQ_EN_TC (MT6685_TC_EN_MASK << MT6685_TC_EN_SHIFT) -#define RTC_IRQ_EN_ONESHOT (MT6685_ONESHOT_MASK << MT6685_ONESHOT_SHIFT) -#define RTC_IRQ_EN_LP (MT6685_LP_EN_MASK << MT6685_LP_EN_SHIFT) -#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL) - -#define RTC_CII_EN MT6685_SECCII_ADDR -#define RTC_CII_SEC (MT6685_SECCII_MASK << MT6685_SECCII_SHIFT) -#define RTC_CII_MIN (MT6685_MINCII_MASK << MT6685_MINCII_SHIFT) -#define RTC_CII_HOU (MT6685_HOUCII_MASK << MT6685_HOUCII_SHIFT) -#define RTC_CII_DOM (MT6685_DOMCII_MASK << MT6685_DOMCII_SHIFT) -#define RTC_CII_DOW (MT6685_DOWCII_MASK << MT6685_DOWCII_SHIFT) -#define RTC_CII_MTH (MT6685_MTHCII_MASK << MT6685_MTHCII_SHIFT) -#define RTC_CII_YEA (MT6685_YEACII_MASK << MT6685_YEACII_SHIFT) -#define RTC_CII_1_2_SEC (MT6685_SECCII_1_2_MASK << MT6685_SECCII_1_2_SHIFT) -#define RTC_CII_1_4_SEC (MT6685_SECCII_1_4_MASK << (MT6685_SECCII_1_4_SHIFT + 8)) -#define RTC_CII_1_8_SEC (MT6685_SECCII_1_8_MASK << (MT6685_SECCII_1_8_SHIFT + 8)) - -#define RTC_AL_MASK MT6685_SEC_MSK_ADDR -#define RTC_AL_MASK_SEC (MT6685_SEC_MSK_MASK << MT6685_SEC_MSK_SHIFT) -#define RTC_AL_MASK_MIN (MT6685_MIN_MSK_MASK << MT6685_MIN_MSK_SHIFT) -#define RTC_AL_MASK_HOU (MT6685_HOU_MSK_MASK << MT6685_HOU_MSK_SHIFT) -#define RTC_AL_MASK_DOM (MT6685_DOM_MSK_MASK << MT6685_DOM_MSK_SHIFT) -#define RTC_AL_MASK_DOW (MT6685_DOW_MSK_MASK << MT6685_DOW_MSK_SHIFT) -#define RTC_AL_MASK_MTH (MT6685_MTH_MSK_MASK << MT6685_MTH_MSK_SHIFT) -#define RTC_AL_MASK_YEA (MT6685_YEA_MSK_MASK << MT6685_YEA_MSK_SHIFT) - -#define RTC_TC_SEC MT6685_TC_SECOND_ADDR -#define RTC_TC_SEC_MASK MT6685_TC_SECOND_MASK -#define RTC_TC_MIN MT6685_TC_MINUTE_ADDR -#define RTC_TC_MIN_MASK MT6685_TC_MINUTE_MASK -#define RTC_TC_HOU MT6685_TC_HOUR_ADDR -#define RTC_TC_HOU_MASK MT6685_TC_HOUR_MASK -#define RTC_TC_DOM MT6685_TC_DOM_ADDR -#define RTC_TC_DOM_MASK MT6685_TC_DOM_MASK -#define RTC_TC_DOW MT6685_TC_DOW_ADDR -#define RTC_TC_DOW_MASK MT6685_TC_DOW_MASK -#define RTC_TC_MTH MT6685_TC_MONTH_ADDR -#define RTC_TC_MTH_MASK MT6685_TC_MONTH_MASK -#define RTC_TC_YEA MT6685_TC_YEAR_ADDR -#define RTC_TC_YEA_MASK MT6685_TC_YEAR_MASK -#define RTC_AL_SEC MT6685_AL_SECOND_ADDR -#define RTC_AL_SEC_MASK MT6685_AL_SECOND_MASK - -#define RTC_BBPU_AUTO_PDN_SEL (MT6685_BBPU_AUTO_PDN_SEL_MASK << MT6685_BBPU_AUTO_PDN_SEL_SHIFT) -#define RTC_BBPU_2SEC_CK_SEL (MT6685_BBPU_2SEC_CK_SEL_MASK << MT6685_BBPU_2SEC_CK_SEL_SHIFT) -#define RTC_BBPU_2SEC_EN (MT6685_BBPU_2SEC_EN_MASK << (MT6685_BBPU_2SEC_EN_SHIFT + 8)) -#define RTC_BBPU_2SEC_MODE (MT6685_BBPU_2SEC_MODE_MASK << (MT6685_BBPU_2SEC_MODE_SHIFT + 8)) -/* RTC masks include shift */ -#define RTC_BBPU_2SEC_MODE_MSK (MT6685_BBPU_2SEC_MODE_MASK << (MT6685_BBPU_2SEC_MODE_SHIFT + 8)) -#define RTC_BBPU_2SEC_MODE_SHIFT (MT6685_BBPU_2SEC_MODE_SHIFT + 8) -#define RTC_BBPU_2SEC_STAT_CLEAR (MT6685_BBPU_2SEC_STAT_CLEAR_MASK << (MT6685_BBPU_2SEC_STAT_CLEAR_SHIFT + 8)) -#define RTC_BBPU_2SEC_STAT_STA (MT6685_BBPU_2SEC_STAT_STA_MASK << (MT6685_BBPU_2SEC_STAT_STA_SHIFT + 8)) -#define RTC_LPD_OPT_SHIFT (MT6685_RTC_LPD_OPT_SHIFT + 8) -#define RTC_LPD_OPT_MASK (MT6685_RTC_LPD_OPT_MASK << (MT6685_RTC_LPD_OPT_SHIFT + 8)) -#define RTC_LPD_OPT_XOSC_AND_EOSC_LPD (0U << (MT6685_RTC_LPD_OPT_SHIFT + 8)) -#define RTC_LPD_OPT_EOSC_LPD (1U << (MT6685_RTC_LPD_OPT_SHIFT + 8)) -#define RTC_LPD_OPT_XOSC_LPD (2U << (MT6685_RTC_LPD_OPT_SHIFT + 8)) -#define RTC_LPD_OPT_F32K_CK_ALIVE (3U << (MT6685_RTC_LPD_OPT_SHIFT + 8)) -#define RTC_K_EOSC32_VTCXO_ON_SEL (MT6685_K_EOSC32_VTCXO_ON_SEL_MASK << (MT6685_K_EOSC32_VTCXO_ON_SEL_SHIFT + 8)) - -#define RTC_AL_MIN MT6685_AL_MINUTE_ADDR -#define RTC_AL_MIN_MASK (MT6685_AL_MINUTE_MASK << MT6685_AL_MINUTE_SHIFT) - -/* - * RTC_NEW_SPARE0: RTC_AL_HOU bit0~4 - * bit 8 ~ 15 : For design used, can't be overwritten. - */ -#define RTC_AL_HOU MT6685_AL_HOUR_ADDR -#define RTC_AL_HOU_MASK (MT6685_AL_HOUR_MASK << MT6685_AL_HOUR_SHIFT) -#define RTC_NEW_SPARE0 (MT6685_NEW_SPARE0_MASK << (MT6685_NEW_SPARE0_SHIFT + 8)) -#define RTC_AL_HOU_FG_SHIFT 8 -#define RTC_AL_HOU_FG_MASK 0xff00 - -/* - * RTC_NEW_SPARE1: RTC_AL_DOM bit0~4 - * bit 8 ~ 15 : for 2 second reboot desing used, - * can't be overwritten. - */ -#define RTC_AL_DOM MT6685_AL_DOM_ADDR -#define RTC_AL_DOM_MASK (MT6685_AL_DOM_MASK << MT6685_AL_DOM_SHIFT) -#define RTC_NEW_SPARE1 (MT6685_NEW_SPARE1_MASK << (MT6685_NEW_SPARE1_SHIFT + 8)) -#define RTC_SPAR_CONDITION BIT(8) /* by uvlo */ -#define RTC_AUTOMATICALLY_SPAR BIT(9) /* clear by sw */ -#define RTC_ALARM_CLEAR_METHOD BIT(11) /* by sw */ - -/* - * RTC_NEW_SPARE2: RTC_AL_DOW bit0~2 - * bit 8 ~ 15 : reserved bits - */ -#define RTC_AL_DOW MT6685_AL_DOW_ADDR -#define RTC_AL_DOW_MASK (MT6685_AL_DOW_MASK << MT6685_AL_DOW_SHIFT) -#define RTC_RG_EOSC_CALI_TD_1SEC (3 << (MT6685_NEW_SPARE2_SHIFT + 8)) -#define RTC_RG_EOSC_CALI_TD_2SEC (4 << (MT6685_NEW_SPARE2_SHIFT + 8)) -#define RTC_RG_EOSC_CALI_TD_4SEC (5 << (MT6685_NEW_SPARE2_SHIFT + 8)) -#define RTC_RG_EOSC_CALI_TD_8SEC (6 << (MT6685_NEW_SPARE2_SHIFT + 8)) -#define RTC_RG_EOSC_CALI_TD_16SEC (7 << (MT6685_NEW_SPARE2_SHIFT + 8)) -#define RTC_RG_EOSC_CALI_TD_MASK (0x7 << (MT6685_NEW_SPARE2_SHIFT + 8)) -#define RTC_NEW_SPARE2 (MT6685_NEW_SPARE2_MASK << (MT6685_NEW_SPARE2_SHIFT + 8)) - -/* - * RTC_NEW_SPARE3: RTC_AL_MTH bit0~3 - * bit 8 ~ 15 : Fuel Gauge - */ -#define RTC_AL_MTH MT6685_AL_MONTH_ADDR -#define RTC_AL_MTH_MASK (MT6685_AL_MONTH_MASK << MT6685_AL_MONTH_SHIFT) -#define RTC_NEW_SPARE3 (MT6685_NEW_SPARE3_MASK << (MT6685_NEW_SPARE3_SHIFT + 8)) -#define RTC_AL_MTH_FG_SHIFT 8 -#define RTC_AL_MTH_FG_MASK 0xff00 - -#define RTC_AL_YEA MT6685_AL_YEAR_ADDR -#define RTC_AL_YEA_MASK (MT6685_AL_YEAR_MASK << MT6685_AL_YEAR_SHIFT) -#define RTC_K_EOSC_RSV_0 BIT(8) -#define RTC_K_EOSC_RSV_1 BIT(9) -#define RTC_K_EOSC_RSV_2 BIT(10) -#define RTC_K_EOSC_RSV_3 BIT(11) -#define RTC_K_EOSC_RSV_4 BIT(12) -#define RTC_K_EOSC_RSV_5 BIT(13) -#define RTC_K_EOSC_RSV_6 BIT(14) -#define RTC_K_EOSC_RSV_7 BIT(15) - -#define RTC_OSC32CON MT6685_XOSCCALI_ADDR -#define RTC_OSC32CON_UNLOCK1 0x1a57 -#define RTC_OSC32CON_UNLOCK2 0x2b68 - -/* Default 4'b0111, 2nd step suggest to set to 4'b0000 EOSC_CALI = charging cap calibration */ -#define RTC_XOSCCALI_MASK (MT6685_XOSCCALI_MASK << MT6685_XOSCCALI_SHIFT) - -/* 0 (32k crystal exist) 1 (32k crystal doesn't exist)*/ -#define RTC_XOSC32_ENB (MT6685_RTC_XOSC32_ENB_MASK << MT6685_RTC_XOSC32_ENB_SHIFT) -#define RTC_EMBCK_SEL_MODE (MT6685_RTC_EMBCK_SEL_MODE_MASK << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) -#define RTC_EMBCK_SRC_SEL (MT6685_RTC_EMBCK_SRC_SEL_MASK << (MT6685_RTC_EMBCK_SRC_SEL_SHIFT + 8)) -#define RTC_EMBCK_SEL_OPTION (MT6685_RTC_EMBCK_SEL_OPTION_MASK << (MT6685_RTC_EMBCK_SEL_OPTION_SHIFT + 8)) -#define RTC_GPS_CKOUT_EN (MT6685_RTC_GPS_CKOUT_EN_MASK << (MT6685_RTC_GPS_CKOUT_EN_SHIFT + 8)) -#define RTC_EOSC32_VCT_EN (MT6685_RTC_EOSC32_VCT_EN_MASK << (MT6685_RTC_EOSC32_VCT_EN_SHIFT + 8)) -#define RTC_EOSC32_CHOP_EN (MT6685_RTC_EOSC32_CHOP_EN_MASK << (MT6685_RTC_EOSC32_CHOP_EN_SHIFT + 8)) - -/* Keep RG_EOSC_RSV[0] to low for lower EOSC leakage current hardware design change. */ -#define RTC_GP_OSC32_CON (2U << (MT6685_RTC_GP_OSC32_CON_SHIFT + 8)) -#define RTC_REG_XOSC32_ENB (MT6685_RTC_REG_XOSC32_ENB_MASK << (MT6685_RTC_REG_XOSC32_ENB_SHIFT + 8)) - -/* 0: emb_hw 1: emb_k_eosc_32 2:dcxo_ck 3: eosc32_ck*/ -#define RTC_EMBCK_SEL_HW (0 << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) -#define RTC_EMBCK_SEL_K_EOSC (1U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) -#define RTC_EMBCK_SEL_DCXO (2U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) -#define RTC_EMBCK_SEL_EOSC (3U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) - -#define OSC32CON_ANALOG_SETTING (RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | \ - RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | \ - RTC_EMBCK_SEL_OPTION | RTC_EMBCK_SEL_K_EOSC) - -#define RTC_XOSCCALI_START 0x0000 -#define RTC_XOSCCALI_END 0x001f - -#define RTC_POWERKEY1 MT6685_RTC_POWERKEY1_L_ADDR -#define RTC_POWERKEY2 MT6685_RTC_POWERKEY2_L_ADDR -#define RTC_POWERKEY1_KEY 0xa357 -#define RTC_POWERKEY2_KEY 0x67d2 - -#define RTC_PDN1 MT6685_RTC_PDN1_L_ADDR -#define RTC_PDN1_RECOVERY_MASK 0x0030 -#define RTC_PDN1_FAC_RESET BIT(4) -#define RTC_PDN1_BYPASS_PWR BIT(6) -#define RTC_PDN1_PWRON_TIME BIT(7) -#define RTC_PDN1_FAST_BOOT BIT(13) -#define RTC_PDN1_KPOC BIT(14) -#define RTC_PDN1_DEBUG BIT(15) - -#define RTC_PDN2 MT6685_RTC_PDN2_L_ADDR -#define RTC_PDN2_PWRON_MTH_MASK 0x000f -#define RTC_PDN2_PWRON_MTH_SHIFT 0 -#define RTC_PDN2_PWRON_ALARM BIT(4) -#define RTC_PDN2_PWRON_YEA_MASK 0x7f00 -#define RTC_PDN2_AUTOBOOT BIT(7) -#define RTC_PDN2_PWRON_YEA_SHIFT 8 -#define RTC_PDN2_PWRON_LOGO BIT(15) - -#define RTC_SPAR0 MT6685_RTC_SPAR0_L_ADDR -#define RTC_SPAR0_PWRON_SEC_MASK 0x003f -#define RTC_SPAR0_PWRON_SEC_SHIFT 0 -#define RTC_SPAR0_32K_LESS BIT(6) - -#define RTC_SPAR1 MT6685_RTC_SPAR1_L_ADDR -#define RTC_SPAR1_PWRON_MIN_MASK 0x003f -#define RTC_SPAR1_PWRON_MIN_SHIFT 0 -#define RTC_SPAR1_PWRON_HOU_MASK 0x07c0 -#define RTC_SPAR1_PWRON_HOU_SHIFT 6 -#define RTC_SPAR1_PWRON_DOM_MASK 0xf800 -#define RTC_SPAR1_PWRON_DOM_SHIFT 11 - -#define RTC_PROT MT6685_RTC_PROT_L_ADDR -#define RTC_PROT_UNLOCK1 0x586a -#define RTC_PROT_UNLOCK2 0x9136 -#define RTC_PROT_UNLOCK_SUCCESS 0x3 - -#define RTC_DIFF MT6685_RTC_DIFF_L_ADDR -#define RTC_POWER_DETECTED (MT6685_POWER_DETECTED_MASK << (MT6685_POWER_DETECTED_SHIFT + 8)) -#define RTC_K_EOSC32_RSV (MT6685_K_EOSC32_RSV_MASK << (MT6685_K_EOSC32_RSV_SHIFT + 8)) -#define RTC_CALI_RD_SEL_SHIFT (MT6685_CALI_RD_SEL_SHIFT + 8) -#define RTC_CALI_RD_SEL (MT6685_CALI_RD_SEL_MASK << (MT6685_CALI_RD_SEL_SHIFT + 8)) - -#define RTC_CALI MT6685_RTC_CALI_L_ADDR -#define RTC_CALI_MASK (MT6685_RTC_CALI_H_MASK << (MT6685_RTC_CALI_H_SHIFT + 8) | \ - MT6685_RTC_CALI_L_MASK << MT6685_RTC_CALI_L_SHIFT) - -#define RTC_CALI_WR_SEL (MT6685_CALI_WR_SEL_MASK << (MT6685_CALI_WR_SEL_SHIFT + 8)) -#define RTC_CALI_WR_SEL_SHIFT (MT6685_CALI_WR_SEL_SHIFT + 8) -#define RTC_K_EOSC32_OVERFLOW (MT6685_K_EOSC32_OVERFLOW_MASK << (MT6685_K_EOSC32_OVERFLOW_SHIFT + 8)) - -#define RTC_WRTGR MT6685_WRTGR_ADDR - -#define RTC_CON MT6685_VBAT_LPSTA_RAW_ADDR -#define RTC_VBAT_LPSTA_RAW (MT6685_VBAT_LPSTA_RAW_MASK << MT6685_VBAT_LPSTA_RAW_SHIFT) -#define RTC_EOSC32_LPEN (MT6685_EOSC32_LPEN_MASK << MT6685_EOSC32_LPEN_SHIFT) -#define RTC_XOSC32_LPEN (MT6685_XOSC32_LPEN_MASK << MT6685_XOSC32_LPEN_SHIFT) -#define RTC_CON_LPRST (MT6685_LPRST_MASK << MT6685_LPRST_SHIFT) -#define RTC_CON_CDBO (MT6685_CDBO_MASK << MT6685_CDBO_SHIFT) -/* 0: RTC_GPIO exports 32K */ -#define RTC_CON_F32KOB (MT6685_F32KOB_MASK << MT6685_F32KOB_SHIFT) -#define RTC_CON_GPO (MT6685_GPO_MASK << MT6685_GPO_SHIFT) -/* 1: GPO mode, 0: GPI mode */ -#define RTC_CON_GOE (MT6685_GOE_MASK << MT6685_GOE_SHIFT) -#define RTC_CON_GSR (MT6685_GSR_MASK << (MT6685_GSR_SHIFT + 8)) -#define RTC_CON_GSMT (MT6685_GSMT_MASK << (MT6685_GSMT_SHIFT + 8)) -#define RTC_CON_GPEN (MT6685_GPEN_MASK << (MT6685_GPEN_SHIFT + 8)) -#define RTC_CON_GPU (MT6685_GPU_MASK << (MT6685_GPU_SHIFT + 8)) -#define RTC_CON_GE4 (MT6685_GE4_MASK << (MT6685_GE4_SHIFT + 8)) -#define RTC_CON_GE8 (MT6685_GE8_MASK << (MT6685_GE8_SHIFT + 8)) -#define RTC_CON_GPI (MT6685_GPI_MASK << (MT6685_GPI_SHIFT + 8)) -/* 32K was stopped */ -#define RTC_CON_LPSTA_RAW (MT6685_LPSTA_RAW_MASK << (MT6685_LPSTA_RAW_SHIFT + 8)) - -#define RTC_INT_CNT MT6685_RTC_INT_CNT_L_ADDR - -#define SCK_TOP_CKPDN_CON0_L_SET MT6685_SCK_TOP_CKPDN_CON0_L_SET_ADDR -#define RG_RTC_EOSC32_CK_PDN_MASK MT6685_RG_RTC_EOSC32_CK_PDN_MASK -#define RG_RTC_EOSC32_CK_PDN_SHIFT MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT - -#define SCK_TOP_CKPDN_CON0_L_CLR MT6685_SCK_TOP_CKPDN_CON0_L_CLR_ADDR -#define SCK_TOP_CKPDN_CON0_L_CLR_SHIFT MT6685_SCK_TOP_CKPDN_CON0_L_CLR_SHIFT - -#define SCK_TOP_CKPDN_CON0_L MT6685_SCK_TOP_CKPDN_CON0_L -#define RG_RTC_SEC_MCLK_PDN_MASK MT6685_RG_RTC_SEC_MCLK_PDN_MASK -#define RG_RTC_SEC_32K_CK_PDN_MASK MT6685_RG_RTC_SEC_32K_CK_PDN_MASK -#define RG_RTC_SEC_32K_CK_PDN_SHIFT MT6685_RG_RTC_SEC_32K_CK_PDN_SHIFT - -#define SCK_TOP_XTAL_SEL_ADDR MT6685_SCK_TOP_XTAL_SEL_ADDR -#define SCK_TOP_XTAL_SEL_MASK MT6685_SCK_TOP_XTAL_SEL_MASK -#define SCK_TOP_XTAL_SEL_SHIFT MT6685_SCK_TOP_XTAL_SEL_SHIFT - -#define TOP_RST_MISC_CLR MT6685_TOP_RST_MISC_CLR_ADDR -#define TOP_RST_MISC_CLR_MASK MT6685_TOP_RST_MISC_CLR_MASK -#define TOP_RST_MISC_CLR_SHIFT MT6685_TOP_RST_MISC_CLR_SHIFT - -#define TMA_KEY MT6685_TMA_KEY_ADDR -#define TMA_KEY_MASK MT6685_TMA_KEY_MASK -#define TMA_KEY_SHIFT MT6685_TMA_KEY_SHIFT - -#define TMA_KEY_H MT6685_TMA_KEY_H_ADDR -#define TMA_KEY_H_MASK MT6685_TMA_KEY_H_MASK -#define TMA_KEY_H_SHIFT MT6685_TMA_KEY_H_SHIFT - -#define TOP_DIG_WPK MT6685_TOP_DIG_WPK -#define DIG_WPK_KEY_MASK MT6685_DIG_WPK_KEY_MASK -#define DIG_WPK_KEY_SHIFT MT6685_DIG_WPK_KEY_SHIFT - -#define TOP_DIG_WPK_H MT6685_TOP_DIG_WPK_H -#define DIG_WPK_KEY_H_MASK MT6685_DIG_WPK_KEY_H_MASK -#define DIG_WPK_KEY_H_SHIFT MT6685_DIG_WPK_KEY_H_SHIFT - -#define RG_RTC_MCLK_PDN_SET MT6685_SCK_TOP_CKPDN_CON0_L_SET -#define RG_RTC_MCLK_PDN_CLR MT6685_SCK_TOP_CKPDN_CON0_L_CLR -#define RG_RTC_MCLK_PDN_MASK MT6685_RG_RTC_MCLK_PDN_MASK -#define RG_RTC_MCLK_PDN_SHIFT MT6685_RG_RTC_MCLK_PDN_SHIFT - -#define RG_SHUTDOWN_SRC_SEL MT6685_RG_SHUTDOWN_SRC_SEL_ADDR -#define RG_SHUTDOWN_SRC_SEL_MASK MT6685_RG_SHUTDOWN_SRC_SEL_MASK -#define RG_SHUTDOWN_SRC_SEL_SHIFT MT6685_RG_SHUTDOWN_SRC_SEL_SHIFT - -#define RG_SRCLKEN_IN0_HW_MODE MT6685_TOP_CON -#define RG_SRCLKEN_IN0_HW_MODE_MASK MT6685_RG_SRCLKEN_IN0_HW_MODE_MASK -#define RG_SRCLKEN_IN0_HW_MODE_SHIFT MT6685_RG_SRCLKEN_IN0_HW_MODE_SHIFT - -#define RG_SRCLKEN_IN1_HW_MODE MT6685_TOP_CON -#define RG_SRCLKEN_IN1_HW_MODE_MASK MT6685_RG_SRCLKEN_IN1_HW_MODE_MASK -#define RG_SRCLKEN_IN1_HW_MODE_SHIFT MT6685_RG_SRCLKEN_IN1_HW_MODE_SHIFT - -#define RG_RTC_EOSC32_CK_PDN MT6685_SCK_TOP_CKPDN_CON0_L -#define RG_RTC_EOSC32_CK_PDN_MASK MT6685_RG_RTC_EOSC32_CK_PDN_MASK -#define RG_RTC_EOSC32_CK_PDN_SHIFT MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT - -#define XO_EN32K_MAN_ADDR MT6685_DCXO_DIG_MODE_CW0 -#define XO_EN32K_MAN_MASK MT6685_XO_EN32K_MAN_MASK -#define XO_EN32K_MAN_SHIFT MT6685_XO_EN32K_MAN_SHIFT - -#define SCK_TOP_CKSEL_CON MT6685_SCK_TOP_CKSEL_CON -#define R_SCK32K_CK_MASK 0x1 -#define R_SCK32K_CK_SHIFT 0 - -#define RTC_SPAR_MACRO MT6685_RTC_SPAR_MACRO -#define SPAR_THRE_SEL (MT6685_RTC_SPAR_THRE_SEL_MASK << MT6685_RTC_SPAR_THRE_SEL_SHIFT) -#define SPAR_UVLO_WAIT_SHIFT MT6685_RTC_UVLO_WAIT_SHIFT -#define SPAR_UVLO_WAIT_1T 0x0 -#define SPAR_UVLO_WAIT_4ms 0x1 -#define SPAR_UVLO_WAIT_16ms 0x2 -#define SPAR_UVLO_WAIT_32ms 0x3 -#define RTC_SPAR_PWRKEY_MATCH_LPD_MASK 0x1 -#define RTC_SPAR_PWRKEY_MATCH_LPD_SHIFT 4 -#define RTC_SPAR_PWRKEY_MATCH_MASK 0x1 -#define RTC_SPAR_PWRKEY_MATCH_SHIFT 5 -#define RTC_SPAR_PROT_STAT_MASK 0x3 -#define RTC_SPAR_PROT_STAT_SHIFT 6 - -/* Secure RTC */ -#define RTC_TC_SEC_SEC MT6685_TC_SECOND_SEC_ADDR -#define RTC_TC_MIN_SEC MT6685_TC_MINUTE_SEC_ADDR -#define RTC_TC_HOU_SEC MT6685_TC_HOUR_SEC_ADDR -#define RTC_TC_DOM_SEC MT6685_TC_DOM_SEC_ADDR -#define RTC_TC_DOW_SEC MT6685_TC_DOW_SEC_ADDR -#define RTC_TC_MTH_SEC MT6685_TC_MONTH_SEC_ADDR -#define RTC_TC_YEA_SEC MT6685_TC_YEAR_SEC_ADDR - -#define RTC_WRTGR_SEC MT6685_RTC_SEC_WRTGR_ADDR -#define RTC_SEC_CK_PDN MT6685_RTC_SEC_CK_PDN_ADDR - -#define RTC_SEC_DSN_REV0 MT6685_RTC_SEC_ANA_REV -#define RTC_SEC_DSN_ID MT6685_RTC_SEC_ANA_ID - -#define RTC_SEC_BAS RTC_SEC_DSN_ID - -#endif /* SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H */ diff --git a/src/soc/mediatek/mt8196/include/soc/rtc.h b/src/soc/mediatek/mt8196/include/soc/rtc.h index e48c13e..ba90669 100644 --- a/src/soc/mediatek/mt8196/include/soc/rtc.h +++ b/src/soc/mediatek/mt8196/include/soc/rtc.h @@ -8,6 +8,7 @@ #ifndef SOC_MEDIATEK_MT8196_RTC_H #define SOC_MEDIATEK_MT8196_RTC_H +#include <soc/mt6685_rtc.h> #include <soc/rtc_common.h> #include <soc/rtc_reg_common.h> #include <stdbool.h> diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c index 4564a31..9300693 100644 --- a/src/soc/mediatek/mt8196/mt6685_rtc.c +++ b/src/soc/mediatek/mt8196/mt6685_rtc.c @@ -7,9 +7,9 @@ #include <commonlib/bsd/bcd.h> #include <console/console.h> #include <delay.h> +#include <rtc.h> #include <soc/mt6685.h> -#include <soc/mt6685_rtc.h> -#include <soc/mt6685_rtc_hw.h> +#include <soc/rtc.h> #include <stdbool.h> #include <timer.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/86264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69ee165df6a1c9ea5853173f46f0aafc382153c1 Gerrit-Change-Number: 86264 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

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coreboot-gerrit February 2025