coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[M] Change in coreboot[main]: soc/amd/common: Support sbin ucode files
by Fred Reitberger (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Felix Held, Jason Glenesk, Martin Roth, Matt DeVillier, Maximilian Brune, Patrick Rudolph, Raul Rangel. Fred Reitberger has posted comments on this change by Fred Reitberger. ( https://review.coreboot.org/c/coreboot/+/68122?usp=email ) Change subject: soc/amd/common: Support sbin ucode files ...................................................................... Patch Set 9: (2 comments) File src/soc/amd/common/block/cpu/Makefile.mk: https://review.coreboot.org/c/coreboot/+/68122/comment/f95984f0_9c5860b2?us… : PS9, Line 15: # check for duplicate microcode files. Same sbin and bin ucode is allowed here though, because mendocino has a duplicate. I just checked this out and it looks like both the Mendocino .bin and .sbin in amd_blobs have the same data. https://review.coreboot.org/c/coreboot/+/68122/comment/9805ecef_58d5a29a?us… : PS9, Line 32: # if there is both a sbin and bin microcode only include the bin one to keep the old behaviour When I last worked on this, the releases would be in '.sbin' format and we had to manually make the '.bin' variations. That was the reason for this patch in the first place. If a new release updates the ucode and only provides a .sbin file, will this select the wrong file? -- To view, visit https://review.coreboot.org/c/coreboot/+/68122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae Gerrit-Change-Number: 68122 Gerrit-PatchSet: 9 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 03 Feb 2025 23:04:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: mb/amd/birman_plus: Update phoenix port descriptors
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Matt DeVillier has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/86232?usp=email ) Change subject: mb/amd/birman_plus: Update phoenix port descriptors ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > It was merged out of queue. Just merged CB:85493 which should fix the issue. Thanks, I looked and must have missed the dependency -- To view, visit https://review.coreboot.org/c/coreboot/+/86232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54d35060c34043f9d97658ab84b9b1bb2e62ba60 Gerrit-Change-Number: 86232 Gerrit-PatchSet: 2 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Mon, 03 Feb 2025 22:13:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

1 0

[M] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Vikrant L Jadeja. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Mon, 03 Feb 2025 21:58:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: tree: Use boolean for PchHdaDspEnable
by Elyes Haouas (Code Review) 03 Feb '25

03 Feb '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86190?usp=email ) Change subject: tree: Use boolean for PchHdaDspEnable ...................................................................... tree: Use boolean for PchHdaDspEnable Change-Id: I47852c9b023cc4839000019b8a932b6e471fa839 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86190 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/tigerlake/chip.h 19 files changed, 19 insertions(+), 19 deletions(-) Approvals: Maxim Polyakov: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2b55e7c..879f4d0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -129,7 +129,7 @@ register "PcieClkSrcClkReq[5]" = "5" # Audio related configurations - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkHdaEnable" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" register "PchHdaAudioLinkSspEnable[1]" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 6b3eff6..da1c45f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -177,7 +177,7 @@ register "PcieClkSrcClkReq[3]" = "3" #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override) - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index de4631a..c5b0121 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -177,7 +177,7 @@ register "PcieClkSrcClkReq[3]" = "3" #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override) - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8110bb7..9c7b592 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -506,7 +506,7 @@ end end device ref hda on - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" chip drivers/sof register "spkr_tplg" = "max98373" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 012afc4..16c68cd 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -22,7 +22,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkHda" = "1" register "PcieClkSrcUsage[0]" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 049859a..031974f 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -39,7 +39,7 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1" - register "PchHdaDspEnable" = "0" + register "PchHdaDspEnable" = "false" register "PchHdaAudioLinkHda" = "1" register "PcieRpEnable[0]" = "true" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index 266c698..3f1820e 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -37,7 +37,7 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1" - register "PchHdaDspEnable" = "0" + register "PchHdaDspEnable" = "false" register "PchHdaAudioLinkHda" = "1" register "PcieRpEnable[0]" = "true" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index 0133a11..84ebda5 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkHda" = "1" register "PcieRpEnable[0]" = "true" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 157a465..846fea9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -38,7 +38,7 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1" - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkHda" = "1" register "PcieRpEnable[0]" = "true" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 8df9851..89e59a4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -23,7 +23,7 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1" - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkHda" = "1" register "PcieRpEnable[0]" = "true" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 56c7bd6..b4a9261 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -56,7 +56,7 @@ # Skip the CPU replacement check register "SkipCpuReplacementCheck" = "1" - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkSspEnable[0]" = "1" register "PchHdaAudioLinkSspEnable[1]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b9af2c5..032e80e 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -322,7 +322,7 @@ end end device ref hda on - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkDmicEnable" = "{ [0] = 1, [1] = 1, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7e00917..720e40f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -325,7 +325,7 @@ end end device ref hda on - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkDmicEnable" = "{ [0] = 1, [1] = 1, diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index cb5f211..e9bd24a 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -23,7 +23,7 @@ register "SataPortsHotPlug[6]" = "1" register "SataPortsHotPlug[7]" = "1" - register "PchHdaDspEnable" = "0" + register "PchHdaDspEnable" = "false" register "PchHdaAudioLinkHda" = "1" register "PcieClkSrcUsage[0]" = "20" # PCIe Slot1 diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index c00404d..82cac12 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -39,7 +39,7 @@ register "SerialIoUartMode[2]" = "PchSerialIoSkipInit" # Audio related configurations - register "PchHdaDspEnable" = "1" + register "PchHdaDspEnable" = "true" register "PchHdaAudioLinkHdaEnable" = "1" device domain 0 on diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 851a8bf..f217461 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -4,7 +4,7 @@ # FSP configuration register "RMT" = "0" - register "PchHdaDspEnable" = "0" + register "PchHdaDspEnable" = "false" register "PchHdaAudioLinkHda" = "1" device domain 0 on diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index c5121f9a..38358d8 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -4,7 +4,7 @@ # FSP configuration register "RMT" = "0" - register "PchHdaDspEnable" = "0" + register "PchHdaDspEnable" = "false" register "PchHdaAudioLinkHda" = "1" device domain 0 on diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 397372d..d4bb04f 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -203,7 +203,7 @@ uint16_t SataPortsDitoVal[CONFIG_MAX_SATA_PORTS]; /* Audio related */ - uint8_t PchHdaDspEnable; + bool PchHdaDspEnable; uint8_t PchHdaAudioLinkHdaEnable; uint8_t PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS]; uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 41c7dd3c..2c0a9b4 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -249,7 +249,7 @@ uint16_t SataPortsDitoVal[8]; /* Audio related */ - uint8_t PchHdaDspEnable; + bool PchHdaDspEnable; uint8_t PchHdaAudioLinkHdaEnable; uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; -- To view, visit https://review.coreboot.org/c/coreboot/+/86190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47852c9b023cc4839000019b8a932b6e471fa839 Gerrit-Change-Number: 86190 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: tree: Use true, false for DspEnable
by Elyes Haouas (Code Review) 03 Feb '25

03 Feb '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86189?usp=email ) Change subject: tree: Use true, false for DspEnable ...................................................................... tree: Use true, false for DspEnable DspEnable is a boolean, so use true false instead of 0 1. Change-Id: I5bab9db3632848f92732160bb821dda8cdb14281 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86189 Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 20 files changed, 20 insertions(+), 20 deletions(-) Approvals: Sean Rhodes: Looks good to me, but someone else must approve build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index d0084e7..a5bb944c 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -30,7 +30,7 @@ register "dptf_enable" = "false" # FSP Configuration - register "DspEnable" = "0" + register "DspEnable" = "false" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index e3abec8..60136ed 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -315,7 +315,7 @@ register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" # 17:16 in pmbase+0018h end device ref hda on - register "DspEnable" = "1" + register "DspEnable" = "true" # PchHdaDspEndpointDmic is only to be returned to reference code # DXE phase as HOB, used to select blob for NHLT end diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 0189e62..5ff4392 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -30,7 +30,7 @@ register "gpe0_dw2" = "GPP_E" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 145b093..d2bb08e 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -59,7 +59,7 @@ register "s0ix_enable" = true # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 1de2833..bac1ed3 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -31,7 +31,7 @@ register "dptf_enable" = "true" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 159acb3..d1a3542 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -37,7 +37,7 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 8fa6a14..160dfd3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -25,7 +25,7 @@ register "s0ix_enable" = true # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 3a5806b..e32e5e4 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = true # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index c0c9861..dfb11ee 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = true # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 39b4e74..e64d408 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -30,7 +30,7 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 5cc1be7..3251916 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -37,7 +37,7 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index de3b2ab..7602bcb 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = true # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index cd17307..5da43c2 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake # FSP Configuration - register "DspEnable" = "0" + register "DspEnable" = "false" register "ScsEmmcHs400Enabled" = "0" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 7dae329..1880cd9 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -4,7 +4,7 @@ register "gpe0_dw0" = "GPP_C" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 08eb965..758b913 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -17,7 +17,7 @@ register "dptf_enable" = "true" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 2aae0d0..fd2ae41 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -15,7 +15,7 @@ register "gpe0_dw2" = "GPP_E" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "3" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 771ea06..29d82de 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -27,7 +27,7 @@ register "dptf_enable" = "false" # FSP Configuration - register "DspEnable" = "1" + register "DspEnable" = "true" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index af7fd5b..30152b5 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -20,7 +20,7 @@ register "tcc_offset" = "5" # TCC of 95C # FSP Configuration - register "DspEnable" = "0" + register "DspEnable" = "false" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 0b912c6..9af8046 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -38,7 +38,7 @@ register "dptf_enable" = "false" # FSP Configuration - register "DspEnable" = "0" + register "DspEnable" = "false" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 05c619a..637427a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -19,7 +19,7 @@ register "dptf_enable" = "false" # FSP Configuration - register "DspEnable" = "0" + register "DspEnable" = "false" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" -- To view, visit https://review.coreboot.org/c/coreboot/+/86189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5bab9db3632848f92732160bb821dda8cdb14281 Gerrit-Change-Number: 86189 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XL] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers to 3015.00
by Jérémy Compostella (Code Review) 03 Feb '25

03 Feb '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86258?usp=email ) Change subject: vc/intel/fsp: Update PTL FSP headers to 3015.00 ...................................................................... vc/intel/fsp: Update PTL FSP headers to 3015.00 This update revises the Panther Lake Firmware Support Package (FSP) headers to incorporate the latest enhancements for Panther Lake FSP version 3015.00. Modifications are made to the FspmUpd.h and FspsUpd.h header files to integrate these advancements. The update introduces the following significant alterations: - Introduction of settings to manage the Intel Total Memory Encryption (TME) feature. - A feature designed to reduce acoustic noise emissions for specific product models when the CPU operates in an advanced C power-saving state. - Implementation of PSYS PMax power adjustments. - Adjustments to the AcLoadline and DcLoadline parameters. - The inclusion of FastPkgCRampDisable, which controls the Fast Slew Rate for Voltage Regulator (VR) domains when in Deep Package C States, aiding in the reduction of acoustic noise during these states. - A new limit setting for the Voltage Regulator Fast Voltage Mode (Vmode) inrush current (ICC). - A toggle for the activation or deactivation of Current Excursion Protection (CEP). - VgaInitControl, a directive to initialize the VGA based sign-of-life. TEST: google/fatcat build can be successfully compiled. Change-Id: I1b43faa704959dce5846e22e57f81e651be2d56c Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h 2 files changed, 1,476 insertions(+), 1,318 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/86258/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h index 354f7ba..82a790e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2024, Intel Corporation. All rights reserved. +Copyright (c) 2025, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -230,659 +230,191 @@ **/ UINT16 RcompTarget[5]; -/** Offset 0x011C - LowerBasicMemTestSize feature +/** Offset 0x011C - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch0[2]; + +/** Offset 0x011E - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch1[2]; + +/** Offset 0x0120 - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch2[2]; + +/** Offset 0x0122 - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch3[2]; + +/** Offset 0x0124 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch0[2]; + +/** Offset 0x0126 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch1[2]; + +/** Offset 0x0128 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch2[2]; + +/** Offset 0x012A - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch3[2]; + +/** Offset 0x012C - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch0[16]; + +/** Offset 0x013C - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch1[16]; + +/** Offset 0x014C - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch2[16]; + +/** Offset 0x015C - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch3[16]; + +/** Offset 0x016C - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch0[16]; + +/** Offset 0x017C - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch1[16]; + +/** Offset 0x018C - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch2[16]; + +/** Offset 0x019C - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch3[16]; + +/** Offset 0x01AC - LowerBasicMemTestSize Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, shorter BasicMemTest (faster boot) $EN_DIS **/ UINT8 LowerBasicMemTestSize; -/** Offset 0x011D - Reserved +/** Offset 0x01AD - Reserved **/ UINT8 Reserved5[2]; -/** Offset 0x011F - CaVrefHigh feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS +/** Offset 0x01AF - CaVrefHigh + DDR5 CA Sweep High Vref Value for DDR5 OC **/ UINT8 CaVrefHigh; -/** Offset 0x0120 - CsVrefLow feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT8 CsVrefLow; - -/** Offset 0x0121 - CsVrefHigh feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT8 CsVrefHigh; - -/** Offset 0x0122 - CaVrefLow feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS +/** Offset 0x01B0 - CaVrefLow + DDR5 CA Sweep Low Vref Value for DDR5 OC **/ UINT8 CaVrefLow; -/** Offset 0x0123 - DFETap2StepSize feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS +/** Offset 0x01B1 - CsVrefHigh + DDR5 CS Sweep High Vref Value for DDR5 OC **/ - UINT8 DFETap2StepSize; + UINT8 CsVrefHigh; -/** Offset 0x0124 - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS +/** Offset 0x01B2 - CsVrefLow + DDR5 CS Sweep Low Vref Value for DDR5 OC **/ - UINT16 Vdd2Mv; + UINT8 CsVrefLow; -/** Offset 0x0126 - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT16 tWTR_S; - -/** Offset 0x0128 - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT16 tCCD_L; - -/** Offset 0x012A - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT16 tWTR_L; - -/** Offset 0x012C - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT16 tRRD_S; - -/** Offset 0x012E - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT16 tRRD_L; - -/** Offset 0x0130 - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT16 tRFC4; - -/** Offset 0x0132 - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT16 tRFC2; - -/** Offset 0x0134 - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT16 tRFCpb; - -/** Offset 0x0136 - Reserved -**/ - UINT8 Reserved6[7]; - -/** Offset 0x013D - Vdd2Mv feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS -**/ - UINT8 LpMode; - -/** Offset 0x013E - LowerBasicMemTestSize feature - Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, - shorter BasicMemTest (faster boot) - $EN_DIS +/** Offset 0x01B3 - DIMM DFE Tap1 Step Size + DIMM DFE Tap1 Step Size for DDR5 OC **/ UINT8 DFETap1StepSize; -/** Offset 0x013F - Dqs Map CPU to DRAM MC 0 CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +/** Offset 0x01B4 - DIMM DFE Tap2 Step Size + DIMM DFE Tap2 Step Size for DDR5 OC **/ - UINT8 DqsMapCpu2DramMc0Ch0[2]; + UINT8 DFETap2StepSize; -/** Offset 0x0141 - Dqs Map CPU to DRAM MC 0 CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +/** Offset 0x01B5 - Reserved **/ - UINT8 DqsMapCpu2DramMc0Ch1[2]; + UINT8 Reserved6; -/** Offset 0x0143 - Dqs Map CPU to DRAM MC 0 CH 2 - Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +/** Offset 0x01B6 - VDD2 override + VDD2 override for DDR5 OC; 0 - Auto **/ - UINT8 DqsMapCpu2DramMc0Ch2[2]; + UINT16 Vdd2Mv; -/** Offset 0x0145 - Dqs Map CPU to DRAM MC 0 CH 3 - Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent -**/ - UINT8 DqsMapCpu2DramMc0Ch3[2]; - -/** Offset 0x0147 - Dqs Map CPU to DRAM MC 1 CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramMc1Ch0[2]; - -/** Offset 0x0149 - Dqs Map CPU to DRAM MC 1 CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramMc1Ch1[2]; - -/** Offset 0x014B - Dqs Map CPU to DRAM MC 1 CH 2 - Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent -**/ - UINT8 DqsMapCpu2DramMc1Ch2[2]; - -/** Offset 0x014D - Dqs Map CPU to DRAM MC 1 CH 3 - Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent -**/ - UINT8 DqsMapCpu2DramMc1Ch3[2]; - -/** Offset 0x014F - Dq Map CPU to DRAM MC 0 CH 0 - Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqMapCpu2DramMc0Ch0[16]; - -/** Offset 0x015F - Dq Map CPU to DRAM MC 0 CH 1 - Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqMapCpu2DramMc0Ch1[16]; - -/** Offset 0x016F - Dq Map CPU to DRAM MC 0 CH 2 - Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent -**/ - UINT8 DqMapCpu2DramMc0Ch2[16]; - -/** Offset 0x017F - Dq Map CPU to DRAM MC 0 CH 3 - Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent -**/ - UINT8 DqMapCpu2DramMc0Ch3[16]; - -/** Offset 0x018F - Dq Map CPU to DRAM MC 1 CH 0 - Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqMapCpu2DramMc1Ch0[16]; - -/** Offset 0x019F - Dq Map CPU to DRAM MC 1 CH 1 - Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqMapCpu2DramMc1Ch1[16]; - -/** Offset 0x01AF - Dq Map CPU to DRAM MC 1 CH 2 - Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent -**/ - UINT8 DqMapCpu2DramMc1Ch2[16]; - -/** Offset 0x01BF - Dq Map CPU to DRAM MC 1 CH 3 - Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent -**/ - UINT8 DqMapCpu2DramMc1Ch3[16]; - -/** Offset 0x01CF - Reserved -**/ - UINT8 Reserved7[2]; - -/** Offset 0x01D1 - MRC OCSafeMode - OverClocking Safe Mode - 0:CMOS, 1:Break, 2:Force -**/ - UINT8 OCSafeMode; - -/** Offset 0x01D2 - Reserved -**/ - UINT8 Reserved8; - -/** Offset 0x01D3 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x01D4 - Reserved -**/ - UINT8 Reserved9[2]; - -/** Offset 0x01D6 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT16 MrcFastBoot; - -/** Offset 0x01D8 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x01D9 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x01DA - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x01DB - Reserved -**/ - UINT8 Reserved10; - -/** Offset 0x01DC - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, - 2133, 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x01DE - SAGV - System Agent dynamic frequency support. - 0:Disabled, 1:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x01DF - SAGV WP Mask - System Agent dynamic frequency workpoints that memory will be training at the enabled - frequencies. - 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 -**/ - UINT8 SaGvWpMask; - -/** Offset 0x01E0 - SAGV Gear Ratio - Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 -**/ - UINT8 SaGvGear[4]; - -/** Offset 0x01E4 - SAGV Frequency - SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. -**/ - UINT16 SaGvFreq[4]; - -/** Offset 0x01EC - SAGV Disabled Gear Ratio - Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 -**/ - UINT8 GearRatio; - -/** Offset 0x01ED - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x01EE - Controller 0 Channel 0 DIMM Control - Enable / Disable DIMMs on Controller 0 Channel 0 - $EN_DIS -**/ - UINT8 DisableMc0Ch0; - -/** Offset 0x01EF - Controller 0 Channel 1 DIMM Control - Enable / Disable DIMMs on Controller 0 Channel 1 - $EN_DIS -**/ - UINT8 DisableMc0Ch1; - -/** Offset 0x01F0 - Controller 0 Channel 2 DIMM Control - Enable / Disable DIMMs on Controller 0 Channel 2 - $EN_DIS -**/ - UINT8 DisableMc0Ch2; - -/** Offset 0x01F1 - Controller 0 Channel 3 DIMM Control - Enable / Disable DIMMs on Controller 0 Channel 3 - $EN_DIS -**/ - UINT8 DisableMc0Ch3; - -/** Offset 0x01F2 - Controller 1 Channel 0 DIMM Control - Enable / Disable DIMMs on Controller 1 Channel 0 - $EN_DIS -**/ - UINT8 DisableMc1Ch0; - -/** Offset 0x01F3 - Controller 1 Channel 1 DIMM Control - Enable / Disable DIMMs on Controller 1 Channel 1 - $EN_DIS -**/ - UINT8 DisableMc1Ch1; - -/** Offset 0x01F4 - Controller 1 Channel 2 DIMM Control - Enable / Disable DIMMs on Controller 1 Channel 2 - $EN_DIS -**/ - UINT8 DisableMc1Ch2; - -/** Offset 0x01F5 - Controller 1 Channel 3 DIMM Control - Enable / Disable DIMMs on Controller 1 Channel 3 - $EN_DIS -**/ - UINT8 DisableMc1Ch3; - -/** Offset 0x01F6 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x01F7 - Reserved -**/ - UINT8 Reserved11[3]; - -/** Offset 0x01FA - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT16 Ratio; - -/** Offset 0x01FC - tCL - CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT16 tCL; - -/** Offset 0x01FE - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT16 tCWL; - -/** Offset 0x0200 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected - == 1 (Custom Profile). -**/ - UINT16 tFAW; - -/** Offset 0x0202 - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x0203 -**/ - UINT8 RXVREFPERBIT; - -/** Offset 0x0204 - Reserved -**/ - UINT8 Reserved12; - -/** Offset 0x0205 - Ch Hash Override - Select if Channel Hash setting values will be taken from input parameters or automatically - taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashOverride; - -/** Offset 0x0206 - Reserved -**/ - UINT8 Reserved13[2]; - -/** Offset 0x0208 - DQS Rise/Fall - Enables/Disable DQS Rise/Fall - $EN_DIS -**/ - UINT8 RDDQSODTT; - -/** Offset 0x0209 - Reserved -**/ - UINT8 Reserved14[2]; - -/** Offset 0x020B - Functional Duty Cycle Correction for DDR5 CLK - Enable/Disable Functional Duty Cycle Correction for DDR5 CLK - 0:Disable, 1:Enable -**/ - UINT8 FUNCDCCCLK; - -/** Offset 0x020C - Functional Duty Cycle Correction for DDR5 DQS - Enable/Disable Functional Duty Cycle Correction for DDR5 DQS - 0:Disable, 1:Enable -**/ - UINT8 FUNCDCCDQS; - -/** Offset 0x020D -**/ - UINT8 FUNCDCCWCK; - -/** Offset 0x020E - Duty Cycle Correction for LP5 DCA - Enable/Disable Duty Cycle Correction for LP5 DCA - $EN_DIS -**/ - UINT8 DCCLP5WCKDCA; - -/** Offset 0x020F - Reserved -**/ - UINT8 Reserved15; - -/** Offset 0x0210 - DQ/DQS Swizzle Training - Enable/Disable DQ/DQS Swizzle Training - $EN_DIS -**/ - UINT32 DQDQSSWZ; - -/** Offset 0x0214 - Reserved -**/ - UINT8 Reserved16[4]; - -/** Offset 0x0218 - Functional Duty Cycle Correction for Data DQ - Enable/Disable Functional Duty Cycle Correction for Data DQ - 0:Disable, 1:Enable -**/ - UINT8 FUNCDCCDQ; - -/** Offset 0x0219 - Reserved -**/ - UINT8 Reserved17[5]; - -/** Offset 0x021E - tRAS +/** Offset 0x01B8 - tRAS RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tRAS; -/** Offset 0x0220 - tRCD/tRP +/** Offset 0x01BA - tRCD/tRP RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tRCDtRP; -/** Offset 0x0222 - Reserved -**/ - UINT8 Reserved18[2]; - -/** Offset 0x0224 - tREFI +/** Offset 0x01BC - tREFI Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT32 tREFI; -/** Offset 0x0228 - Unmatched Rx Calibration - Enable/Disable Rx Unmatched Calibration - $EN_DIS +/** Offset 0x01C0 - tCL + CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). **/ - UINT32 RXUNMATCHEDCAL; + UINT16 tCL; -/** Offset 0x022C - Hard Post Package Repair - Enables/Disable Hard Post Package Repair - $EN_DIS +/** Offset 0x01C2 - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). **/ - UINT32 PPR; + UINT16 tCWL; -/** Offset 0x0230 - Reserved +/** Offset 0x01C4 - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). **/ - UINT8 Reserved19; + UINT16 tFAW; -/** Offset 0x0231 - PPR Run Once - When Eanble, PPR will run only once and then is disabled at next training cycle - $EN_DIS -**/ - UINT8 PprRunOnce; - -/** Offset 0x0232 - PPR Run During Fastboot - When Eanble, PPR will run during fastboot - $EN_DIS -**/ - UINT8 PprRunAtFastboot; - -/** Offset 0x0233 - PPR Repair Type - PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair - 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair -**/ - UINT8 PprRepairType; - -/** Offset 0x0234 - PPR Error Injection - When Eanble, PPR will inject bad rows during testing - $EN_DIS -**/ - UINT8 PprErrorInjection; - -/** Offset 0x0235 - PPR Repair Controller - PPR repair controller: User chooses to force repair specifc address -**/ - UINT8 PprRepairController; - -/** Offset 0x0236 - PPR Repair Channel - PPR repair Channel: User chooses to force repair specifc address -**/ - UINT8 PprRepairChannel; - -/** Offset 0x0237 - PPR Repair Dimm - PPR repair Dimm: User chooses to force repair specifc address -**/ - UINT8 PprRepairDimm; - -/** Offset 0x0238 - PPR Repair Rank - PPR repair Rank: User chooses to force repair specifc address -**/ - UINT8 PprRepairRank; - -/** Offset 0x0239 - Reserved -**/ - UINT8 Reserved20[3]; - -/** Offset 0x023C - PPR Repair Row - PPR repair Row: User chooses to force repair specifc address -**/ - UINT32 PprRepairRow; - -/** Offset 0x0240 - Reserved -**/ - UINT8 Reserved21[8]; - -/** Offset 0x0248 - PPR Repair BankGroup - PPR repair BankGroup: User chooses to force repair specifc address -**/ - UINT8 PprRepairBankGroup; - -/** Offset 0x0249 - Reserved -**/ - UINT8 Reserved22; - -/** Offset 0x024A - tCCD_L_WR - Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same - bank groups -**/ - UINT16 tCCD_L_WR; - -/** Offset 0x024C - LVR Auto Trim - Enable/disable LVR Auto Trim - $EN_DIS -**/ - UINT32 LVRAUTOTRIM; - -/** Offset 0x0250 - Power Saving Meter Update - Enable/Disable Power Saving Meter Update - $EN_DIS -**/ - UINT32 PWRMETER; - -/** Offset 0x0254 - Compensation Optimization - Enable/Disable Compensation Optimization - $EN_DIS -**/ - UINT32 OPTIMIZECOMP; - -/** Offset 0x0258 - Write DQ/DQS Retraining - Enable/Disable Write DQ/DQS Retraining - $EN_DIS -**/ - UINT32 WRTRETRAIN; - -/** Offset 0x025C - Pre-Training Comp Calibration - Enable/Disable Pre-Training Comp Calibration - $EN_DIS -**/ - UINT32 DDRPRECOMP; - -/** Offset 0x0260 - Reserved -**/ - UINT8 Reserved23[12]; - -/** Offset 0x026C - RDDQODTT - Enable/disable Read DQ ODT Training - $EN_DIS -**/ - UINT32 RDDQODTT; - -/** Offset 0x0270 - RDCTLET - Enable/disable Read CTLE Training - $EN_DIS -**/ - UINT32 RDCTLET; - -/** Offset 0x0274 - RxVref Pre EMPHASIS Training - Enable/Disable Pre EMPHASIS Training - $EN_DIS -**/ - UINT8 EMPHASIS; - -/** Offset 0x0275 - Reserved -**/ - UINT8 Reserved24; - -/** Offset 0x0276 - tRFC +/** Offset 0x01C6 - tRFC Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tRFC; -/** Offset 0x0278 - tRRD +/** Offset 0x01C8 - tRRD Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tRRD; -/** Offset 0x027A - tRTP +/** Offset 0x01CA - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tRTP; -/** Offset 0x027C - tWR +/** Offset 0x01CC - tWR Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, @@ -890,522 +422,943 @@ **/ UINT16 tWR; -/** Offset 0x027E - tWTR +/** Offset 0x01CE - tWTR Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tWTR; -/** Offset 0x0280 - NMode +/** Offset 0x01D0 - tWTR_S + tWTR_S value for OC Custom Profile, 0 - Auto +**/ + UINT16 tWTR_S; + +/** Offset 0x01D2 - tWTR_L + tWTR_L value for OC Custom Profile, 0 - Auto +**/ + UINT16 tWTR_L; + +/** Offset 0x01D4 - tCCD_L + tCCD_L value for OC Custom Profile, 0 - Auto +**/ + UINT16 tCCD_L; + +/** Offset 0x01D6 - tRRD_S + tRRD_S value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRRD_S; + +/** Offset 0x01D8 - tRRD_L + tRRD_L value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRRD_L; + +/** Offset 0x01DA - tRFC4 + tRFC4 value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRFC4; + +/** Offset 0x01DC - tRFC2 + tRFC2 value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRFC2; + +/** Offset 0x01DE - tRFCpb + tRFCpb value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRFCpb; + +/** Offset 0x01E0 - tCCD_L_WR + Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same + bank groups, for OC Custom Profile, 0 - Auto +**/ + UINT16 tCCD_L_WR; + +/** Offset 0x01E2 - Reserved +**/ + UINT8 Reserved7[2]; + +/** Offset 0x01E4 - LPMode Support + Bit[0]: Enable Lpmode0p5 (Idle_enable), Bit[1]: Enable Lpmode2 (Powerdown_enable), + Bit[2]: Enable Lpmode3 (Selfrefresh_enable) +**/ + UINT8 LpMode; + +/** Offset 0x01E5 - Reserved +**/ + UINT8 Reserved8[2]; + +/** Offset 0x01E7 - MRC OCSafeMode + OverClocking Safe Mode for tCL + $EN_DIS +**/ + UINT8 OCSafeMode; + +/** Offset 0x01E8 - Reserved +**/ + UINT8 Reserved9; + +/** Offset 0x01E9 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x01EA - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x01EB - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x01EC - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x01ED - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x01EE - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x01EF - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x01F0 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x01F2 - SAGV + System Agent dynamic frequency support. + 0:Disabled, 1:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x01F3 - SAGV WP Mask + System Agent dynamic frequency workpoints that memory will be training at the enabled + frequencies. + 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 +**/ + UINT8 SaGvWpMask; + +/** Offset 0x01F4 - SAGV Gear Ratio + Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 SaGvGear[4]; + +/** Offset 0x01F8 - SAGV Frequency + SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. +**/ + UINT16 SaGvFreq[4]; + +/** Offset 0x0200 - SAGV Disabled Gear Ratio + Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 GearRatio; + +/** Offset 0x0201 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0202 - Controller 0 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc0Ch0; + +/** Offset 0x0203 - Controller 0 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc0Ch1; + +/** Offset 0x0204 - Controller 0 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc0Ch2; + +/** Offset 0x0205 - Controller 0 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc0Ch3; + +/** Offset 0x0206 - Controller 1 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc1Ch0; + +/** Offset 0x0207 - Controller 1 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc1Ch1; + +/** Offset 0x0208 - Controller 1 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc1Ch2; + +/** Offset 0x0209 - Controller 1 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc1Ch3; + +/** Offset 0x020A - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x020B - Reserved +**/ + UINT8 Reserved11; + +/** Offset 0x020C - Memory Voltage + DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM + chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. + 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 + Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts +**/ + UINT16 VddVoltage; + +/** Offset 0x020E - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT16 Ratio; + +/** Offset 0x0210 - SPD Profile Selected + Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP + Profile 1, 3=XMP Profile 2 + 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x0211 +**/ + UINT8 RXVREFPERBIT; + +/** Offset 0x0212 - Reserved +**/ + UINT8 Reserved12; + +/** Offset 0x0213 - Ch Hash Override + Select if Channel Hash setting values will be taken from input parameters or automatically + taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashOverride; + +/** Offset 0x0214 - Reserved +**/ + UINT8 Reserved13[2]; + +/** Offset 0x0216 - DQS Rise/Fall + Enables/Disable DQS Rise/Fall + $EN_DIS +**/ + UINT8 RDDQSODTT; + +/** Offset 0x0217 - Reserved +**/ + UINT8 Reserved14[2]; + +/** Offset 0x0219 - Functional Duty Cycle Correction for DDR5 CLK + Enable/Disable Functional Duty Cycle Correction for DDR5 CLK + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCCLK; + +/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 DQS + Enable/Disable Functional Duty Cycle Correction for DDR5 DQS + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCDQS; + +/** Offset 0x021B +**/ + UINT8 FUNCDCCWCK; + +/** Offset 0x021C - Duty Cycle Correction for LP5 DCA + Enable/Disable Duty Cycle Correction for LP5 DCA + $EN_DIS +**/ + UINT8 DCCLP5WCKDCA; + +/** Offset 0x021D - DQ/DQS Swizzle Training + Enable/Disable DQ/DQS Swizzle Training + $EN_DIS +**/ + UINT8 DQDQSSWZ; + +/** Offset 0x021E - Reserved +**/ + UINT8 Reserved15; + +/** Offset 0x021F - Functional Duty Cycle Correction for Data DQ + Enable/Disable Functional Duty Cycle Correction for Data DQ + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCDQ; + +/** Offset 0x0220 - Reserved +**/ + UINT8 Reserved16[5]; + +/** Offset 0x0225 - Unmatched Rx Calibration + Enable/Disable Rx Unmatched Calibration + $EN_DIS +**/ + UINT8 RXUNMATCHEDCAL; + +/** Offset 0x0226 - Hard Post Package Repair + Enables/Disable Hard Post Package Repair + $EN_DIS +**/ + UINT8 PPR; + +/** Offset 0x0227 - Reserved +**/ + UINT8 Reserved17; + +/** Offset 0x0228 - PPR Run Once + When Eanble, PPR will run only once and then is disabled at next training cycle + $EN_DIS +**/ + UINT8 PprRunOnce; + +/** Offset 0x0229 - PPR Run During Fastboot + When Eanble, PPR will run during fastboot + $EN_DIS +**/ + UINT8 PprRunAtFastboot; + +/** Offset 0x022A - PPR Repair Type + PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair + 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair +**/ + UINT8 PprRepairType; + +/** Offset 0x022B - PPR Error Injection + When Eanble, PPR will inject bad rows during testing + $EN_DIS +**/ + UINT8 PprErrorInjection; + +/** Offset 0x022C - PPR Repair Controller + PPR repair controller: User chooses to force repair specifc address +**/ + UINT8 PprRepairController; + +/** Offset 0x022D - PPR Repair Channel + PPR repair Channel: User chooses to force repair specifc address +**/ + UINT8 PprRepairChannel; + +/** Offset 0x022E - PPR Repair Dimm + PPR repair Dimm: User chooses to force repair specifc address +**/ + UINT8 PprRepairDimm; + +/** Offset 0x022F - PPR Repair Rank + PPR repair Rank: User chooses to force repair specifc address +**/ + UINT8 PprRepairRank; + +/** Offset 0x0230 - PPR Repair Row + PPR repair Row: User chooses to force repair specifc address +**/ + UINT32 PprRepairRow; + +/** Offset 0x0234 - Reserved +**/ + UINT8 Reserved18[8]; + +/** Offset 0x023C - PPR Repair BankGroup + PPR repair BankGroup: User chooses to force repair specifc address +**/ + UINT8 PprRepairBankGroup; + +/** Offset 0x023D - LVR Auto Trim + Enable/disable LVR Auto Trim + $EN_DIS +**/ + UINT8 LVRAUTOTRIM; + +/** Offset 0x023E - Compensation Optimization + Enable/Disable Compensation Optimization + $EN_DIS +**/ + UINT8 OPTIMIZECOMP; + +/** Offset 0x023F - Write DQ/DQS Retraining + Enable/Disable Write DQ/DQS Retraining + $EN_DIS +**/ + UINT8 WRTRETRAIN; + +/** Offset 0x0240 - Reserved +**/ + UINT8 Reserved19[3]; + +/** Offset 0x0243 - RDDQODTT + Enable/disable Read DQ ODT Training + $EN_DIS +**/ + UINT8 RDDQODTT; + +/** Offset 0x0244 - RDCTLET + Enable/disable Read CTLE Training + $EN_DIS +**/ + UINT8 RDCTLET; + +/** Offset 0x0245 - RxVref Pre EMPHASIS Training + Enable/Disable Pre EMPHASIS Training + $EN_DIS +**/ + UINT8 EMPHASIS; + +/** Offset 0x0246 - RX DQS VOC Centring Training + Enable/Disable RX DQS VOC Centring Training + $EN_DIS +**/ + UINT8 RXDQSVOCC; + +/** Offset 0x0247 - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N **/ UINT8 NModeSupport; -/** Offset 0x0281 - LPDDR ODT RttWr +/** Offset 0x0248 - LPDDR ODT RttWr Initial RttWr for LP4/5 in Ohms. 0x0 - Auto **/ UINT8 LpddrRttWr; -/** Offset 0x0282 - Retrain on Fast flow Failure +/** Offset 0x0249 - Retrain on Fast flow Failure Restart MRC in Cold mode if SW MemTest fails during Fast flow. $EN_DIS **/ UINT8 RetrainOnFastFail; -/** Offset 0x0283 - LPDDR ODT RttCa +/** Offset 0x024A - LPDDR ODT RttCa Initial RttCa for LP4/5 in Ohms. 0x0 - Auto **/ UINT8 LpddrRttCa; -/** Offset 0x0284 - DIMM DFE Training +/** Offset 0x024B - DIMM DFE Training Enable/Disable DIMM DFE Training $EN_DIS **/ UINT8 WRTDIMMDFE; -/** Offset 0x0285 - DDR5 ODT Timing Config +/** Offset 0x024C - DDR5 ODT Timing Config Enable/Disable DDR5 ODT TIMING CONFIG $EN_DIS **/ UINT8 DDR5ODTTIMING; -/** Offset 0x0286 - HobBufferSize +/** Offset 0x024D - HobBufferSize Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size). 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value **/ UINT8 HobBufferSize; -/** Offset 0x0287 - Early Command Training +/** Offset 0x024E - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x0288 - SenseAmp Offset Training +/** Offset 0x024F - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS **/ UINT8 SOT; -/** Offset 0x0289 - Early ReadMPR Timing Centering 2D +/** Offset 0x0250 - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $EN_DIS **/ UINT8 ERDMPRTC2D; -/** Offset 0x028A - Read MPR Training +/** Offset 0x0251 - Read MPR Training Enables/Disable Read MPR Training $EN_DIS **/ UINT8 RDMPRT; -/** Offset 0x028B - Receive Enable Training +/** Offset 0x0252 - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS **/ UINT8 RCVET; -/** Offset 0x028C - Jedec Write Leveling +/** Offset 0x0253 - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS **/ UINT8 JWRL; -/** Offset 0x028D - Early Write Time Centering 2D +/** Offset 0x0254 - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS **/ UINT8 EWRTC2D; -/** Offset 0x028E - Early Read Time Centering 2D +/** Offset 0x0255 - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS **/ UINT8 ERDTC2D; -/** Offset 0x028F - Unmatched Write Time Centering 1D +/** Offset 0x0256 - Unmatched Write Time Centering 1D Enable/Disable Unmatched Write Time Centering 1D $EN_DIS **/ UINT8 UNMATCHEDWRTC1D; -/** Offset 0x0290 - Write Timing Centering 1D +/** Offset 0x0257 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS **/ UINT8 WRTC1D; -/** Offset 0x0291 - Write Voltage Centering 1D +/** Offset 0x0258 - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS **/ UINT8 WRVC1D; -/** Offset 0x0292 - Read Timing Centering 1D +/** Offset 0x0259 - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS **/ UINT8 RDTC1D; -/** Offset 0x0293 - Dimm ODT Training +/** Offset 0x025A - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS **/ UINT8 DIMMODTT; -/** Offset 0x0294 - DIMM RON Training +/** Offset 0x025B - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS **/ UINT8 DIMMRONT; -/** Offset 0x0295 - Write Drive Strength/Equalization 2D +/** Offset 0x025C - Write Drive Strength/Equalization 2D Enables/Disable Write Drive Strength/Equalization 2D $EN_DIS **/ UINT8 WRDSEQT; -/** Offset 0x0296 - Read Equalization Training +/** Offset 0x025D - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS **/ UINT8 RDEQT; -/** Offset 0x0297 - Write Timing Centering 2D +/** Offset 0x025E - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS **/ UINT8 WRTC2D; -/** Offset 0x0298 - Read Timing Centering 2D +/** Offset 0x025F - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS **/ UINT8 RDTC2D; -/** Offset 0x0299 - Write Voltage Centering 2D +/** Offset 0x0260 - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS **/ UINT8 WRVC2D; -/** Offset 0x029A - Read Voltage Centering 2D +/** Offset 0x0261 - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS **/ UINT8 RDVC2D; -/** Offset 0x029B - Command Voltage Centering +/** Offset 0x0262 - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS **/ UINT8 CMDVC; -/** Offset 0x029C - Late Command Training +/** Offset 0x0263 - Late Command Training Enables/Disable Late Command Training $EN_DIS **/ UINT8 LCT; -/** Offset 0x029D - Round Trip Latency Training +/** Offset 0x0264 - Round Trip Latency Training Enables/Disable Round Trip Latency Training $EN_DIS **/ UINT8 RTL; -/** Offset 0x029E - Turn Around Timing Training +/** Offset 0x0265 - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS **/ UINT8 TAT; -/** Offset 0x029F - Reserved +/** Offset 0x0266 - Reserved **/ - UINT8 Reserved25; + UINT8 Reserved20; -/** Offset 0x02A0 - DIMM SPD Alias Test +/** Offset 0x0267 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS **/ UINT8 ALIASCHK; -/** Offset 0x02A1 - Receive Enable Centering 1D +/** Offset 0x0268 - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D $EN_DIS **/ UINT8 RCVENC1D; -/** Offset 0x02A2 - Retrain Margin Check +/** Offset 0x0269 - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS **/ UINT8 RMC; -/** Offset 0x02A3 - ECC Support +/** Offset 0x026A - ECC Support Enables/Disable ECC Support $EN_DIS **/ UINT8 EccSupport; -/** Offset 0x02A4 - Reserved +/** Offset 0x026B - Reserved **/ - UINT8 Reserved26[2]; + UINT8 Reserved21[2]; -/** Offset 0x02A6 - Ibecc +/** Offset 0x026D - Ibecc In-Band ECC Support $EN_DIS **/ UINT8 Ibecc; -/** Offset 0x02A7 - IbeccParity +/** Offset 0x026E - IbeccParity In-Band ECC Parity Control $EN_DIS **/ UINT8 IbeccParity; -/** Offset 0x02A8 - Reserved +/** Offset 0x026F - Reserved **/ - UINT8 Reserved27[4]; + UINT8 Reserved22; -/** Offset 0x02AC - IbeccOperationMode +/** Offset 0x0270 - IbeccOperationMode In-Band ECC Operation Mode 0:Protect base on address range, 1: Non-protected, 2: All protected **/ UINT8 IbeccOperationMode; -/** Offset 0x02AD - IbeccProtectedRegionEnable +/** Offset 0x0271 - IbeccProtectedRegionEnable In-Band ECC Protected Region Enable $EN_DIS **/ UINT8 IbeccProtectedRegionEnable[8]; -/** Offset 0x02B5 - Reserved +/** Offset 0x0279 - Reserved **/ - UINT8 Reserved28; + UINT8 Reserved23; -/** Offset 0x02B6 - IbeccProtectedRegionBases +/** Offset 0x027A - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance **/ UINT16 IbeccProtectedRegionBase[8]; -/** Offset 0x02C6 - IbeccProtectedRegionMasks +/** Offset 0x028A - IbeccProtectedRegionMasks IBECC Protected Region Masks **/ UINT16 IbeccProtectedRegionMask[8]; -/** Offset 0x02D6 - Memory Remap +/** Offset 0x029A - Memory Remap Enables/Disable Memory Remap $EN_DIS **/ UINT8 RemapEnable; -/** Offset 0x02D7 - Reserved -**/ - UINT8 Reserved29; - -/** Offset 0x02D8 - Rank Interleave support +/** Offset 0x029B - Rank Interleave support Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time. $EN_DIS **/ - UINT32 RankInterleave; + UINT8 RankInterleave; -/** Offset 0x02DC - Enhanced Interleave support +/** Offset 0x029C - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS **/ - UINT32 EnhancedInterleave; + UINT8 EnhancedInterleave; -/** Offset 0x02E0 - Ch Hash Support +/** Offset 0x029D - Ch Hash Support Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode $EN_DIS **/ - UINT32 ChHashEnable; + UINT8 ChHashEnable; -/** Offset 0x02E4 - DDR PowerDown and idle counter +/** Offset 0x029E - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ - UINT32 EnablePwrDn; + UINT8 EnablePwrDn; -/** Offset 0x02E8 - DDR PowerDown and idle counter +/** Offset 0x029F - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ UINT8 EnablePwrDnLpddr; -/** Offset 0x02E9 - Reserved -**/ - UINT8 Reserved30[3]; - -/** Offset 0x02EC - SelfRefresh Enable +/** Offset 0x02A0 - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS **/ - UINT32 SrefCfgEna; + UINT8 SrefCfgEna; -/** Offset 0x02F0 - Throttler CKEMin Defeature +/** Offset 0x02A1 - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) $EN_DIS **/ UINT8 ThrtCkeMinDefeatLpddr; -/** Offset 0x02F1 - Reserved -**/ - UINT8 Reserved31[3]; - -/** Offset 0x02F4 - Throttler CKEMin Defeature +/** Offset 0x02A2 - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS **/ - UINT32 ThrtCkeMinDefeat; + UINT8 ThrtCkeMinDefeat; -/** Offset 0x02F8 - Exit On Failure (MRC) +/** Offset 0x02A3 - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS **/ UINT8 ExitOnFailure; -/** Offset 0x02F9 - Reserved +/** Offset 0x02A4 - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved24[2]; -/** Offset 0x02FB - Read Voltage Centering 1D +/** Offset 0x02A6 - Read Voltage Centering 1D Enable/Disable Read Voltage Centering 1D $EN_DIS **/ UINT8 RDVC1D; -/** Offset 0x02FC - TxDqTCO Comp Training +/** Offset 0x02A7 - TxDqTCO Comp Training Enable/Disable TxDqTCO Comp Training $EN_DIS **/ UINT8 TXTCO; -/** Offset 0x02FD - ClkTCO Comp Training +/** Offset 0x02A8 - ClkTCO Comp Training Enable/Disable ClkTCO Comp Training $EN_DIS **/ UINT8 CLKTCO; -/** Offset 0x02FE - CMD Slew Rate Training +/** Offset 0x02A9 - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS **/ UINT8 CMDSR; -/** Offset 0x02FF - CMD Drive Strength and Tx Equalization +/** Offset 0x02AA - CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equalization $EN_DIS **/ UINT8 CMDDSEQ; -/** Offset 0x0300 - DIMM CA ODT Training +/** Offset 0x02AB - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training $EN_DIS **/ UINT8 DIMMODTCA; -/** Offset 0x0301 - Read Vref Decap Training* +/** Offset 0x02AC - Read Vref Decap Training* Enable/Disable Read Vref Decap Training* $EN_DIS **/ UINT8 RDVREFDC; -/** Offset 0x0302 - Vddq Training - Enable/Disable Vddq Training - $EN_DIS -**/ - UINT8 VDDQT; - -/** Offset 0x0303 - Rank Margin Tool Per Bit +/** Offset 0x02AD - Rank Margin Tool Per Bit Enable/Disable Rank Margin Tool Per Bit $EN_DIS **/ UINT8 RMTBIT; -/** Offset 0x0304 - Ref PI Calibration +/** Offset 0x02AE - Ref PI Calibration Enable/Disable Ref PI Calibration $EN_DIS **/ UINT8 REFPI; -/** Offset 0x0305 - VccClk FF Offset Correction +/** Offset 0x02AF - VccClk FF Offset Correction Enable/Disable VccClk FF Offset Correction 0:Disable, 1:Enable **/ UINT8 VCCCLKFF; -/** Offset 0x0306 - Reserved -**/ - UINT8 Reserved33[2]; - -/** Offset 0x0308 - Data PI Linearity Calibration +/** Offset 0x02B0 - Data PI Linearity Calibration Enable/Disable {Data PI Linearity Calibration $EN_DIS **/ - UINT32 DATAPILIN; + UINT8 DATAPILIN; -/** Offset 0x030C - Ddr5 Rx Cross-Talk Cancellation +/** Offset 0x02B1 - Ddr5 Rx Cross-Talk Cancellation Enable/Disable {Ddr5 Rx Cross-Talk Cancellation $EN_DIS **/ UINT8 DDR5XTALK; -/** Offset 0x030D - Retrain On Working Channel +/** Offset 0x02B2 - Retrain On Working Channel Enables/Disable Retrain On Working Channel feature $EN_DIS **/ UINT8 RetrainToWorkingChannel; -/** Offset 0x030E - Reserved +/** Offset 0x02B3 - Row Press + Enables/Disable Row Press feature + $EN_DIS **/ - UINT8 Reserved34; + UINT8 RowPressEn; -/** Offset 0x030F - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP +/** Offset 0x02B4 - Reserved +**/ + UINT8 Reserved25; + +/** Offset 0x02B5 - DDR5 MR7 WICA support + Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment $EN_DIS **/ UINT8 IsDdr5MR7WicaSupported; -/** Offset 0x0310 - Ch Hash Interleaved Bit +/** Offset 0x02B6 - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 **/ UINT8 ChHashInterleaveBit; -/** Offset 0x0311 - Reserved +/** Offset 0x02B7 - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved26; -/** Offset 0x0312 - Ch Hash Mask +/** Offset 0x02B8 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC **/ UINT16 ChHashMask; -/** Offset 0x0314 - Reserved +/** Offset 0x02BA - Reserved **/ - UINT8 Reserved36[2]; + UINT8 Reserved27; -/** Offset 0x0316 - Throttler CKEMin Timer +/** Offset 0x02BB - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Dfault is 0x00 **/ UINT8 ThrtCkeMinTmr; -/** Offset 0x0317 - Allow Opp Ref Below Write Threhold +/** Offset 0x02BC - Allow Opp Ref Below Write Threhold Allow opportunistic refreshes while we don't exit power down. $EN_DIS **/ UINT8 AllowOppRefBelowWriteThrehold; -/** Offset 0x0318 - Write Threshold +/** Offset 0x02BD - Write Threshold Number of writes that can be accumulated while CKE is low before CKE is asserted. **/ UINT8 WriteThreshold; -/** Offset 0x0319 - MC_REFRESH_RATE +/** Offset 0x02BE - MC_REFRESH_RATE Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh **/ UINT8 McRefreshRate; -/** Offset 0x031A - Refresh Watermarks +/** Offset 0x02BF - Refresh Watermarks Refresh Watermarks: 0-Low, 1-High (default) 0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default) **/ UINT8 RefreshWm; -/** Offset 0x031B - Reserved +/** Offset 0x02C0 - User Manual Threshold + Disabled: Predefined threshold will be used.\n + Enabled: User Input will be used. + $EN_DIS **/ - UINT8 Reserved37[2]; + UINT8 UserThresholdEnable; -/** Offset 0x031D - Power Down Mode +/** Offset 0x02C1 - User Manual Budget + Disabled: Configuration of memories will defined the Budget value.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserBudgetEnable; + +/** Offset 0x02C2 - Power Down Mode This option controls command bus tristating during idle periods 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto **/ UINT8 PowerDownMode; -/** Offset 0x031E - Pwr Down Idle Timer +/** Offset 0x02C3 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo **/ UINT8 PwdwnIdleCounter; -/** Offset 0x031F - Page Close Idle Timeout +/** Offset 0x02C4 - Page Close Idle Timeout This option controls Page Close Idle Timeout 0:Enabled, 1:Disabled **/ UINT8 DisPgCloseIdleTimeout; -/** Offset 0x0320 - Reserved +/** Offset 0x02C5 - Bitmask of ranks that have CA bus terminated + LPDDR5: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is + terminating and Rank1 is non-terminating **/ - UINT8 Reserved38; + UINT8 CmdRanksTerminated; -/** Offset 0x0321 - MRC Safe Mode Override +/** Offset 0x02C6 - MRC Safe Mode Override SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3] Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4] @@ -1413,18 +1366,18 @@ **/ UINT8 SafeModeOverride; -/** Offset 0x0322 - Reserved +/** Offset 0x02C7 - Reserved **/ - UINT8 Reserved39[2]; + UINT8 Reserved28[5]; -/** Offset 0x0324 - DDR Phy Safe Mode Support +/** Offset 0x02CC - DDR Phy Safe Mode Support DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]: Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]: PLL Operation, DdrSafeMode[6]: Safe ODT **/ UINT32 DdrSafeMode; -/** Offset 0x0328 - Mc Safe Mode Support +/** Offset 0x02D0 - Mc Safe Mode Support McSafeMode[0]: Clk Gate / BGF, McSafeMode[1]: CKE Pdwn, McSafeMode[2]: Tristate, McSafeMode[3]: PHY Power States / Clock Spine, McSafeMode[4]: Same Rank TA, McSafeMode[5]: Different Rank TA, McSafeMode[6]: MR4_Period / ZQCAL_Period McSafeMode[7]: LP5 @@ -1433,349 +1386,360 @@ **/ UINT8 McSafeMode; -/** Offset 0x0329 - Ask MRC to clear memory content +/** Offset 0x02D1 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. $EN_DIS **/ UINT8 CleanMemory; -/** Offset 0x032A - Reserved +/** Offset 0x02D2 - Reserved **/ - UINT8 Reserved40[8]; + UINT8 Reserved29[8]; -/** Offset 0x0332 - RMTLoopCount +/** Offset 0x02DA - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO **/ UINT8 RMTLoopCount; -/** Offset 0x0333 - DdrOneDpc +/** Offset 0x02DB - DdrOneDpc DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, or on both (default) 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled **/ UINT8 DdrOneDpc; -/** Offset 0x0334 - Vddq Voltage Override +/** Offset 0x02DC - Vddq Voltage Override # is multiple of 1mV where 0 means Auto. **/ UINT16 VddqVoltageOverride; -/** Offset 0x0336 - VccIog Voltage Override +/** Offset 0x02DE - VccIog Voltage Override # is multiple of 1mV where 0 means Auto. **/ UINT16 VccIogVoltageOverride; -/** Offset 0x0338 - VccClk Voltage Override +/** Offset 0x02E0 - VccClk Voltage Override # is multiple of 1mV where 0 means Auto. **/ UINT16 VccClkVoltageOverride; -/** Offset 0x033A - ThrtCkeMinTmrLpddr +/** Offset 0x02E2 - ThrtCkeMinTmrLpddr Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default **/ UINT8 ThrtCkeMinTmrLpddr; -/** Offset 0x033B - Reserved +/** Offset 0x02E3 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved30; -/** Offset 0x033C - Margin limit check L2 +/** Offset 0x02E4 - Margin limit check L2 Margin limit check L2 threshold: 100=Default **/ UINT16 MarginLimitL2; -/** Offset 0x033E - Extended Bank Hashing +/** Offset 0x02E6 - Extended Bank Hashing Eanble/Disable ExtendedBankHashing $EN_DIS **/ UINT8 ExtendedBankHashing; -/** Offset 0x033F - Reserved +/** Offset 0x02E7 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved31; -/** Offset 0x0340 - Command Pins Mapping +/** Offset 0x02E8 - LP5 Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. **/ UINT8 Lp5CccConfig; -/** Offset 0x0341 - Command Pins Mirrored +/** Offset 0x02E9 - Command Pins Mirrored BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. **/ UINT8 CmdMirror; -/** Offset 0x0342 - Time Measure +/** Offset 0x02EA - Time Measure Time Measure: 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 MrcTimeMeasure; -/** Offset 0x0343 - Reserved +/** Offset 0x02EB - Reserved **/ - UINT8 Reserved43[8]; + UINT8 Reserved32[66]; -/** Offset 0x034B - Board Type +/** Offset 0x032D - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server **/ UINT8 UserBd; -/** Offset 0x034C - Spd Address Table +/** Offset 0x032E - Spd Address Table Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00 **/ UINT8 SpdAddressTable[16]; -/** Offset 0x035C - Enable/Disable MRC TXT dependency +/** Offset 0x033E - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization $EN_DIS **/ UINT8 TxtImplemented; -/** Offset 0x035D - Reserved +/** Offset 0x033F - Reserved **/ - UINT8 Reserved44; + UINT8 Reserved33; -/** Offset 0x035E - Skip external display device scanning +/** Offset 0x0340 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x035F - Generate BIOS Data ACPI Table +/** Offset 0x0341 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it $EN_DIS **/ UINT8 BdatEnable; -/** Offset 0x0360 - BdatTestType +/** Offset 0x0342 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D **/ UINT8 BdatTestType; -/** Offset 0x0361 - Enable PCH HSIO PCIE Rx Set Ctle +/** Offset 0x0343 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. **/ UINT8 PchPcieHsioRxSetCtleEnable[28]; -/** Offset 0x037D - PCH HSIO PCIE Rx Set Ctle Value +/** Offset 0x035F - PCH HSIO PCIE Rx Set Ctle Value PCH PCIe Gen 3 Set CTLE Value. **/ UINT8 PchPcieHsioRxSetCtle[28]; -/** Offset 0x0399 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override +/** Offset 0x037B - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; -/** Offset 0x03B5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value +/** Offset 0x0397 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; -/** Offset 0x03D1 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override +/** Offset 0x03B3 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; -/** Offset 0x03ED - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value +/** Offset 0x03CF - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; -/** Offset 0x0409 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override +/** Offset 0x03EB - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; -/** Offset 0x0425 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value +/** Offset 0x0407 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; -/** Offset 0x0441 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x0423 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; -/** Offset 0x045D - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value +/** Offset 0x043F - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen1DeEmph[28]; -/** Offset 0x0479 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override +/** Offset 0x045B - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; -/** Offset 0x0495 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value +/** Offset 0x0477 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; -/** Offset 0x04B1 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override +/** Offset 0x0493 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; -/** Offset 0x04CD - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value +/** Offset 0x04AF - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; -/** Offset 0x04E9 - HD Audio DMIC Link Clock Select +/** Offset 0x04CB - HD Audio DMIC Link Clock Select Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB 0: Both, 1: ClkA, 2: ClkB **/ UINT8 PchHdaAudioLinkDmicClockSelect[2]; -/** Offset 0x04EB - Enable Intel HD Audio (Azalia) +/** Offset 0x04CD - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller $EN_DIS **/ UINT8 PchHdaEnable; -/** Offset 0x04EC - Universal Audio Architecture compliance for DSP enabled system +/** Offset 0x04CE - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). $EN_DIS **/ UINT8 PchHdaDspUaaCompliance; -/** Offset 0x04ED - Enable HD Audio Link +/** Offset 0x04CF - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x04EE - Enable HDA SDI lanes +/** Offset 0x04D0 - Enable HDA SDI lanes Enable/disable HDA SDI lanes. **/ UINT8 PchHdaSdiEnable[2]; -/** Offset 0x04F0 - Enable HD Audio DMIC_N Link +/** Offset 0x04D2 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x04F2 - Reserved -**/ - UINT8 Reserved45[2]; - -/** Offset 0x04F4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) +/** Offset 0x04D4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* **/ UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; -/** Offset 0x04FC - Enable HD Audio DSP +/** Offset 0x04DC - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x04FD - Reserved +/** Offset 0x04DD - Reserved **/ - UINT8 Reserved46[3]; + UINT8 Reserved34[3]; -/** Offset 0x0500 - DMIC<N> Data Pin Muxing +/** Offset 0x04E0 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* **/ UINT32 PchHdaAudioLinkDmicDataPinMux[2]; -/** Offset 0x0508 - Enable HD Audio SSP0 Link +/** Offset 0x04E8 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[7]; -/** Offset 0x050F - Reserved +/** Offset 0x04EF - Reserved **/ - UINT8 Reserved47[117]; + UINT8 Reserved35[117]; -/** Offset 0x0584 - Enable HD Audio SoundWire#N Link +/** Offset 0x0564 - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[5]; -/** Offset 0x0589 - iDisp-Link Frequency +/** Offset 0x0569 - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x058A - iDisp-Link T-mode +/** Offset 0x056A - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x058B - Reserved +/** Offset 0x056B - Reserved **/ - UINT8 Reserved48[45]; + UINT8 Reserved36[45]; -/** Offset 0x05B8 - iDisplay Audio Codec disconnection +/** Offset 0x0598 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x05B9 - Reserved +/** Offset 0x0599 - Reserved **/ - UINT8 Reserved49[5]; + UINT8 Reserved37[5]; -/** Offset 0x05BE - HDA Power/Clock Gating (PGD/CGD) +/** Offset 0x059E - HDA Power/Clock Gating (PGD/CGD) Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE. 0: POR, 1: Force Enable, 2: Force Disable **/ UINT8 PchHdaTestPowerClockGating; -/** Offset 0x05BF - Reserved +/** Offset 0x059F - Reserved **/ - UINT8 Reserved50[6]; + UINT8 Reserved38; -/** Offset 0x05C5 - Usage type for ClkSrc +/** Offset 0x05A0 - Audio Sub System IDs + Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. +**/ + UINT32 PchHdaSubSystemIds; + +/** Offset 0x05A4 - Reserved +**/ + UINT8 Reserved39; + +/** Offset 0x05A5 - PCH LPC Enhance the port 8xh decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x05A6 - Usage type for ClkSrc 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ UINT8 PcieClkSrcUsage[18]; -/** Offset 0x05D7 - ClkReq-to-ClkSrc mapping +/** Offset 0x05B8 - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[18]; -/** Offset 0x05E9 - Reserved +/** Offset 0x05CA - Reserved **/ - UINT8 Reserved51[47]; + UINT8 Reserved40[46]; -/** Offset 0x0618 - Enable PCIE RP Mask +/** Offset 0x05F8 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpEnableMask; -/** Offset 0x061C - Debug Interfaces +/** Offset 0x05FC - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x061D - Reserved +/** Offset 0x05FD - Reserved **/ - UINT8 Reserved52[3]; + UINT8 Reserved41[3]; -/** Offset 0x0620 - Serial Io Uart Debug Mmio Base +/** Offset 0x0600 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode = SerialIoUartPci. **/ UINT32 SerialIoUartDebugMmioBase; -/** Offset 0x0624 - PcdSerialDebugLevel +/** Offset 0x0604 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -1784,7 +1748,7 @@ **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0625 - SerialDebugMrcLevel +/** Offset 0x0605 - SerialDebugMrcLevel MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -1793,318 +1757,318 @@ **/ UINT8 SerialDebugMrcLevel; -/** Offset 0x0626 - Serial Io Uart Debug Controller Number +/** Offset 0x0606 - Serial Io Uart Debug Controller Number Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x0627 - Serial Io Uart Debug Parity +/** Offset 0x0607 - Serial Io Uart Debug Parity Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartDebugParity; -/** Offset 0x0628 - Serial Io Uart Debug BaudRate +/** Offset 0x0608 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 **/ UINT32 SerialIoUartDebugBaudRate; -/** Offset 0x062C - Serial Io Uart Debug Stop Bits +/** Offset 0x060C - Serial Io Uart Debug Stop Bits Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartDebugStopBits; -/** Offset 0x062D - Serial Io Uart Debug Data Bits +/** Offset 0x060D - Serial Io Uart Debug Data Bits Set default word length. 0: Default, 5,6,7,8 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS **/ UINT8 SerialIoUartDebugDataBits; -/** Offset 0x062E - IMGU CLKOUT Configuration +/** Offset 0x060E - IMGU CLKOUT Configuration The configuration of IMGU CLKOUT, 0: Disable;1: Enable. $EN_DIS **/ UINT8 ImguClkOutEn[6]; -/** Offset 0x0634 - Enable/Disable SA IPU +/** Offset 0x0614 - Enable/Disable SA IPU Enable(Default): Enable SA IPU, Disable: Disable SA IPU $EN_DIS **/ UINT8 SaIpuEnable; -/** Offset 0x0635 - Disable and Lock Watch Dog Register +/** Offset 0x0615 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. $EN_DIS **/ UINT8 WdtDisableAndLock; -/** Offset 0x0636 - Reserved +/** Offset 0x0616 - Reserved **/ - UINT8 Reserved53[6]; + UINT8 Reserved42[2]; -/** Offset 0x063C - HECI Timeouts +/** Offset 0x0618 - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI $EN_DIS **/ UINT8 HeciTimeouts; -/** Offset 0x063D - HECI2 Interface Communication +/** Offset 0x0619 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. $EN_DIS **/ UINT8 HeciCommunication2; -/** Offset 0x063E - Check HECI message before send +/** Offset 0x061A - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. $EN_DIS **/ UINT8 DisableMessageCheck; -/** Offset 0x063F - Force ME DID Init Status +/** Offset 0x061B - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS **/ UINT8 DidInitStat; -/** Offset 0x0640 - Enable KT device +/** Offset 0x061C - Enable KT device Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device. $EN_DIS **/ UINT8 KtDeviceEnable; -/** Offset 0x0641 - CPU Replaced Polling Disable +/** Offset 0x061D - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS **/ UINT8 DisableCpuReplacedPolling; -/** Offset 0x0642 - Skip CPU replacement check +/** Offset 0x061E - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x0643 - Skip MBP HOB +/** Offset 0x061F - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob. $EN_DIS **/ UINT8 SkipMbpHob; -/** Offset 0x0644 - Reserved +/** Offset 0x0620 - Reserved **/ - UINT8 Reserved54[2]; + UINT8 Reserved43[2]; -/** Offset 0x0646 - ISA Serial Base selection +/** Offset 0x0622 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x0647 - PcdSerialDebugBaudRate +/** Offset 0x0623 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. 3:9600, 4:19200, 6:56700, 7:115200 **/ UINT8 PcdSerialDebugBaudRate; -/** Offset 0x0648 - Post Code Output Port +/** Offset 0x0624 - Post Code Output Port This option configures Post Code Output Port **/ UINT16 PostCodeOutputPort; -/** Offset 0x064A - Reserved +/** Offset 0x0626 - Reserved **/ - UINT8 Reserved55[26]; + UINT8 Reserved44[22]; -/** Offset 0x0664 - Enable SMBus +/** Offset 0x063C - Enable SMBus Enable/disable SMBus controller. $EN_DIS **/ UINT8 SmbusEnable; -/** Offset 0x0665 - Enable SMBus ARP support +/** Offset 0x063D - Enable SMBus ARP support Enable SMBus ARP support. $EN_DIS **/ UINT8 SmbusArpEnable; -/** Offset 0x0666 - Number of RsvdSmbusAddressTable. +/** Offset 0x063E - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x0667 - Reserved +/** Offset 0x063F - Reserved **/ - UINT8 Reserved56; + UINT8 Reserved45; -/** Offset 0x0668 - SMBUS Base Address +/** Offset 0x0640 - SMBUS Base Address SMBUS Base Address (IO space). **/ UINT16 PchSmbusIoBase; -/** Offset 0x066A - Enable SMBus Alert Pin +/** Offset 0x0642 - Enable SMBus Alert Pin Enable SMBus Alert Pin. $EN_DIS **/ UINT8 PchSmbAlertEnable; -/** Offset 0x066B - Reserved +/** Offset 0x0643 - Reserved **/ - UINT8 Reserved57[13]; + UINT8 Reserved46[13]; -/** Offset 0x0678 - Smbus dynamic power gating +/** Offset 0x0650 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. $EN_DIS **/ UINT8 SmbusDynamicPowerGating; -/** Offset 0x0679 - SMBUS SPD Write Disable +/** Offset 0x0651 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS **/ UINT8 SmbusSpdWriteDisable; -/** Offset 0x067A - Enable/Disable SA OcSupport +/** Offset 0x0652 - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport $EN_DIS **/ UINT8 SaOcSupport; -/** Offset 0x067B - Reserved +/** Offset 0x0653 - Reserved **/ - UINT8 Reserved58[18]; + UINT8 Reserved47[18]; -/** Offset 0x068D - Over clocking support +/** Offset 0x0665 - Over clocking support Over clocking support; 0: Disable; 1: Enable $EN_DIS **/ UINT8 OcSupport; -/** Offset 0x068E - Reserved +/** Offset 0x0666 - Reserved **/ - UINT8 Reserved59; + UINT8 Reserved48; -/** Offset 0x068F - Realtime Memory Timing +/** Offset 0x0667 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE. 0: Disabled, 1: Enabled **/ UINT8 RealtimeMemoryTiming; -/** Offset 0x0690 - core voltage override +/** Offset 0x0668 - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000 **/ UINT16 CoreVoltageOverride; -/** Offset 0x0692 - Core Turbo voltage Offset +/** Offset 0x066A - Core Turbo voltage Offset The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 **/ UINT16 CoreVoltageOffset; -/** Offset 0x0694 - Core PLL voltage offset +/** Offset 0x066C - Core PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 **/ UINT8 CorePllVoltageOffset; -/** Offset 0x0695 - AVX2 Ratio Offset +/** Offset 0x066D - AVX2 Ratio Offset 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. **/ UINT8 Avx2RatioOffset; -/** Offset 0x0696 - BCLK Adaptive Voltage Enable +/** Offset 0x066E - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable $EN_DIS **/ UINT8 BclkAdaptiveVoltage; -/** Offset 0x0697 - Ring Downbin +/** Offset 0x066F - Ring Downbin Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable. $EN_DIS **/ UINT8 RingDownBin; -/** Offset 0x0698 - Row Hammer pTRR LFSR0 Mask +/** Offset 0x0670 - Row Hammer pTRR LFSR0 Mask Row Hammer pTRR LFSR0 Mask, 1/2^(value) **/ UINT8 Lfsr0Mask; -/** Offset 0x0699 - Margin Limit Check +/** Offset 0x0671 - Margin Limit Check Margin Limit Check. Choose level of margin check 0:Disable, 1:L1, 2:L2, 3:Both **/ UINT8 MarginLimitCheck; -/** Offset 0x069A - Row Hammer pTRR LFSR1 Mask +/** Offset 0x0672 - Row Hammer pTRR LFSR1 Mask Row Hammer pTRR LFSR1 Mask, 1/2^(value) **/ UINT8 Lfsr1Mask; -/** Offset 0x069B - Reserved +/** Offset 0x0673 - Reserved **/ - UINT8 Reserved60[2]; + UINT8 Reserved49[2]; -/** Offset 0x069D - TjMax Offset +/** Offset 0x0675 - TjMax Offset TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 **/ UINT8 TjMaxOffset; -/** Offset 0x069E - Reserved +/** Offset 0x0676 - Reserved **/ - UINT8 Reserved61[48]; + UINT8 Reserved50[48]; -/** Offset 0x06CE - Core VF Point Offset +/** Offset 0x06A6 - Core VF Point Offset Array used to specifies the Core Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts. **/ UINT16 CoreVfPointOffset[15]; -/** Offset 0x06EC - Core VF Point Offset Prefix +/** Offset 0x06C4 - Core VF Point Offset Prefix Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative. 0:Positive, 1:Negative **/ UINT8 CoreVfPointOffsetPrefix[15]; -/** Offset 0x06FB - Core VF Point Ratio +/** Offset 0x06D3 - Core VF Point Ratio Array for the each selected Core VF Point to display the ration. **/ UINT8 CoreVfPointRatio[15]; -/** Offset 0x070A - Reserved +/** Offset 0x06E2 - Reserved **/ - UINT8 Reserved62[26]; + UINT8 Reserved51[26]; -/** Offset 0x0724 - Per Core Max Ratio override +/** Offset 0x06FC - Per Core Max Ratio override Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. 0: Disable, 1: enable $EN_DIS **/ UINT8 PerCoreRatioOverride; -/** Offset 0x0725 - Reserved +/** Offset 0x06FD - Reserved **/ - UINT8 Reserved63[25]; + UINT8 Reserved52[25]; -/** Offset 0x073E - Per Core Current Max Ratio +/** Offset 0x0716 - Per Core Current Max Ratio Array for the Per Core Max Ratio **/ UINT8 PerCoreRatio[8]; -/** Offset 0x0746 - Reserved +/** Offset 0x071E - Reserved **/ - UINT8 Reserved64[8]; + UINT8 Reserved53[8]; -/** Offset 0x074E - Pvd Ratio Threshold for SOC/CPU die +/** Offset 0x0726 - Pvd Ratio Threshold for SOC/CPU die Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range. As per the die selected, this threshold is applied to SA and MC/CMI PLL @@ -2113,63 +2077,63 @@ **/ UINT8 PvdRatioThreshold; -/** Offset 0x074F - Reserved +/** Offset 0x0727 - Reserved **/ - UINT8 Reserved65[65]; + UINT8 Reserved54[65]; -/** Offset 0x0790 - CPU BCLK OC Frequency +/** Offset 0x0768 - CPU BCLK OC Frequency CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is 40Mhz-1000Mhz. **/ UINT32 CpuBclkOcFrequency; -/** Offset 0x0794 - Reserved +/** Offset 0x076C - Reserved **/ - UINT8 Reserved66[13]; + UINT8 Reserved55[13]; -/** Offset 0x07A1 - Avx2 Voltage Guardband Scaling Factor +/** Offset 0x0779 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. **/ UINT8 Avx2VoltageScaleFactor; -/** Offset 0x07A2 - Ring PLL voltage offset +/** Offset 0x077A - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 **/ UINT8 RingPllVoltageOffset; -/** Offset 0x07A3 - Reserved +/** Offset 0x077B - Reserved **/ - UINT8 Reserved67[5]; + UINT8 Reserved56[5]; -/** Offset 0x07A8 - Enable PCH ISH Controller +/** Offset 0x0780 - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller $EN_DIS **/ UINT8 PchIshEnable; -/** Offset 0x07A9 - Reserved +/** Offset 0x0781 - Reserved **/ - UINT8 Reserved68; + UINT8 Reserved57; -/** Offset 0x07AA - BiosSize +/** Offset 0x0782 - BiosSize The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected Range) so that a BIOS Update Script can be stored in the DPR. **/ UINT16 BiosSize; -/** Offset 0x07AC - BiosGuard +/** Offset 0x0784 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS **/ UINT8 BiosGuard; -/** Offset 0x07AD +/** Offset 0x0785 **/ UINT8 BiosGuardToolsInterface; -/** Offset 0x07AE - Txt +/** Offset 0x0786 - Txt Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect. 0: Disable, 1: Enable @@ -2177,318 +2141,415 @@ **/ UINT8 Txt; -/** Offset 0x07AF - Skip Stop PBET Timer Enable/Disable +/** Offset 0x0787 - Skip Stop PBET Timer Enable/Disable Skip Stop PBET Timer; 0: Disable; 1: Enable $EN_DIS **/ UINT8 SkipStopPbet; -/** Offset 0x07B0 - Reserved +/** Offset 0x0788 - Reserved **/ - UINT8 Reserved69[38]; + UINT8 Reserved58[3]; -/** Offset 0x07D6 - BIST on Reset +/** Offset 0x078B - MKTME Key-Id Bits Override Enable + Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager + (VMM)/hypervisor 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 GenerateNewTmeKey; + +/** Offset 0x078C - Reserved +**/ + UINT8 Reserved59[4]; + +/** Offset 0x0790 - TME Exclude Base Address + TME Exclude Base Address. +**/ + UINT64 TmeExcludeBase; + +/** Offset 0x0798 - TME Exclude Size Value + TME Exclude Size Value. +**/ + UINT64 TmeExcludeSize; + +/** Offset 0x07A0 - Reserved +**/ + UINT8 Reserved60[14]; + +/** Offset 0x07AE - BIST on Reset Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 BistOnReset; -/** Offset 0x07D7 - Reserved +/** Offset 0x07AF - Reserved **/ - UINT8 Reserved70; + UINT8 Reserved61; -/** Offset 0x07D8 - Enable or Disable VMX +/** Offset 0x07B0 - Enable or Disable VMX Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x07D9 - Processor Early Power On Configuration FCLK setting +/** Offset 0x07B1 - Processor Early Power On Configuration FCLK setting FCLK frequency can take values of 400MHz, 800MHz and 1GHz. 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved **/ UINT8 FClkFrequency; -/** Offset 0x07DA - Enable CPU CrashLog +/** Offset 0x07B2 - Enable CPU CrashLog Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CpuCrashLogEnable; -/** Offset 0x07DB - Enable or Disable TME +/** Offset 0x07B3 - Enable or Disable TME Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TmeEnable; -/** Offset 0x07DC - CPU Run Control +/** Offset 0x07B4 - CPU Run Control Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: No Change 0:Disabled, 1:Enabled, 2:No Change **/ UINT8 DebugInterfaceEnable; -/** Offset 0x07DD - CPU Run Control Lock +/** Offset 0x07B5 - CPU Run Control Lock Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceLockEnable; -/** Offset 0x07DE - Enable CPU CrashLog GPRs dump +/** Offset 0x07B6 - Enable CPU CrashLog GPRs dump Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only disable Smm GPRs dump 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled **/ UINT8 CrashLogGprs; -/** Offset 0x07DF - Over clocking Lock +/** Offset 0x07B7 - Over clocking Lock Lock Overclocking. 0: Disable; 1: Enable $EN_DIS **/ UINT8 OcLock; -/** Offset 0x07E0 - CPU ratio value +/** Offset 0x07B8 - CPU ratio value This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio set by Hardware (HFM). Valid Range 0 to 63. **/ UINT8 CpuRatio; -/** Offset 0x07E1 - Number of active big cores +/** Offset 0x07B9 - Number of active big cores Number of P-cores to enable in each processor package. Note: Number of P-Cores and E-Cores are looked at together. When both are {0,0 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores **/ UINT8 ActiveCoreCount; -/** Offset 0x07E2 - Reserved +/** Offset 0x07BA - Reserved **/ - UINT8 Reserved71[6]; + UINT8 Reserved62[6]; -/** Offset 0x07E8 - PrmrrSize +/** Offset 0x07C0 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable **/ UINT32 PrmrrSize; -/** Offset 0x07EC - Tseg Size +/** Offset 0x07C4 - Tseg Size Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build 0x0400000:4MB, 0x01000000:16MB **/ UINT32 TsegSize; -/** Offset 0x07F0 - SmmRelocationEnable Enable +/** Offset 0x07C8 - SmmRelocationEnable Enable Enable or Disable SmmRelocationEnable. 0: Disable, 1:Enable $EN_DIS **/ UINT8 SmmRelocationEnable; -/** Offset 0x07F1 - TCC Activation Offset +/** Offset 0x07C9 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts. Default = 0h. **/ UINT8 TccActivationOffset; -/** Offset 0x07F2 - Reserved +/** Offset 0x07CA - Reserved **/ - UINT8 Reserved72[98]; + UINT8 Reserved63[98]; -/** Offset 0x0854 - SinitMemorySize +/** Offset 0x082C - SinitMemorySize Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable **/ UINT32 SinitMemorySize; -/** Offset 0x0858 - TxtDprMemoryBase +/** Offset 0x0830 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable **/ UINT64 TxtDprMemoryBase; -/** Offset 0x0860 - TxtHeapMemorySize +/** Offset 0x0838 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable **/ UINT32 TxtHeapMemorySize; -/** Offset 0x0864 - TxtDprMemorySize +/** Offset 0x083C - TxtDprMemorySize Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize , 1: enable **/ UINT32 TxtDprMemorySize; -/** Offset 0x0868 - TxtLcpPdBase +/** Offset 0x0840 - TxtLcpPdBase Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable **/ UINT64 TxtLcpPdBase; -/** Offset 0x0870 - TxtLcpPdSize +/** Offset 0x0848 - TxtLcpPdSize Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable **/ UINT64 TxtLcpPdSize; -/** Offset 0x0878 - BiosAcmBase +/** Offset 0x0850 - BiosAcmBase Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable **/ UINT64 BiosAcmBase; -/** Offset 0x0880 - BiosAcmSize +/** Offset 0x0858 - BiosAcmSize Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable **/ UINT32 BiosAcmSize; -/** Offset 0x0884 - ApStartupBase +/** Offset 0x085C - ApStartupBase Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable **/ UINT32 ApStartupBase; -/** Offset 0x0888 - TgaSize +/** Offset 0x0860 - TgaSize Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable **/ UINT32 TgaSize; -/** Offset 0x088C - IsTPMPresence +/** Offset 0x0864 - IsTPMPresence IsTPMPresence default values **/ UINT8 IsTPMPresence; -/** Offset 0x088D - Reserved +/** Offset 0x0865 - Acoustic Noise Mitigation feature + Enabling this option will help mitigate acoustic noise on certain SKUs when the + CPU is in deeper C state. 0: Disabled; 1: Enabled + $EN_DIS **/ - UINT8 Reserved73[157]; + UINT8 AcousticNoiseMitigation; -/** Offset 0x092A - Thermal Design Current enable/disable +/** Offset 0x0866 - Reserved +**/ + UINT8 Reserved64[2]; + +/** Offset 0x0868 - Platform Power Pmax + PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 + Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x086A - Reserved +**/ + UINT8 Reserved65[12]; + +/** Offset 0x0876 - AcLoadline + AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 AcLoadline[6]; + +/** Offset 0x0882 - DcLoadline + DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 DcLoadline[6]; + +/** Offset 0x088E - Reserved +**/ + UINT8 Reserved66[116]; + +/** Offset 0x0902 - Thermal Design Current enable/disable Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved. **/ UINT8 TdcEnable[6]; -/** Offset 0x0930 - Reserved +/** Offset 0x0908 - Reserved **/ - UINT8 Reserved74[24]; + UINT8 Reserved67[6]; -/** Offset 0x0948 - Thermal Design Current time window +/** Offset 0x090E - Disable Fast Slew Rate for Deep Package C States for VR domains + This option needs to be configured to reduce acoustic noise during deeper C states. + False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp + during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are + Reserved. 0: False; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[6]; + +/** Offset 0x0914 - Slew Rate configuration for Deep Package C States for VR domains + Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate + equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew + rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: + Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration +**/ + UINT8 SlowSlewRate[6]; + +/** Offset 0x091A - Reserved +**/ + UINT8 Reserved68[6]; + +/** Offset 0x0920 - Thermal Design Current time window Auto = 0 is default. Range is from 1ms to 448s. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved. **/ UINT32 TdcTimeWindow[6]; -/** Offset 0x0960 - Reserved +/** Offset 0x0938 - Reserved **/ - UINT8 Reserved75[8]; + UINT8 Reserved69[8]; -/** Offset 0x0968 - DLVR RFI Enable +/** Offset 0x0940 - DLVR RFI Enable Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DlvrRfiEnable; -/** Offset 0x0969 - Reserved +/** Offset 0x0941 - Reserved **/ - UINT8 Reserved76[25]; + UINT8 Reserved70[13]; -/** Offset 0x0982 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. +/** Offset 0x094E - VR Fast Vmode ICC Limit support + Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds + to feature disabled (no reactive protection). This value represents the current + threshold where the VR would initiate reactive protection if Fast Vmode is enabled. + The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccLimit[6]; + +/** Offset 0x095A - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. Enable/Disable VR FastVmode; 0: Disable; 1: Enable.For all VR by domain 0: Disable, 1: Enable **/ UINT8 EnableFastVmode[6]; -/** Offset 0x0988 - Reserved +/** Offset 0x0960 - Enable/Disable CEP + Control for enabling/disabling CEP (Current Excursion Protection). 0: Disable; 1: Enable + 0: Disable, 1: Enable **/ - UINT8 Reserved77[26]; + UINT8 CepEnable[6]; -/** Offset 0x09A2 - PCH Port80 Route +/** Offset 0x0966 - Reserved +**/ + UINT8 Reserved71[28]; + +/** Offset 0x0982 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. $EN_DIS **/ UINT8 PchPort80Route; -/** Offset 0x09A3 - GPIO Override +/** Offset 0x0983 - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use **/ UINT8 GpioOverride; -/** Offset 0x09A4 - Reserved +/** Offset 0x0984 - Reserved **/ - UINT8 Reserved78[4]; + UINT8 Reserved72[4]; -/** Offset 0x09A8 - PMR Size +/** Offset 0x0988 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot **/ UINT32 DmaBufferSize; -/** Offset 0x09AC - The policy for VTd driver behavior +/** Offset 0x098C - The policy for VTd driver behavior BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS **/ UINT8 PreBootDmaMask; -/** Offset 0x09AD - State of DMA_CONTROL_GUARANTEE bit in the DMAR table +/** Offset 0x098D - State of DMA_CONTROL_GUARANTEE bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 DmaControlGuarantee; -/** Offset 0x09AE - Disable VT-d +/** Offset 0x098E - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisable; -/** Offset 0x09AF - Reserved +/** Offset 0x098F - Reserved **/ - UINT8 Reserved79; + UINT8 Reserved73; -/** Offset 0x09B0 - Base addresses for VT-d function MMIO access +/** Offset 0x0990 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine **/ UINT32 VtdBaseAddress[9]; -/** Offset 0x09D4 - Reserved +/** Offset 0x09B4 - Reserved **/ - UINT8 Reserved80[20]; + UINT8 Reserved74[20]; -/** Offset 0x09E8 - MMIO Size +/** Offset 0x09C8 - MMIO Size Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB **/ UINT16 MmioSize; -/** Offset 0x09EA - MMIO size adjustment for AUTO mode +/** Offset 0x09CA - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size **/ UINT16 MmioSizeAdjustment; -/** Offset 0x09EC - Reserved +/** Offset 0x09CC - Reserved **/ - UINT8 Reserved81[36]; + UINT8 Reserved75[36]; -/** Offset 0x0A10 - Enable above 4GB MMIO resource support +/** Offset 0x09F0 - Enable above 4GB MMIO resource support Enable/disable above 4GB MMIO resource support $EN_DIS **/ UINT8 EnableAbove4GBMmio; -/** Offset 0x0A11 - Enable/Disable SA CRID +/** Offset 0x09F1 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS **/ UINT8 CridEnable; -/** Offset 0x0A12 - Reserved +/** Offset 0x09F2 - Reserved **/ - UINT8 Reserved82[10]; + UINT8 Reserved76[10]; -/** Offset 0x0A1C - Enable/Disable CrashLog Device +/** Offset 0x09FC - Enable/Disable CrashLog Device Enable or Disable CrashLog/Telemetry Device 0- Disable, 1- Enable $EN_DIS **/ UINT32 CpuCrashLogDevice; -/** Offset 0x0A20 - Reserved +/** Offset 0x0A00 - Reserved **/ - UINT8 Reserved83[20]; + UINT8 Reserved77[20]; -/** Offset 0x0A34 - Platform Debug Option +/** Offset 0x0A14 - Platform Debug Option Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n \n Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n @@ -2501,122 +2562,122 @@ **/ UINT8 PlatformDebugOption; -/** Offset 0x0A35 - Reserved +/** Offset 0x0A15 - Reserved **/ - UINT8 Reserved84[14]; + UINT8 Reserved78[14]; -/** Offset 0x0A43 - Program GPIOs for LFP on DDI port-A device +/** Offset 0x0A23 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortAConfig; -/** Offset 0x0A44 - Reserved +/** Offset 0x0A24 - Reserved **/ - UINT8 Reserved85[2]; + UINT8 Reserved79[2]; -/** Offset 0x0A46 - Program GPIOs for LFP on DDI port-B device +/** Offset 0x0A26 - Program GPIOs for LFP on DDI port-B device 0(Default)=Disabled,1=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortBConfig; -/** Offset 0x0A47 - Enable or disable HPD of DDI port A +/** Offset 0x0A27 - Enable or disable HPD of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortAHpd; -/** Offset 0x0A48 - Enable or disable HPD of DDI port B +/** Offset 0x0A28 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBHpd; -/** Offset 0x0A49 - Enable or disable HPD of DDI port C +/** Offset 0x0A29 - Enable or disable HPD of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCHpd; -/** Offset 0x0A4A - Enable or disable HPD of DDI port 1 +/** Offset 0x0A2A - Enable or disable HPD of DDI port 1 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPort1Hpd; -/** Offset 0x0A4B - Enable or disable HPD of DDI port 2 +/** Offset 0x0A2B - Enable or disable HPD of DDI port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Hpd; -/** Offset 0x0A4C - Enable or disable HPD of DDI port 3 +/** Offset 0x0A2C - Enable or disable HPD of DDI port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Hpd; -/** Offset 0x0A4D - Enable or disable HPD of DDI port 4 +/** Offset 0x0A2D - Enable or disable HPD of DDI port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Hpd; -/** Offset 0x0A4E - Enable or disable DDC of DDI port A +/** Offset 0x0A2E - Enable or disable DDC of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortADdc; -/** Offset 0x0A4F - Enable or disable DDC of DDI port B +/** Offset 0x0A2F - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBDdc; -/** Offset 0x0A50 - Enable or disable DDC of DDI port C +/** Offset 0x0A30 - Enable or disable DDC of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCDdc; -/** Offset 0x0A51 - Enable DDC setting of DDI Port 1 +/** Offset 0x0A31 - Enable DDC setting of DDI Port 1 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort1Ddc; -/** Offset 0x0A52 - Enable DDC setting of DDI Port 2 +/** Offset 0x0A32 - Enable DDC setting of DDI Port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Ddc; -/** Offset 0x0A53 - Enable DDC setting of DDI Port 3 +/** Offset 0x0A33 - Enable DDC setting of DDI Port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Ddc; -/** Offset 0x0A54 - Enable DDC setting of DDI Port 4 +/** Offset 0x0A34 - Enable DDC setting of DDI Port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Ddc; -/** Offset 0x0A55 - Reserved +/** Offset 0x0A35 - Reserved **/ - UINT8 Reserved86[3]; + UINT8 Reserved80[3]; -/** Offset 0x0A58 - Temporary MMIO address for GMADR +/** Offset 0x0A38 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1) **/ UINT64 LMemBar; -/** Offset 0x0A60 - Temporary MMIO address for GTTMMADR +/** Offset 0x0A40 - Temporary MMIO address for GTTMMADR The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO @@ -2624,104 +2685,164 @@ **/ UINT64 GttMmAdr; -/** Offset 0x0A68 - Reserved +/** Offset 0x0A48 - Reserved **/ - UINT8 Reserved87[2]; + UINT8 Reserved81[2]; -/** Offset 0x0A6A - Enable/Disable Memory Bandwidth Compression +/** Offset 0x0A4A - Enable/Disable Memory Bandwidth Compression 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 MemoryBandwidthCompression; -/** Offset 0x0A6B - Panel Power Enable +/** Offset 0x0A4B - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 PanelPowerEnable; -/** Offset 0x0A6C - Selection of the primary display device +/** Offset 0x0A4C - Selection of the primary display device 3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics 3:AUTO, 0:IGFX, 4:HG **/ UINT8 PrimaryDisplay; -/** Offset 0x0A6D - TCSS USB HOST (xHCI) Enable +/** Offset 0x0A4D - Internal Graphics Data Stolen Memory GSM2 + Size of memory preallocated for internal graphics GSM2. + 0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB, + 11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation +**/ + UINT8 IGpuGsm2Size; + +/** Offset 0x0A4E - Reserved +**/ + UINT8 Reserved82[2]; + +/** Offset 0x0A50 - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0A54 - Reserved +**/ + UINT8 Reserved83[4]; + +/** Offset 0x0A58 - Graphics Configuration Ptr + Points to VBT +**/ + UINT64 VbtPtr; + +/** Offset 0x0A60 - SOL Training Message Pointer + Points to SOL Message String +**/ + UINT64 VgaMessage; + +/** Offset 0x0A68 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0A69 - Control SOL VGA Initialition sequence + Initialise SOL Init + 0x0: NO SOL VGA Init, 0x1: SOL VGA Init +**/ + UINT8 VgaInitControl; + +/** Offset 0x0A6A - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below $EN_DIS **/ UINT8 TcssXhciEn; -/** Offset 0x0A6E - Reserved +/** Offset 0x0A6B - Reserved **/ - UINT8 Reserved88[4]; + UINT8 Reserved84[4]; -/** Offset 0x0A72 - TCSS Type C Port 0 +/** Offset 0x0A6F - TCSS Type C Port 0 Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN **/ UINT8 TcssPort0; -/** Offset 0x0A73 - TCSS Type C Port 1 +/** Offset 0x0A70 - TCSS Type C Port 1 Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN **/ UINT8 TcssPort1; -/** Offset 0x0A74 - TCSS Type C Port 2 +/** Offset 0x0A71 - TCSS Type C Port 2 Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN **/ UINT8 TcssPort2; -/** Offset 0x0A75 - TCSS Type C Port 3 +/** Offset 0x0A72 - TCSS Type C Port 3 Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN **/ UINT8 TcssPort3; -/** Offset 0x0A76 - Reserved +/** Offset 0x0A73 - Reserved **/ - UINT8 Reserved89[2]; + UINT8 Reserved85; -/** Offset 0x0A78 - TypeC port GPIO setting +/** Offset 0x0A74 - TypeC port GPIO setting GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake) **/ UINT32 IomTypeCPortPadCfg[12]; -/** Offset 0x0AA8 - TCSS Aux Orientation Override Enable +/** Offset 0x0AA4 - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x0AAA - TCSS HSL Orientation Override Enable +/** Offset 0x0AA6 - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x0AAC - CNVi DDR RFI Mitigation +/** Offset 0x0AA8 - CNVi DDR RFI Mitigation Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviDdrRfim; -/** Offset 0x0AAD - SOC Trace Hub Mode +/** Offset 0x0AA9 - SOC Trace Hub Mode Enable/Disable SOC TraceHub $EN_DIS **/ UINT8 SocTraceHubMode; -/** Offset 0x0AAE - Reserved +/** Offset 0x0AAA - SOC Trace Hub Memory Region 0 buffer Size + Select size of memory region 0 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB **/ - UINT8 Reserved90[4]; + UINT16 SocTraceHubMemReg0Size; -/** Offset 0x0AB2 - Internal Graphics Pre-allocated Memory +/** Offset 0x0AAC - SOC Trace Hub Memory Region 0 buffer Size + Select size of memory region 1 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg1Size; + +/** Offset 0x0AAE - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, @@ -2729,175 +2850,175 @@ **/ UINT16 IgdDvmt50PreAlloc; -/** Offset 0x0AB4 - Internal Graphics +/** Offset 0x0AB0 - Internal Graphics Enable/disable internal graphics. $EN_DIS **/ UINT8 InternalGraphics; -/** Offset 0x0AB5 - Reserved +/** Offset 0x0AB1 - Reserved **/ - UINT8 Reserved91[7]; + UINT8 Reserved86[7]; -/** Offset 0x0ABC - DynamicMemoryBoost +/** Offset 0x0AB8 - DynamicMemoryBoost Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled. $EN_DIS **/ UINT32 DynamicMemoryBoost; -/** Offset 0x0AC0 - RealtimeMemoryFrequency +/** Offset 0x0ABC - RealtimeMemoryFrequency Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled. $EN_DIS **/ UINT32 RealtimeMemoryFrequency; -/** Offset 0x0AC4 - Reserved +/** Offset 0x0AC0 - Reserved **/ - UINT8 Reserved92[9]; + UINT8 Reserved87[9]; -/** Offset 0x0ACD - Vref Offset +/** Offset 0x0AC9 - Vref Offset Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset 0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6 **/ UINT8 VrefOffset; -/** Offset 0x0ACE - Reserved +/** Offset 0x0ACA - Reserved **/ - UINT8 Reserved93[2]; + UINT8 Reserved88[2]; -/** Offset 0x0AD0 - tRRSG Delta +/** Offset 0x0ACC - tRRSG Delta Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRRSG; -/** Offset 0x0AD1 - tRRDG Delta +/** Offset 0x0ACD - tRRDG Delta Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRRDG; -/** Offset 0x0AD2 - tRRDR Delta +/** Offset 0x0ACE - tRRDR Delta Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRRDR; -/** Offset 0x0AD3 - tRRDD Delta +/** Offset 0x0ACF - tRRDD Delta Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRRDD; -/** Offset 0x0AD4 - tWRSG Delta +/** Offset 0x0AD0 - tWRSG Delta Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWRSG; -/** Offset 0x0AD5 - tWRDG Delta +/** Offset 0x0AD1 - tWRDG Delta Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWRDG; -/** Offset 0x0AD6 - tWRDR Delta +/** Offset 0x0AD2 - tWRDR Delta Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWRDR; -/** Offset 0x0AD7 - tWRDD Delta +/** Offset 0x0AD3 - tWRDD Delta Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWRDD; -/** Offset 0x0AD8 - tWWSG Delta +/** Offset 0x0AD4 - tWWSG Delta Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWWSG; -/** Offset 0x0AD9 - tWWDG Delta +/** Offset 0x0AD5 - tWWDG Delta Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWWDG; -/** Offset 0x0ADA - tWWDR Delta +/** Offset 0x0AD6 - tWWDR Delta Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWWDR; -/** Offset 0x0ADB - tWWDD Delta +/** Offset 0x0AD7 - tWWDD Delta Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tWWDD; -/** Offset 0x0ADC - tRWSG Delta +/** Offset 0x0AD8 - tRWSG Delta Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRWSG; -/** Offset 0x0ADD - tRWDG Delta +/** Offset 0x0AD9 - tRWDG Delta Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRWDG; -/** Offset 0x0ADE - tRWDR Delta +/** Offset 0x0ADA - tRWDR Delta Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRWDR; -/** Offset 0x0ADF - tRWDD Delta +/** Offset 0x0ADB - tRWDD Delta Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127] **/ UINT8 tRWDD; -/** Offset 0x0AE0 - Reserved +/** Offset 0x0ADC - Reserved **/ - UINT8 Reserved94[13]; + UINT8 Reserved89[13]; -/** Offset 0x0AED - PPR ForceRepair +/** Offset 0x0AE9 - PPR ForceRepair When Eanble, PPR will force repair some rows many times (90) $EN_DIS **/ UINT8 PprForceRepair; -/** Offset 0x0AEE - PPR Repair Bank +/** Offset 0x0AEA - PPR Repair Bank PPR repair Bank: User chooses to force repair specifc address **/ UINT8 PprRepairBank; -/** Offset 0x0AEF - Reserved +/** Offset 0x0AEB - Reserved **/ - UINT8 Reserved95[33]; + UINT8 Reserved90[53]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2916,11 +3037,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0B10 +/** Offset 0x0B20 **/ - UINT8 UnusedUpdSpace56[6]; + UINT8 UnusedUpdSpace0[6]; -/** Offset 0x0B16 +/** Offset 0x0B26 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h index 1b81588..31911f8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2024, Intel Corporation. All rights reserved. +Copyright (c) 2025, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -255,38 +255,31 @@ **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x00DC - Enable or Disable Enhanced C-states - Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores - enter C-State. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x00DD - Enable or Disable Package Cstate Demotion +/** Offset 0x00DC - Enable or Disable Package Cstate Demotion Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x00DE - Enable or Disable Package Cstate UnDemotion +/** Offset 0x00DD - Enable or Disable Package Cstate UnDemotion Enable or Disable Package C-State Un-Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x00DF - Enable or Disable CState-Pre wake +/** Offset 0x00DE - Enable or Disable CState-Pre wake Disable - to disable the Cstate Pre-Wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x00E0 - Enable or Disable TimedMwait Support. +/** Offset 0x00DF - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x00E1 - Set the Max Pkg Cstate +/** Offset 0x00E0 - Set the Max Pkg Cstate Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. Auto: Initializes to deepest available Package C State Limit. Valid values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 - @@ -294,49 +287,49 @@ **/ UINT8 PkgCStateLimit; -/** Offset 0x00E2 - Reserved +/** Offset 0x00E1 - Reserved **/ UINT8 Reserved5[2]; -/** Offset 0x00E4 - Interrupt Redirection Mode Select +/** Offset 0x00E3 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1: Round robin; 2: Hash vector; 7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x00E5 - Turbo Mode +/** Offset 0x00E4 - Turbo Mode Enable/Disable processor Turbo Mode. 0:disable, 1: Enable $EN_DIS **/ UINT8 TurboMode; -/** Offset 0x00E6 - Reserved +/** Offset 0x00E5 - Reserved **/ UINT8 Reserved6; -/** Offset 0x00E7 - P-state ratios for custom P-state table +/** Offset 0x00E6 - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x010F - Custom Ratio State Entries +/** Offset 0x010E - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table. Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x0110 - Max P-State Ratio +/** Offset 0x010F - Max P-State Ratio Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x0111 - Reserved +/** Offset 0x0110 - Reserved **/ UINT8 Reserved7; -/** Offset 0x0112 - Turbo settings Lock +/** Offset 0x0111 - Turbo settings Lock Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register. 0: Disable; 1: Enable @@ -344,11 +337,11 @@ **/ UINT8 TurboPowerLimitLock; -/** Offset 0x0113 - Reserved +/** Offset 0x0112 - Reserved **/ UINT8 Reserved8[33]; -/** Offset 0x0134 - Race To Halt +/** Offset 0x0133 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. 0: Disable; 1: Enable @@ -356,35 +349,35 @@ **/ UINT8 RaceToHalt; -/** Offset 0x0135 - Enable or Disable C1 Cstate Demotion +/** Offset 0x0134 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x0136 - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x0135 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate Un-Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x0137 - Minimum Ring ratio limit override +/** Offset 0x0136 - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x0138 - Maximum Ring ratio limit override +/** Offset 0x0137 - Maximum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x0139 - Reserved +/** Offset 0x0138 - Reserved **/ UINT8 Reserved9; -/** Offset 0x013A - Enable or Disable HWP +/** Offset 0x0139 - Enable or Disable HWP Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; 1: Enable; @@ -392,20 +385,20 @@ **/ UINT8 Hwp; -/** Offset 0x013B - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x013A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x013C - Enable or Disable HwP Autonomous Per Core P State OS control +/** Offset 0x013B - Enable or Disable HwP Autonomous Per Core P State OS control Disable Autonomous PCPS Autonomous will request the same value for all cores all the time. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoPerCorePstate; -/** Offset 0x013D - Enable or Disable HwP Autonomous EPP Grouping +/** Offset 0x013C - Enable or Disable HwP Autonomous EPP Grouping Enable EPP grouping Autonomous will request the same values for all cores with same EPP. Disable EPP grouping autonomous will not necessarily request same values for all cores with same EPP. 0: Disable; 1: Enable @@ -413,68 +406,72 @@ **/ UINT8 EnableHwpAutoEppGrouping; -/** Offset 0x013E - Reserved +/** Offset 0x013D - Reserved **/ UINT8 Reserved10[4]; -/** Offset 0x0142 - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x0141 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x0143 - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x0142 - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x0144 - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x0143 - Enable or Disable Monitor /MWAIT instructions Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner should not set in MWAIT Loop. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0145 - Enable or Disable initialization of machine check registers +/** Offset 0x0144 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x0146 - Control on Processor Trace output scheme +/** Offset 0x0145 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x0147 - Enable or Disable Processor Trace feature +/** Offset 0x0146 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x0148 - Reserved +/** Offset 0x0147 - Reserved **/ UINT8 Reserved11[3]; -/** Offset 0x014B - UFS enable/disable +/** Offset 0x014A - UFS enable/disable Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller 0 and (0,1) to enable controller 1 $EN_DIS **/ UINT8 UfsEnable[2]; -/** Offset 0x014D - Reserved +/** Offset 0x014C - Reserved **/ UINT8 Reserved12[2]; -/** Offset 0x014F - Enable/Disable PCIe tunneling for USB4 +/** Offset 0x014E - Enable/Disable PCIe tunneling for USB4 Enable/Disable PCIe tunneling for USB4, default is enable $EN_DIS **/ UINT8 ITbtPcieTunnelingForUsb4; +/** Offset 0x014F - Reserved +**/ + UINT8 Reserved13; + /** Offset 0x0150 - ITBTForcePowerOn Timeout value ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. 100 = 100 ms. @@ -492,9 +489,14 @@ **/ UINT16 ITbtDmaLtr[2]; -/** Offset 0x0158 - Reserved +/** Offset 0x0158 - ITbt Usb4CmMode value + ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM **/ - UINT8 Reserved13[16]; + UINT8 Usb4CmMode; + +/** Offset 0x0159 - Reserved +**/ + UINT8 Reserved14[15]; /** Offset 0x0168 - IEH Mode Integrated Error Handler Mode, 0: Bypass, 1: Enable @@ -553,7 +555,7 @@ /** Offset 0x0173 - Reserved **/ - UINT8 Reserved14; + UINT8 Reserved15; /** Offset 0x0174 - ISH GP GPIO Pin Muxing Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER @@ -738,7 +740,7 @@ /** Offset 0x0254 - Reserved **/ - UINT8 Reserved15; + UINT8 Reserved16; /** Offset 0x0255 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -770,7 +772,16 @@ /** Offset 0x0259 - Reserved **/ - UINT8 Reserved16[27]; + UINT8 Reserved17[22]; + +/** Offset 0x026F - Enable PCH ISH I3C pins assigned + Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI3cEnable[2]; + +/** Offset 0x0271 - Reserved +**/ + UINT8 Reserved18[3]; /** Offset 0x0274 - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will @@ -825,9 +836,11 @@ **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x027F - Reserved +/** Offset 0x027F - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS **/ - UINT8 Reserved17; + UINT8 PchPmWoWlanEnable; /** Offset 0x0280 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. @@ -953,7 +966,7 @@ /** Offset 0x0294 - Reserved **/ - UINT8 Reserved18; + UINT8 Reserved19; /** Offset 0x0295 - PMC C10 dynamic threshold dajustment enable Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs @@ -1124,7 +1137,7 @@ /** Offset 0x0534 - Reserved **/ - UINT8 Reserved19[28]; + UINT8 Reserved20[28]; /** Offset 0x0550 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). @@ -1150,7 +1163,7 @@ /** Offset 0x05B0 - Reserved **/ - UINT8 Reserved20[1525]; + UINT8 Reserved21[1525]; /** Offset 0x0BA5 - PCIE RP Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. @@ -1180,7 +1193,7 @@ /** Offset 0x0BBF - Reserved **/ - UINT8 Reserved21[12]; + UINT8 Reserved22[12]; /** Offset 0x0BCB - PCIe RootPort Power Gating Describes whether the PCI Express Power Gating for each root port is enabled by @@ -1191,7 +1204,7 @@ /** Offset 0x0BD7 - Reserved **/ - UINT8 Reserved22[49]; + UINT8 Reserved23[49]; /** Offset 0x0C08 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -1257,7 +1270,7 @@ /** Offset 0x0D86 - Reserved **/ - UINT8 Reserved23[114]; + UINT8 Reserved24[114]; /** Offset 0x0DF8 - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available @@ -1267,7 +1280,7 @@ /** Offset 0x0DFF - Reserved **/ - UINT8 Reserved24[85]; + UINT8 Reserved25[85]; /** Offset 0x0E54 - SPIn Default Chip Select Mode HW/SW Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, @@ -1290,7 +1303,7 @@ /** Offset 0x0E69 - Reserved **/ - UINT8 Reserved25[3]; + UINT8 Reserved26[3]; /** Offset 0x0E6C - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 @@ -1330,7 +1343,7 @@ /** Offset 0x0EB2 - Reserved **/ - UINT8 Reserved26[2]; + UINT8 Reserved27[2]; /** Offset 0x0EB4 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* @@ -1356,777 +1369,801 @@ **/ UINT8 SerialIoUartDbg2[7]; -/** Offset 0x0F0F - I2Cn Device Mode +/** Offset 0x0F0F - Reserved +**/ + UINT8 Reserved28[7]; + +/** Offset 0x0F16 - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[8]; -/** Offset 0x0F17 - Reserved +/** Offset 0x0F1E - Reserved **/ - UINT8 Reserved27; + UINT8 Reserved29[2]; -/** Offset 0x0F18 - Serial IO I2C SDA Pin Muxing +/** Offset 0x0F20 - Serial IO I2C SDA Pin Muxing Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values. **/ UINT32 PchSerialIoI2cSdaPinMux[8]; -/** Offset 0x0F38 - Serial IO I2C SCL Pin Muxing +/** Offset 0x0F40 - Serial IO I2C SCL Pin Muxing Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values. **/ UINT32 PchSerialIoI2cSclPinMux[8]; -/** Offset 0x0F58 - PCH SerialIo I2C Pads Termination +/** Offset 0x0F60 - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. **/ UINT8 PchSerialIoI2cPadsTermination[8]; -/** Offset 0x0F60 - Reserved +/** Offset 0x0F68 - I3C Device Mode + Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci, + 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling) **/ - UINT8 Reserved28[148]; + UINT8 SerialIoI3cMode[3]; -/** Offset 0x0FF4 - TypeC port GPIO setting +/** Offset 0x0F6B - Reserved +**/ + UINT8 Reserved30[79]; + +/** Offset 0x0FBA - VMD Port Device + VMD Root port device number. +**/ + UINT8 VmdPortDev[31]; + +/** Offset 0x0FD9 - VMD Port Func + VMD Root port function number. +**/ + UINT8 VmdPortFunc[31]; + +/** Offset 0x0FF8 - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x0FF9 - Reserved +**/ + UINT8 Reserved31[3]; + +/** Offset 0x0FFC - TypeC port GPIO setting GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl = LunarLake) **/ UINT32 IomTypeCPortPadCfg[12]; -/** Offset 0x1024 - CPU USB3 Port Over Current Pin +/** Offset 0x102C - CPU USB3 Port Over Current Pin Describe the specific over current pin number of USBC Port N. **/ UINT8 CpuUsb3OverCurrentPin[10]; -/** Offset 0x102E - Enable D3 Cold in TCSS +/** Offset 0x1036 - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM $EN_DIS **/ UINT8 D3ColdEnable; -/** Offset 0x102F - TC State in TCSS +/** Offset 0x1037 - TC State in TCSS This TC C-State Limit in IOM **/ UINT8 TcCstateLimit; -/** Offset 0x1030 - Reserved +/** Offset 0x1038 - Reserved **/ - UINT8 Reserved29[2]; + UINT8 Reserved32[2]; -/** Offset 0x1032 - Enable/Disable PMC-PD Solution +/** Offset 0x103A - Enable/Disable PMC-PD Solution This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution $EN_DIS **/ UINT8 PmcPdEnable; -/** Offset 0x1033 - Reserved +/** Offset 0x103B - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved33; -/** Offset 0x1034 - TCSS Aux Orientation Override Enable +/** Offset 0x103C - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x1036 - TCSS HSL Orientation Override Enable +/** Offset 0x103E - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x1038 - TCSS USB Port Enable +/** Offset 0x1040 - TCSS USB Port Enable Bits 0, 1, ... max Type C port control enables **/ UINT8 UsbTcPortEn; -/** Offset 0x1039 - VCCST request for IOM +/** Offset 0x1041 - VCCST request for IOM This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 $EN_DIS **/ UINT8 VccSt; -/** Offset 0x103A - Enable/Disable PTM +/** Offset 0x1042 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports $EN_DIS **/ UINT8 PtmEnabled[4]; -/** Offset 0x103E - PCIE RP Ltr Enable +/** Offset 0x1046 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 SaPcieItbtRpLtrEnable[4]; -/** Offset 0x1042 - PCIE RP Snoop Latency Override Mode +/** Offset 0x104A - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; -/** Offset 0x1046 - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x104E - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x104A - PCIE RP Snoop Latency Override Value +/** Offset 0x1052 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; -/** Offset 0x1052 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x105A - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; -/** Offset 0x1056 - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x105E - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x105A - PCIE RP Non Snoop Latency Override Value +/** Offset 0x1062 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; -/** Offset 0x1062 - Force LTR Override +/** Offset 0x106A - Force LTR Override Force LTR Override. **/ UINT8 SaPcieItbtRpForceLtrOverride[4]; -/** Offset 0x1066 - PCIE RP Ltr Config Lock +/** Offset 0x106E - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 SaPcieItbtRpLtrConfigLock[4]; -/** Offset 0x106A - Reserved +/** Offset 0x1072 - Reserved **/ - UINT8 Reserved31[4]; + UINT8 Reserved34[4]; -/** Offset 0x106E - Touch Host Controller Assignment +/** Offset 0x1076 - Touch Host Controller Assignment Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcAssignment[2]; -/** Offset 0x1070 - Touch Host Controller Interrupt Pin Mux +/** Offset 0x1078 - Touch Host Controller Interrupt Pin Mux Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. **/ UINT8 ThcInterruptPinMuxing[8]; -/** Offset 0x1078 - Touch Host Controller Mode +/** Offset 0x1080 - Touch Host Controller Mode Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid **/ UINT8 ThcMode[2]; -/** Offset 0x107A - Touch Host Controller Wake On Touch +/** Offset 0x1082 - Touch Host Controller Wake On Touch Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI **/ UINT8 ThcWakeOnTouch[2]; -/** Offset 0x107C - Reserved +/** Offset 0x1084 - Reserved **/ - UINT8 Reserved32[337]; + UINT8 Reserved35[337]; -/** Offset 0x11CD - PCHHOT# pin +/** Offset 0x11D5 - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ UINT8 PchHotEnable; -/** Offset 0x11CE - Thermal Throttling Custimized T0Level Value +/** Offset 0x11D6 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x11D0 - Thermal Throttling Custimized T1Level Value +/** Offset 0x11D8 - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x11D2 - Thermal Throttling Custimized T2Level Value +/** Offset 0x11DA - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x11D4 - Enable The Thermal Throttle +/** Offset 0x11DC - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x11D5 - PMSync State 13 +/** Offset 0x11DD - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x11D6 - Thermal Throttle Lock +/** Offset 0x11DE - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x11D7 - Thermal Throttling Suggested Setting +/** Offset 0x11DF - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x11D8 - Thermal Device Temperature +/** Offset 0x11E0 - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x11DA +/** Offset 0x11E2 **/ UINT8 PchTsnEnable[4]; -/** Offset 0x11DE - Enable TSN Multi-VC - Enable/disable Multi Virtual Channels(VC) in TSN. - $EN_DIS +/** Offset 0x11E6 - Reserved **/ - UINT8 PchTsnMultiVcEnable; + UINT8 Reserved36[34]; -/** Offset 0x11DF - Reserved -**/ - UINT8 Reserved33[33]; - -/** Offset 0x1200 - Enable USB2 ports +/** Offset 0x1208 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x1210 - Enable USB3 ports +/** Offset 0x1218 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x121A - Enable xDCI controller +/** Offset 0x1222 - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x121B - USB PDO Programming +/** Offset 0x1223 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable $EN_DIS **/ UINT8 UsbPdoProgramming; -/** Offset 0x121C - Reserved +/** Offset 0x1224 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved37; -/** Offset 0x121D - PCH USB OverCurrent mapping enable +/** Offset 0x1225 - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS **/ UINT8 PchUsbOverCurrentEnable; -/** Offset 0x121E - USB2 Port Over Current Pin +/** Offset 0x1226 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x122E - USB3 Port Over Current Pin +/** Offset 0x1236 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x1238 - Enable xHCI LTR override +/** Offset 0x1240 - Enable xHCI LTR override Enables override of recommended LTR values for xHCI $EN_DIS **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x1239 - Reserved +/** Offset 0x1241 - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved38[3]; -/** Offset 0x123C - xHCI High Idle Time LTR override +/** Offset 0x1244 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting **/ UINT32 PchUsbLtrHighIdleTimeOverride; -/** Offset 0x1240 - xHCI Medium Idle Time LTR override +/** Offset 0x1248 - xHCI Medium Idle Time LTR override Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting **/ UINT32 PchUsbLtrMediumIdleTimeOverride; -/** Offset 0x1244 - xHCI Low Idle Time LTR override +/** Offset 0x124C - xHCI Low Idle Time LTR override Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting **/ UINT32 PchUsbLtrLowIdleTimeOverride; -/** Offset 0x1248 - USB2 Port Reset Message Enable +/** Offset 0x1250 - USB2 Port Reset Message Enable 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must be enable for USB2 Port those are paired with CPU XHCI Port **/ UINT8 PortResetMessageEnable[16]; -/** Offset 0x1258 - PCH USB OverCurrent mapping lock enable +/** Offset 0x1260 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x1259 - USB Per Port HS Preemphasis Bias +/** Offset 0x1261 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2PhyPetxiset[16]; -/** Offset 0x1269 - USB Per Port HS Transmitter Bias +/** Offset 0x1271 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2PhyTxiset[16]; -/** Offset 0x1279 - USB Per Port HS Transmitter Emphasis +/** Offset 0x1281 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2PhyPredeemp[16]; -/** Offset 0x1289 - USB Per Port Half Bit Pre-emphasis +/** Offset 0x1291 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2PhyPehalfbit[16]; -/** Offset 0x1299 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x12A1 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x12A3 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x12AB - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x12AD - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x12B5 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x12B7 - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x12BF - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x12C1 +/** Offset 0x12C9 **/ UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; -/** Offset 0x12CB +/** Offset 0x12D3 **/ UINT8 PchUsb3HsioFilterSelNEnable[10]; -/** Offset 0x12D5 +/** Offset 0x12DD **/ UINT8 PchUsb3HsioFilterSelPEnable[10]; -/** Offset 0x12DF +/** Offset 0x12E7 **/ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; -/** Offset 0x12E9 +/** Offset 0x12F1 **/ UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; -/** Offset 0x12F3 +/** Offset 0x12FB **/ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; -/** Offset 0x12FD +/** Offset 0x1305 **/ UINT8 PchUsb3HsioFilterSelN[10]; -/** Offset 0x1307 +/** Offset 0x130F **/ UINT8 PchUsb3HsioFilterSelP[10]; -/** Offset 0x1311 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 +/** Offset 0x1319 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTranEnable[10]; -/** Offset 0x131B - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 +/** Offset 0x1323 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTran[10]; -/** Offset 0x1325 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 +/** Offset 0x132D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTranEnable[10]; -/** Offset 0x132F - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 +/** Offset 0x1337 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTran[10]; -/** Offset 0x1339 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 +/** Offset 0x1341 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTranEnable[10]; -/** Offset 0x1343 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 +/** Offset 0x134B - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTran[10]; -/** Offset 0x134D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 +/** Offset 0x1355 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTranEnable[10]; -/** Offset 0x1357 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 +/** Offset 0x135F - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTran[10]; -/** Offset 0x1361 - Reserved +/** Offset 0x1369 - Reserved **/ - UINT8 Reserved36[4]; + UINT8 Reserved39[4]; -/** Offset 0x1365 - Enable/Disable NPU Device +/** Offset 0x136D - Enable/Disable NPU Device Enable(Default): Enable NPU Device, Disable: Disable NPU Device $EN_DIS **/ UINT8 NpuEnable; -/** Offset 0x1366 - Enable LAN +/** Offset 0x136E - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x1367 - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x136F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x1368 - Reserved +/** Offset 0x1370 - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved40; -/** Offset 0x1369 - Skip Ssid Programming. +/** Offset 0x1371 - Skip Ssid Programming. When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly. $EN_DIS **/ UINT8 SiSkipSsidProgramming; -/** Offset 0x136A - Change Default SVID +/** Offset 0x1372 - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSvid; -/** Offset 0x136C - Change Default SSID +/** Offset 0x1374 - Change Default SSID Change the default SSID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSsid; -/** Offset 0x136E - Reserved +/** Offset 0x1376 - Reserved **/ - UINT8 Reserved38[2]; + UINT8 Reserved41[2]; -/** Offset 0x1370 - SVID SDID table Poniter. +/** Offset 0x1378 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE. **/ UINT64 SiSsidTablePtr; -/** Offset 0x1378 - Number of ssid table. +/** Offset 0x1380 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x137A - Reserved +/** Offset 0x1382 - Reserved **/ - UINT8 Reserved39[10]; + UINT8 Reserved42[10]; -/** Offset 0x1384 - LogoPixelHeight Address +/** Offset 0x138C - LogoPixelHeight Address Address of LogoPixelHeight **/ UINT32 LogoPixelHeight; -/** Offset 0x1388 - LogoPixelWidth Address +/** Offset 0x1390 - LogoPixelWidth Address Address of LogoPixelWidth **/ UINT32 LogoPixelWidth; -/** Offset 0x138C - Reserved +/** Offset 0x1394 - Reserved **/ - UINT8 Reserved40[4]; + UINT8 Reserved43[4]; -/** Offset 0x1390 - Blt Buffer Address +/** Offset 0x1398 - Blt Buffer Address Address of Blt buffer **/ UINT64 BltBufferAddress; -/** Offset 0x1398 - Graphics Configuration Ptr +/** Offset 0x13A0 - Graphics Configuration Ptr Points to VBT **/ UINT64 GraphicsConfigPtr; -/** Offset 0x13A0 - Enable/Disable SkipFspGop +/** Offset 0x13A8 - Enable/Disable SkipFspGop Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver $EN_DIS **/ UINT8 SkipFspGop; -/** Offset 0x13A1 - Reserved +/** Offset 0x13A9 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved44; -/** Offset 0x13A2 - Enable/Disable IGFX RenderStandby +/** Offset 0x13AA - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x13A3 - Reserved +/** Offset 0x13AB - Reserved **/ - UINT8 Reserved42[3]; + UINT8 Reserved45[3]; -/** Offset 0x13A6 - Enable/Disable PavpEnable +/** Offset 0x13AE - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS **/ UINT8 PavpEnable; -/** Offset 0x13A7 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x13AF - Enable/Disable PeiGraphicsPeimInit Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x13A8 - Reserved +/** Offset 0x13B0 - Reserved **/ - UINT8 Reserved43[4]; + UINT8 Reserved46[4]; -/** Offset 0x13AC - Intel Graphics VBT (Video BIOS Table) Size +/** Offset 0x13B4 - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image **/ UINT32 VbtSize; -/** Offset 0x13B0 - Platform LID Status for LFP Displays. +/** Offset 0x13B8 - Platform LID Status for LFP Displays. LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. 0: LidClosed, 1: LidOpen **/ UINT8 LidStatus; -/** Offset 0x13B1 - Reserved +/** Offset 0x13B9 - Reserved **/ - UINT8 Reserved44[11]; + UINT8 Reserved47[11]; -/** Offset 0x13BC - Address of PCH_DEVICE_INTERRUPT_CONFIG table. +/** Offset 0x13C4 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. **/ UINT32 DevIntConfigPtr; -/** Offset 0x13C0 - Number of DevIntConfig Entry +/** Offset 0x13C8 - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. **/ UINT8 NumOfDevIntConfig; -/** Offset 0x13C1 - Select GPIO IRQ Route +/** Offset 0x13C9 - Select GPIO IRQ Route GPIO IRQ Select. The valid value is 14 or 15. **/ UINT8 GpioIrqRoute; -/** Offset 0x13C2 - Select SciIrqSelect +/** Offset 0x13CA - Select SciIrqSelect SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. **/ UINT8 SciIrqSelect; -/** Offset 0x13C3 - Select TcoIrqSelect +/** Offset 0x13CB - Select TcoIrqSelect TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. **/ UINT8 TcoIrqSelect; -/** Offset 0x13C4 - Enable/Disable Tco IRQ +/** Offset 0x13CC - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS **/ UINT8 TcoIrqEnable; -/** Offset 0x13C5 - Reserved +/** Offset 0x13CD - Reserved **/ - UINT8 Reserved45[5]; + UINT8 Reserved48[5]; -/** Offset 0x13CA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states +/** Offset 0x13D2 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtV1p05RailEnabledStates; -/** Offset 0x13CB - Mask to enable the platform configuration of external V1p05 VR rail +/** Offset 0x13D3 - Mask to enable the platform configuration of external V1p05 VR rail External V1P05 Rail Supported Configuration **/ UINT8 PchFivrExtV1p05RailSupportedVoltageStates; -/** Offset 0x13CC - External V1P05 Voltage Value that will be used in S0i2/S0i3 states +/** Offset 0x13D4 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) **/ UINT16 PchFivrExtV1p05RailVoltage; -/** Offset 0x13CE - External V1P05 Icc Max Value +/** Offset 0x13D6 - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtV1p05RailIccMax; -/** Offset 0x13CF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states +/** Offset 0x13D7 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtVnnRailEnabledStates; -/** Offset 0x13D0 - Mask to enable the platform configuration of external Vnn VR rail +/** Offset 0x13D8 - Mask to enable the platform configuration of external Vnn VR rail External Vnn Rail Supported Configuration **/ UINT8 PchFivrExtVnnRailSupportedVoltageStates; -/** Offset 0x13D1 - Reserved +/** Offset 0x13D9 - Reserved **/ - UINT8 Reserved46; + UINT8 Reserved49; -/** Offset 0x13D2 - External Vnn Voltage Value that will be used in S0ix/Sx states +/** Offset 0x13DA - External Vnn Voltage Value that will be used in S0ix/Sx states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 **/ UINT16 PchFivrExtVnnRailVoltage; -/** Offset 0x13D4 - External Vnn Icc Max Value that will be used in S0ix/Sx states +/** Offset 0x13DC - External Vnn Icc Max Value that will be used in S0ix/Sx states Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtVnnRailIccMax; -/** Offset 0x13D5 - Mask to enable the usage of external Vnn VR rail in Sx states +/** Offset 0x13DD - Mask to enable the usage of external Vnn VR rail in Sx states Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtVnnRailSxEnabledStates; -/** Offset 0x13D6 - External Vnn Voltage Value that will be used in Sx states +/** Offset 0x13DE - External Vnn Voltage Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) **/ UINT16 PchFivrExtVnnRailSxVoltage; -/** Offset 0x13D8 - External Vnn Icc Max Value that will be used in Sx states +/** Offset 0x13E0 - External Vnn Icc Max Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtVnnRailSxIccMax; -/** Offset 0x13D9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage +/** Offset 0x13E1 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage. **/ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; -/** Offset 0x13DA - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage +/** Offset 0x13E2 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage. **/ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; -/** Offset 0x13DB - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage +/** Offset 0x13E3 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage. **/ UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; -/** Offset 0x13DC - Transition time in microseconds from Off (0V) to High Current Mode Voltage +/** Offset 0x13E4 - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. **/ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; -/** Offset 0x13DE - FIVR Dynamic Power Management +/** Offset 0x13E6 - FIVR Dynamic Power Management Enable/Disable FIVR Dynamic Power Management. $EN_DIS **/ UINT8 PchFivrDynPm; -/** Offset 0x13DF - Reserved +/** Offset 0x13E7 - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved50; -/** Offset 0x13E0 - External V1P05 Icc Max Value +/** Offset 0x13E8 - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtV1p05RailIccMaximum; -/** Offset 0x13E2 - External Vnn Icc Max Value that will be used in S0ix/Sx states +/** Offset 0x13EA - External Vnn Icc Max Value that will be used in S0ix/Sx states Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtVnnRailIccMaximum; -/** Offset 0x13E4 - External Vnn Icc Max Value that will be used in Sx states +/** Offset 0x13EC - External Vnn Icc Max Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtVnnRailSxIccMaximum; -/** Offset 0x13E6 - External V1P05 Control Ramp Timer value +/** Offset 0x13EE - External V1P05 Control Ramp Timer value Hold off time to be used when changing the v1p05_ctrl for external bypass value in us **/ UINT8 PchFivrExtV1p05RailCtrlRampTmr; -/** Offset 0x13E7 - External VNN Control Ramp Timer value +/** Offset 0x13EF - External VNN Control Ramp Timer value Hold off time to be used when changing the vnn_ctrl for external bypass value in us **/ UINT8 PchFivrExtVnnRailCtrlRampTmr; -/** Offset 0x13E8 - PCH Compatibility Revision ID +/** Offset 0x13F0 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x13E9 - PCH Legacy IO Low Latency Enable +/** Offset 0x13F1 - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x13EA - Reserved +/** Offset 0x13F2 - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved51; -/** Offset 0x13EB - PCH Unlock SideBand access +/** Offset 0x13F3 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x13EC - Enable 8254 Static Clock Gating +/** Offset 0x13F4 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -2134,7 +2171,7 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x13ED - Enable 8254 Static Clock Gating On S3 +/** Offset 0x13F5 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -2142,174 +2179,174 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x13EE - Enable PCH Io Apic Entry 24-119 +/** Offset 0x13F6 - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x13EF - PCH Io Apic ID +/** Offset 0x13F7 - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x13F0 - CNVi Configuration +/** Offset 0x13F8 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x13F1 - CNVi Wi-Fi Core +/** Offset 0x13F9 - CNVi Wi-Fi Core Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviWifiCore; -/** Offset 0x13F2 - CNVi BT Core +/** Offset 0x13FA - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x13F3 - CNVi BT Interface +/** Offset 0x13FB - CNVi BT Interface This option configures BT device interface to either USB/PCI 1:USB, 2:PCI **/ UINT8 CnviBtInterface; -/** Offset 0x13F4 - CNVi BT Audio Offload +/** Offset 0x13FC - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x13F5 - Reserved +/** Offset 0x13FD - Reserved **/ - UINT8 Reserved49[3]; + UINT8 Reserved52[3]; -/** Offset 0x13F8 - CNVi RF_RESET pin muxing +/** Offset 0x1400 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. **/ UINT32 CnviRfResetPinMux; -/** Offset 0x13FC - CNVi CLKREQ pin muxing +/** Offset 0x1404 - CNVi CLKREQ pin muxing Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in GpioPins*.h. **/ UINT32 CnviClkreqPinMux; -/** Offset 0x1400 - Reserved +/** Offset 0x1408 - Reserved **/ - UINT8 Reserved50; + UINT8 Reserved53; -/** Offset 0x1401 - Enable Device 4 +/** Offset 0x1409 - Enable Device 4 Enable/disable Device 4 $EN_DIS **/ UINT8 Device4Enable; -/** Offset 0x1402 - Skip PAM regsiter lock +/** Offset 0x140A - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x1403 - Reserved +/** Offset 0x140B - Reserved **/ - UINT8 Reserved51; + UINT8 Reserved54; -/** Offset 0x1404 - PCH HDA Verb Table Entry Number +/** Offset 0x140C - PCH HDA Verb Table Entry Number Number of Entries in Verb Table. **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x1405 - Reserved +/** Offset 0x140D - Reserved **/ - UINT8 Reserved52[3]; + UINT8 Reserved55[3]; -/** Offset 0x1408 - PCH HDA Verb Table Pointer +/** Offset 0x1410 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. **/ UINT64 PchHdaVerbTablePtr; -/** Offset 0x1410 - PCH HDA Codec Sx Wake Capability +/** Offset 0x1418 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx **/ UINT8 PchHdaCodecSxWakeCapability; -/** Offset 0x1411 - Enable Pme +/** Offset 0x1419 - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x1412 - HD Audio Link Frequency +/** Offset 0x141A - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x1413 - Reserved +/** Offset 0x141B - Reserved **/ - UINT8 Reserved53[2]; + UINT8 Reserved56[2]; -/** Offset 0x1415 - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode +/** Offset 0x141D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire0; -/** Offset 0x1416 - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode +/** Offset 0x141E - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire1; -/** Offset 0x1417 - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode +/** Offset 0x141F - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire2; -/** Offset 0x1418 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode +/** Offset 0x1420 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire3; -/** Offset 0x1419 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode +/** Offset 0x1421 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeSoundWire4; -/** Offset 0x141A - HD Audio Microphone Privacy applied for Dmic in HW Mode +/** Offset 0x1422 - HD Audio Microphone Privacy applied for Dmic in HW Mode HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchHdaMicPrivacyHwModeDmic; -/** Offset 0x141B - Reserved +/** Offset 0x1423 - Reserved **/ - UINT8 Reserved54[13]; + UINT8 Reserved57[13]; -/** Offset 0x1428 - Pointer to ChipsetInit Binary +/** Offset 0x1430 - Pointer to ChipsetInit Binary ChipsetInit Binary Pointer. **/ UINT64 ChipsetInitBinPtr; -/** Offset 0x1430 - Length of ChipsetInit Binary +/** Offset 0x1438 - Length of ChipsetInit Binary ChipsetInit Binary Length. **/ UINT32 ChipsetInitBinLen; -/** Offset 0x1434 - Reserved +/** Offset 0x143C - Reserved **/ - UINT8 Reserved55[36]; + UINT8 Reserved58[36]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -2328,11 +2365,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x1458 +/** Offset 0x1460 **/ - UINT8 UnusedUpdSpace35[6]; + UINT8 FspsUpdRsvd36[6]; -/** Offset 0x145E +/** Offset 0x1466 **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/86258?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b43faa704959dce5846e22e57f81e651be2d56c Gerrit-Change-Number: 86258 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[XS] Change in coreboot[main]: soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86257?usp=email ) Change subject: soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on ...................................................................... soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on This prevents Windows from displaying the IOM device in Device Manager as an unknown device with no driver available, and brings Alderlake and Tigerlake in line with Meteorlake and Pantherlake. TEST=build/boot Win11 on starlabs/starlite_adl, verify IOM device not shown as unknown device in Device Manager. Change-Id: Ib31018173126737b36a6e0d822eba2ebc9c42306 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss.asl 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/86257/1 diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 6f8edda..2d09c64 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -331,7 +331,8 @@ Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) - Name (_STA, 0xF) + /* ACPI_STATUS_DEVICE_HIDDEN_ON */ + Name (_STA, 0xB) } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 588ed5e..f02a4a3 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -331,7 +331,8 @@ Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) - Name (_STA, 0xF) + /* ACPI_STATUS_DEVICE_HIDDEN_ON */ + Name (_STA, 0xB) } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/86257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib31018173126737b36a6e0d822eba2ebc9c42306 Gerrit-Change-Number: 86257 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[XS] Change in coreboot[main]: soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on
by Matt DeVillier (Code Review) 03 Feb '25

03 Feb '25

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86256?usp=email ) Change subject: soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on ...................................................................... soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on This prevents Windows from displaying the PMC device in Device Manager as an unknown device with no driver available, and brings Alderlake and Tigerlake in line with Meteorlake and Pantherlake. TEST=build/boot Win11 on starlabs/starlite_adl, verify PMC device not shown as unknown device in Device Manager. Change-Id: I4bd62d113455fab7fcb272d85f70e6a185e53b74 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/alderlake/pmc.c M src/soc/intel/tigerlake/pmc.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/86256/1 diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 8930a06..58c9fa8 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -108,7 +108,7 @@ acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller"); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 8912cb3..8846c94 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -107,7 +107,7 @@ acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller"); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). -- To view, visit https://review.coreboot.org/c/coreboot/+/86256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bd62d113455fab7fcb272d85f70e6a185e53b74 Gerrit-Change-Number: 86256 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/amd/birman_plus: Update phoenix port descriptors
by Felix Singer (Code Review) 03 Feb '25

03 Feb '25

Felix Singer has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/86232?usp=email ) Change subject: mb/amd/birman_plus: Update phoenix port descriptors ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: It was merged out of queue. Just merged CB:85493 which should fix the issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/86232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54d35060c34043f9d97658ab84b9b1bb2e62ba60 Gerrit-Change-Number: 86232 Gerrit-PatchSet: 2 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Mon, 03 Feb 2025 21:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: mb/amd/birman_plus: Update PCIe Slot configurations
by Felix Singer (Code Review) 03 Feb '25

03 Feb '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85493?usp=email ) Change subject: mb/amd/birman_plus: Update PCIe Slot configurations ...................................................................... mb/amd/birman_plus: Update PCIe Slot configurations Rectify board configuration flags based on the schematics Doc. 105-D99700-00C and User Guide #58168 (NDA). Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85493 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/ec.c M src/mainboard/amd/birman_plus/port_descriptors_glinda.c M src/mainboard/amd/birman_plus/port_descriptors_phoenix.c 4 files changed, 62 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig index 462fece..02f3f23 100644 --- a/src/mainboard/amd/birman_plus/Kconfig +++ b/src/mainboard/amd/birman_plus/Kconfig @@ -99,39 +99,44 @@ help Enable the 19V rail for Eval Card PCIe slot -choice - prompt "DT SLOT/M.2 SSD1 ENABLE" - default ENABLE_DT_SLOT_BIRMANPLUS +config ENABLE_SSD1_BIRMANPLUS + bool "Enable M.2 SSD1 Slot" help - Either DT slot or M.2 SSD1 can be used, as they are sharing PCIe lanes. + Enable M.2 SSD1 Slot. For Glinda SoC this will downgrade + PCIe x8 slot to x4. -config ENABLE_DT_SLOT_BIRMANPLUS - bool "Enable DT slot" +choice + prompt "GBE Enable/WWAN LANE1 Selection" + default ENABLE_GBE_BIRMANPLUS + help + When the M.2 x2 WWAN slot is enabled, the GbE LAN is disabled. -config ENABLE_M2_SSD1_BIRMANPLUS - bool "Enable M.2 SSD1" +config ENABLE_GBE_BIRMANPLUS + bool "Enable GBE (1 Lane WWAN)" -config DISABLE_DT_M2_BIRMANPLUS - bool "Disable both DT and M.2 slot" +config ENABLE_WWAN02_BIRMANPLUS + bool "Enable only WWAN (2 Lanes WWAN)" +config DISABLE_WWAN_GBE_BIRMANPLUS + bool "Disable both WWAN and GBE" endchoice choice - prompt "WLAN/WWAN Selection" - default WLAN0_WWAN0_BIRMANPLUS + prompt "SD Card Enable/WLAN LANE1 Selection" + default ENABLE_SDCARD_BIRMANPLUS help - WLAN and WWAN lane configuration + When the M.2 x2 WLAN slot is enabled, the SD Card Reader is disabled. -config WLAN0_WWAN0_BIRMANPLUS - bool "Both WLAN and WWAN Enabled (1 lane each)" +config ENABLE_SDCARD_BIRMANPLUS + bool "Enable SD Card (1 Lane WLAN)" -config WLAN01_BIRMANPLUS - bool "Only WLAN Enabled (2 lanes WLAN, 0 lanes WWAN)" +config ENABLE_WLAN02_BIRMANPLUS + bool "Enable only WLAN (2 Lanes WLAN)" -config WWAN01_BIRMANPLUS - bool "Only WWAN Enabled (2 lanes WWAN, 0 lanes WLAN)" - +config DISABLE_WLAN_SD_BIRMANPLUS + bool "Disable both WLAN and SD Card" endchoice + if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 3 # Quad IO (1-1-4) diff --git a/src/mainboard/amd/birman_plus/ec.c b/src/mainboard/amd/birman_plus/ec.c index 2ddc049..168da3e 100644 --- a/src/mainboard/amd/birman_plus/ec.c +++ b/src/mainboard/amd/birman_plus/ec.c @@ -130,21 +130,12 @@ ec_write(EC_GPIO_7_ADDR, tmp); tmp = ec_read(EC_GPIO_8_ADDR); - if (CONFIG(ENABLE_M2_SSD1_BIRMANPLUS)) { - tmp |= EC8_DT_N_SSD1_SW; - } else { - tmp &= ~EC8_DT_N_SSD1_SW; - } + tmp |= EC8_DT_N_SSD1_SW; printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp); ec_write(EC_GPIO_8_ADDR, tmp); tmp = ec_read(EC_GPIO_9_ADDR); - tmp |= EC9_CAM0_PWR_EN | EC9_CAM1_PWR_EN | EC9_WWAN_RST | EC9_TPM_PWR_EN; - if (CONFIG(ENABLE_DT_SLOT_BIRMANPLUS)) { - tmp |= EC9_DT_PWREN; - } else { - tmp &= ~EC9_DT_PWREN; - } + tmp |= EC9_CAM0_PWR_EN | EC9_CAM1_PWR_EN | EC9_WWAN_RST | EC9_TPM_PWR_EN | EC9_DT_PWREN; printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_9_ADDR, tmp); ec_write(EC_GPIO_9_ADDR, tmp); @@ -158,12 +149,7 @@ ec_write(EC_GPIO_C_ADDR, tmp); tmp = ec_read(EC_GPIO_D_ADDR); - tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN | ECD_TPAD_DISABLE_N; - if (CONFIG(ENABLE_M2_SSD1_BIRMANPLUS)) { - tmp |= ECD_SSD1_PWR_EN; - } else { - tmp &= ~ECD_SSD1_PWR_EN; - } + tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN | ECD_TPAD_DISABLE_N | ECD_SSD1_PWR_EN; printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_D_ADDR, tmp); ec_write(EC_GPIO_D_ADDR, tmp); @@ -171,12 +157,12 @@ tmp |= ECE_LOM_PWR_EN | ECE_SSD0_PWR_EN | ECE_SD_PWR_EN; tmp |= ECE_CAM_PWR_EN | ECE_FPR_N_GBE_SEL; tmp &= ~ECE_BT_N_TPNL_SEL; - if (CONFIG(WLAN01_BIRMANPLUS)) { // no WWAN, turn off WWAN power + if (CONFIG(DISABLE_WWAN_GBE_BIRMANPLUS)) { // no WWAN, turn off WWAN power tmp &= ~ECE_WWAN_PWR_EN; } else { tmp |= ECE_WWAN_PWR_EN; } - if (CONFIG(WWAN01_BIRMANPLUS)) { // no WLAN, turn off WLAN power + if (CONFIG(DISABLE_WLAN_SD_BIRMANPLUS)) { // no WLAN, turn off WLAN power tmp &= ~ECE_WLAN_PWR_EN; } else { tmp |= ECE_WLAN_PWR_EN; @@ -185,12 +171,12 @@ ec_write(EC_GPIO_E_ADDR, tmp); tmp = ec_read(EC_GPIO_F_ADDR); - if (CONFIG(WLAN01_BIRMANPLUS)) { + if (CONFIG(ENABLE_WLAN02_BIRMANPLUS)) { tmp |= ECF_WWAN0_N_WLAN1_SW; } else { tmp &= ~ECF_WWAN0_N_WLAN1_SW; } - if (CONFIG(WWAN01_BIRMANPLUS)) { + if (CONFIG(ENABLE_WWAN02_BIRMANPLUS)) { tmp |= ECF_WLAN0_N_WWAN1_SW; } else { tmp &= ~ECF_WLAN0_N_WWAN1_SW; diff --git a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c index ae6f668..b699ca8 100644 --- a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c +++ b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c @@ -11,7 +11,7 @@ .engine_type = PCIE_ENGINE, \ .port_present = CONFIG(ENABLE_EVAL_CARD), \ .start_logical_lane = 0, \ - .end_logical_lane = 7, \ + .end_logical_lane = CONFIG(ENABLE_SSD1_BIRMANPLUS) ? 3 : 7, \ .device_number = 3, \ .function_number = 1, \ .link_speed_capability = GEN_MAX, \ @@ -22,6 +22,21 @@ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ } +#define glinda_ssd1_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 4, \ + .end_logical_lane = 7, \ + .device_number = 3, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ1, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + #define glinda_ssd0_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ .port_present = true, \ @@ -39,11 +54,11 @@ #define glinda_wlan_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = true, \ - .start_logical_lane = 15, \ + .port_present = !CONFIG(DISABLE_WLAN_SD_BIRMANPLUS), \ + .start_logical_lane = CONFIG(ENABLE_WLAN02_BIRMANPLUS) ? 14 : 15, \ .end_logical_lane = 15, \ .device_number = 2, \ - .function_number = 2, \ + .function_number = 3, \ .link_speed_capability = GEN_MAX, \ .turn_off_unused_lanes = true, \ .link_aspm = ASPM_L1, \ @@ -53,9 +68,9 @@ #define glinda_wwan_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = true, \ + .port_present = !CONFIG(DISABLE_WWAN_GBE_BIRMANPLUS), \ .start_logical_lane = 12, \ - .end_logical_lane = 12, \ + .end_logical_lane = CONFIG(ENABLE_WWAN02_BIRMANPLUS) ? 13 : 12, \ .device_number = 2, \ .function_number = 5, \ .link_speed_capability = GEN_MAX, \ @@ -91,7 +106,7 @@ .link_speed_capability = GEN_MAX, \ .turn_off_unused_lanes = true, \ .link_aspm = ASPM_L1, \ - .link_hotplug = HOTPLUG_DISABLED, \ + .link_hotplug = HOTPLUG_BASIC, \ .clk_req = CLK_REQ5, \ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ } @@ -170,11 +185,18 @@ static const fsp_dxio_descriptor birmanplus_glinda_dxio_descriptors[] = { glinda_mxm_dxio_descriptor, +#if CONFIG(ENABLE_SSD1_BIRMANPLUS) + glinda_ssd1_dxio_descriptor, +#endif glinda_ssd0_dxio_descriptor, glinda_wlan_dxio_descriptor, glinda_wwan_dxio_descriptor, +#if CONFIG(ENABLE_GBE_BIRMANPLUS) glinda_gbe_dxio_descriptor, +#endif +#if CONFIG(ENABLE_SDCARD_BIRMANPLUS) glinda_sd_dxio_descriptor, +#endif }; *dxio_descs = birmanplus_glinda_dxio_descriptors; diff --git a/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c b/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c index e36e579..0caf713 100644 --- a/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c @@ -52,7 +52,7 @@ #define phx_ssd1_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = true, \ + .port_present = CONFIG(ENABLE_SSD1_BIRMANPLUS), \ .start_lane = 8, \ .end_lane = 11, \ .device_number = 1, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/85493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Gerrit-Change-Number: 85493 Gerrit-PatchSet: 24 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025