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Change subject: mb/amd/birman_plus: Update PCIe Slot configurations
......................................................................
Patch Set 23: Code-Review+2
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Change subject: mb/amd/birman_plus: Update PCIe Slot configurations
......................................................................
Patch Set 23:
(1 comment)
Patchset:
PS23:
CB:86232 was merged out of queue, which is depending on this one and thus breaking the CI. It seems people approved this one before, so I'm getting this in.
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Change subject: tree: Use true, false for DspEnable
......................................................................
Patch Set 3: Code-Review+2
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Maximilian Brune has uploaded a new patch set (#9) to the change originally created by Fred Reitberger. ( https://review.coreboot.org/c/coreboot/+/68122?usp=email )
Change subject: soc/amd/common: Support sbin ucode files
......................................................................
soc/amd/common: Support sbin ucode files
Recent PI releases have been distributing the ucode patch files as sbin
files instead of bin files. The sbin uses a 256 byte amd_fw_header to
wrap the bin file.
Offset 0x14 of the header is the size field. The can be extracted with
od to get the size of the ucode bin file. The bin file can then be
extracted with dd and placed in the build directory for inclusion as a
cbfs file.
In the case where both an sbin and bin ucode file are present, the bin
file will be added and a note will print at the start of the build about
the sbin file being skipped.
TEST=builds with only bin, only sbin, non-matching bin and sbin,
matching bin and sbin files
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae
---
M src/soc/amd/common/Makefile.mk
M src/soc/amd/common/block/cpu/Makefile.mk
2 files changed, 45 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/68122/9
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Maximilian Brune has uploaded a new patch set (#8) to the change originally created by Fred Reitberger. ( https://review.coreboot.org/c/coreboot/+/68122?usp=email )
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: soc/amd/common: Support sbin ucode files
......................................................................
soc/amd/common: Support sbin ucode files
Recent PI releases have been distributing the ucode patch files as sbin
files instead of bin files. The sbin uses a 256 byte amd_fw_header to
wrap the bin file.
Offset 0x14 of the header is the size field. The can be extracted with
od to get the size of the ucode bin file. The bin file can then be
extracted with dd and placed in the build directory for inclusion as a
cbfs file.
In the case where both an sbin and bin ucode file are present, the bin
file will be added and a note will print at the start of the build about
the sbin file being skipped.
TEST=builds with only bin, only sbin, non-matching bin and sbin,
matching bin and sbin files
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae
---
M src/soc/amd/common/Makefile.mk
M src/soc/amd/common/block/cpu/Makefile.mk
2 files changed, 47 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/68122/8
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Change subject: intel/acpi: Put BSP as the first entry
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/86247/comment/ef6cfce9_a4f898f3?us… :
PS5, Line 68: cpu_apic_info.is_bsp_perf = cpu_infos[i].cpu->path.apic.core_type == CPU_TYPE_PERF;
> Break the line to meet coding style guidelines. Similarly to line 72.
Done
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Hello Intel coreboot Reviewers, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86247?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: intel/acpi: Put BSP as the first entry
......................................................................
intel/acpi: Put BSP as the first entry
Linux complains in dmesg as a firmware bug that BSP is not the first
entry.
NetBSD hangs and OpenBSD panics early on boot.
With this patch I was able to boot NetBSD and OpenBSD on darp10-b when
loaded in GRUB.
Note: vanilla bootloaders for NetBSD and OpenBSD still result in an
apparent hang for an unknown reason.
Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
M src/soc/intel/common/block/acpi/cpu_hybrid.c
1 file changed, 29 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/86247/6
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Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86220?usp=email )
Change subject: toolchain: Print CC command and output when CC invocation fails
......................................................................
toolchain: Print CC command and output when CC invocation fails
We are gobbling up the `$(CC_$(arch))` stderr when testing the
toolchain. This change makes it so we print the command we tried to
invoke and the output from the command.
```
toolchain.mk:183: The coreboot toolchain for 'x86_32' architecture was not found.
toolchain.mk:183: /build/guybrush/tmp/portage/sys-boot/coreboot-9999/files/reclient/ccache /build/guybrush/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-gcc -v
I AM STDERR
toolchain.mk:183: I AM STDOUT
toolchain.mk:219:
toolchain.mk:220: Path to your toolchain is currently set to '/build/guybrush/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin'
toolchain.mk:222:
toolchain.mk:223: To build the entire coreboot toolchain: run 'make crossgcc'
```
BUG=b:392874252, b:389737339
TEST=USE_REMOTEEXEC=true BOARD=brya bazel run @portage//internal/packages/stage2/target/board/chromiumos/sys-boot/coreboot:9999_debug
Change-Id: I7c7352c7254c21deb3e4a03106b841ec9f111ba4
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86220
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy(a)google.com>
---
M toolchain.mk
1 file changed, 4 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Jon Murphy: Looks good to me, approved
diff --git a/toolchain.mk b/toolchain.mk
index 77fb46e..8d6d449 100644
--- a/toolchain.mk
+++ b/toolchain.mk
@@ -187,7 +187,10 @@
echo not-coreboot; else echo not-coreboot; fi), \
$(eval COMPILERFAIL:=1)\
$(warning The coreboot toolchain for '$(arch)'\
- architecture was not found.)))
+ architecture was not found.)\
+ $(if $(CC_$(arch)),\
+ $(warning $(CC_$(arch)) -v)\
+ $(warning $(shell $(CC_$(arch)) -v)))))
# If iasl doesn't match the current coreboot version, fail the test
# TODO: Figure out if iasl is even needed for the build.
$(if $(shell if [ -n "$(IASL)" ]; then \
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Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82633?usp=email )
Change subject: mb/asus/p8z77-m: Hide peg11 to squelch warning
......................................................................
mb/asus/p8z77-m: Hide peg11 to squelch warning
All 16 IVB PCIe lanes go to one x16 slot without bifurcation.
There is no use for peg11.
Hide it to squelch the leftover devices warning.
Change-Id: I75402d338e64f477f40682f796477e8fcb94a4e8
Signed-off-by: Keith Hui <buurin(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82633
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index c88b260..e84125b 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -3,6 +3,7 @@
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x1043 0x84ca inherit
+ device ref peg11 hidden end # These don't exist on this board
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "gen1_dec" = "0x000c0291"
register "usb_port_config" = "{
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