Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83218?usp=email )
Change subject: device/azalia_device.c: Always read-write GCAP
......................................................................
device/azalia_device.c: Always read-write GCAP
In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP
register is RO (Read Only). However, it is known that in some Intel
PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some
of the bitfields in the GCAP register are R/WO (Read / Write Once).
GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock
bit for GCAP elsewhere.
Lock GCAP by reading GCAP and writing back the same value. This has
no effect on platforms that implement GCAP as a RO register or lock
GCAP through a different mechanism.
Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/Kconfig
M src/device/azalia_device.c
M src/soc/intel/common/block/hda/Kconfig
3 files changed, 13 insertions(+), 14 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/src/device/Kconfig b/src/device/Kconfig
index f1343f8..243e23e 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -575,15 +575,6 @@
mainboard directory to the build which contain the board-specific HD
audio codec configuration.
-config AZALIA_LOCK_DOWN_R_WO_GCAP
- def_bool n
- depends on AZALIA_HDA_CODEC_SUPPORT
- help
- The GCAP register is implemented as R/WO (Read / Write Once) on some
- HD Audio controllers, such as Intel 6-series PCHs. Select this option
- to lock down the GCAP register after deasserting the controller reset
- bit. Locking is done by reading GCAP and writing back the read value.
-
config PCIEXP_PLUGIN_SUPPORT
bool
default y
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index 02bbf89..4eed489 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -56,10 +56,19 @@
if (azalia_exit_reset(base) < 0)
goto no_codec;
- if (CONFIG(AZALIA_LOCK_DOWN_R_WO_GCAP)) {
- /* If GCAP is R/WO, lock it down after deasserting controller reset */
- write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
- }
+ /*
+ * In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP
+ * register is RO (Read Only). However, it is known that in some Intel
+ * PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some
+ * of the bitfields in the GCAP register are R/WO (Read / Write Once).
+ * GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock
+ * bit for GCAP elsewhere.
+ *
+ * Lock GCAP by reading GCAP and writing back the same value. This has
+ * no effect on platforms that implement GCAP as a RO register or lock
+ * GCAP through a different mechanism.
+ */
+ write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
/* clear STATESTS bits (BAR + 0x0e)[14:0] */
reg16 = read16(base + HDA_STATESTS_REG);
diff --git a/src/soc/intel/common/block/hda/Kconfig b/src/soc/intel/common/block/hda/Kconfig
index 64f34ef..a91764a 100644
--- a/src/soc/intel/common/block/hda/Kconfig
+++ b/src/soc/intel/common/block/hda/Kconfig
@@ -8,6 +8,5 @@
config SOC_INTEL_COMMON_BLOCK_HDA_VERB
bool
depends on SOC_INTEL_COMMON_BLOCK_HDA
- select AZALIA_LOCK_DOWN_R_WO_GCAP
help
Enable initialization of HDA codecs.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80411?usp=email
to look at the new patch set (#18).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s
......................................................................
Documentation/mainboard/lenovo: Add ThinkCentre M710s
Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M 3rdparty/arm-trusted-firmware
M 3rdparty/intel-microcode
M 3rdparty/libgfxinit
M 3rdparty/vboot
M Documentation/mainboard/index.md
A Documentation/mainboard/lenovo/thinkcentre_m710s.md
A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg
7 files changed, 85 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/80411/18
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Change subject: Makefile.mk: Use one line per *_common flag
......................................................................
Patch Set 1: Code-Review+2
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Change subject: util/superiotool: Add extra selectors support
......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83196/comment/1556ed40_c262ff5e?us… :
PS2, Line 9: ,
nit: this comma looks odd. Were you going to add something here?
> Some chips, such as <foo bar baz>, have specific selectors ...
If not, I would prefer to remove it
https://review.coreboot.org/c/coreboot/+/83196/comment/2c8e8702_c23d7661?us… :
PS2, Line 38: the motherboard
Which one?
File util/superiotool/superiotool.h:
https://review.coreboot.org/c/coreboot/+/83196/comment/0679afdb_a5844e75?us… :
PS2, Line 140: typedef struct {
: const char *name;
: uint8_t idx;
: uint8_t mask;
: uint8_t val;
: } extra_selector_t;
Please, no typedefs: https://doc.coreboot.org/contributing/coding_style.html#typedefs
```suggestion
struct extra_selector {
const char *name;
uint8_t idx;
uint8_t mask;
uint8_t val;
};
```
And replace other instances of `extra_selector_t` with `struct extra_selector`.
File util/superiotool/superiotool.c:
https://review.coreboot.org/c/coreboot/+/83196/comment/04349f99_48b5adab?us… :
PS2, Line 87: {
nit: move brace to new line
(When in Rome, do as the Romans do)
https://review.coreboot.org/c/coreboot/+/83196/comment/d99b0ebd_593bef7e?us… :
PS2, Line 96: (~esel->mask)
I'd say it would make more sense to invert the mask, i.e. make `esel->mask` contain ones for the bits to preserve.
https://review.coreboot.org/c/coreboot/+/83196/comment/7ffdc25f_d0347053?us… :
PS2, Line 98: /* -- ESEL[27h] : 0x00 (Port Select Register) -- */
Since these comments are specific to a chip, I would prefer to remove them as they can cause confusion
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Change subject: Makefile.mk: Use one line per *_common flag
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I would prefer that to be a separate commit, since it is easier for review. […]
I agree, it should be a separate commit.
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Change subject: utils/superiotool/fintek: Add missing F81804 name for 0x0215 id
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83018/comment/ce320996_b69a6fba?us… :
PS6, Line 7: utils
nit: util
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Change subject: utils/superiotool/fintek: Add missing F81804 name for 0x0215 id
......................................................................
Patch Set 6: Code-Review+2
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Change subject: util/superiotool/fintek: Add f81866 register table
......................................................................
Patch Set 11:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83004/comment/3d3b5eb5_e721b011?us… :
PS9, Line 13:
> > `'Sould' may be misspelled - perhaps 'Should'?` […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/83004/comment/467780e5_231c74d2?us… :
PS11, Line 12: Should be added after CB:83196.
This should already be clear enough given the patch train. No strong opinion though (it can stay).
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Change subject: util/superiotool/fintek: Add f81866 register table
......................................................................
Patch Set 11:
(1 comment)
File util/superiotool/fintek.c:
https://review.coreboot.org/c/coreboot/+/83004/comment/20cfe8d7_4a9b2965?us… :
PS11, Line 521: {0x30,0x60,0x61,0x70,0x71,0x72,0x73,0x7e,0x7f, 0xf0,0xf1,0xf2,0xf3,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9, 0xe0,0xe1,0xe2,0xe3,0xe8,0xe9, 0xd0,0xd1,0xd2,0xd3, 0xc0,0xc1,0xc2,0xc3, 0xb0,0xb1,0xb2,0xb3, 0xa0,0xa1,0xa2,0xa3,0xa8,0xa9, 0x90,0x91,0x92,0x93, 0x80,0x81,0x82,0x83, 0x88,0x89,0x8a,0x8b,0x8e,0x8f, 0xef, EOT},
Please wrap these lines, as done in other Super I/Os. I see you have extra spaces to separate registers in groups already, these groups can be in separate lines.
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Change subject: drivers/spi/acpi: Add generic property list
......................................................................
Patch Set 10:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83139/comment/ba96b8ec_5386e0b6?us… :
PS9, Line 8:
> Please start by describing the problem.
Done
https://review.coreboot.org/c/coreboot/+/83139/comment/eb0a6bc2_f11c6695?us… :
PS9, Line 14: TEST=emerge-brox coreboot
> Any commands you ran?
local build bios,and verify that the correct transfer of hid-report-addr to the touch driver.
File src/drivers/spi/acpi/chip.h:
https://review.coreboot.org/c/coreboot/+/83139/comment/fe52f5a7_ccb64f77?us… :
PS9, Line 8: #define MAX_GENERIC_PROPERTY_LIST 10
> Why 10? Please elaborate in the commit.
This is a universal code. If only one attribute is defined for the vendor Goodix, in the future, if other vendors need to define multiple attributes, it cannot be met. MAX_GENERIC-PROPERTY-LIST needs to be modified, defined as 10 here, which basically meets the attribute requirements of all vendors. In the future, other projects only need to add the vendor's attributes in the devicetree without further modification.
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