coreboot-gerrit June 2024

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[S] Change in coreboot[main]: util/superiotool: Add extra selectors support
by Maxim (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Angel Pons, Felix Held, Paul Menzel. Maxim has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83196?usp=email ) Change subject: util/superiotool: Add extra selectors support ...................................................................... Patch Set 3: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83196/comment/ec8bcf7a_f578adcb?us… : PS2, Line 9: , > nit: this comma looks odd. Were you going to add something here? […] Removed https://review.coreboot.org/c/coreboot/+/83196/comment/c37bb93a_69a5d37e?us… : PS2, Line 38: the motherboard > Which one? Asrock H110-STX File util/superiotool/superiotool.h: https://review.coreboot.org/c/coreboot/+/83196/comment/01446b8b_0a20be51?us… : PS2, Line 140: typedef struct { : const char *name; : uint8_t idx; : uint8_t mask; : uint8_t val; : } extra_selector_t; > Please, no typedefs: https://doc.coreboot.org/contributing/coding_style.html#typedefs […] Done File util/superiotool/superiotool.c: https://review.coreboot.org/c/coreboot/+/83196/comment/65fd6dfb_641d5df2?us… : PS2, Line 87: { > nit: move brace to new line […] Fixed (Sometimes this happens if switch between C and Go) https://review.coreboot.org/c/coreboot/+/83196/comment/ed9095c9_46b37765?us… : PS2, Line 96: (~esel->mask) > I'd say it would make more sense to invert the mask, i.e. […] Done https://review.coreboot.org/c/coreboot/+/83196/comment/da55f6bf_143e02a4?us… : PS2, Line 98: /* -- ESEL[27h] : 0x00 (Port Select Register) -- */ > Since these comments are specific to a chip, I would prefer to remove them as they can cause confusi […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead Gerrit-Change-Number: 83196 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Jun 2024 21:12:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: lib: Add Kconfig variable for fw_config default value
by Cliff Huang (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Julius Werner, Paul Menzel, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83153?usp=email ) Change subject: lib: Add Kconfig variable for fw_config default value ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83153/comment/ba295a49_9997ba8c?us… : PS3, Line 7: src/lib > Just `lib/`? Acknowledged https://review.coreboot.org/c/coreboot/+/83153/comment/83071754_0a48a67a?us… : PS3, Line 9: This CONFIG_FW_CONFIG_DEFAULT_VALUE flag is default to > Please start by describing the problem, you are trying to solve. Acknowledged https://review.coreboot.org/c/coreboot/+/83153/comment/4832f795_09656ad3?us… : PS3, Line 9: is default to > defaults to Acknowledged https://review.coreboot.org/c/coreboot/+/83153/comment/5ac27360_8909b1c5?us… : PS3, Line 9: This CONFIG_FW_CONFIG_DEFAULT_VALUE flag is default to : UNDEFINED_FW_CONFIG and won't be used when retrieving fw_config : value. Set this with different value in config.<board> file, and : it will be used when fw_config is not able to read via Chrome EC, : CBFS or VPD. > Please try to use 72 characters per line. Acknowledged File src/Kconfig: https://review.coreboot.org/c/coreboot/+/83153/comment/0649f0ac_3e9dd038?us… : PS3, Line 550: when not able to retrieve > This reads strangely. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/83153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9694433e01bdcd9ff1e550585c14ea7ccee020a3 Gerrit-Change-Number: 83153 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Jun 2024 21:09:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: lib: Add Kconfig variable for fw_config default value
by Cliff Huang (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Julius Werner, Subrata Banik, Wonkyu Kim. Hello Anil Kumar K, Bora Guvendik, Jérémy Compostella, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83153?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Anil Kumar K, Verified+1 by build bot (Jenkins) Change subject: lib: Add Kconfig variable for fw_config default value ...................................................................... lib: Add Kconfig variable for fw_config default value This CONFIG_FW_CONFIG_DEFAULT_VALUE is used only when CBI fw_config value cannot be read from all sources such as Chrome EC and VPD. It defaults to the same value as UNDEFINED_FW_CONFIG defined in fw_config.h. and it won't be used unless it is set to different value in config.<board> file. If a valid value is read from the Chrome EC or VPD, the fw_config value won't be not overriden by this flag. TEST=boot and check fw_config value from coreboot log Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I9694433e01bdcd9ff1e550585c14ea7ccee020a3 --- M src/Kconfig M src/lib/fw_config.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/83153/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9694433e01bdcd9ff1e550585c14ea7ccee020a3 Gerrit-Change-Number: 83153 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: util/superiotool: Add extra selectors support
by Maxim (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Felix Held, Maxim, Paul Menzel. Hello Angel Pons, Felix Held, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83196?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/superiotool: Add extra selectors support ...................................................................... util/superiotool: Add extra selectors support Some chips have specific selectors (in addition to LDN-register) that affect the register space. At the same time, the utility doesn't provide a simple and convenient method for configuring such selectors (as in the case of LDN-selector) to create a dump, because this may be configured by several fields of the register, and the values of its other fields should not change after setting in the BIOS (fintek [1,2]). Just add a structure with an index, mask, and value for the selector inside the superio_registers chip for the corresponding LDN to switch the register bank: {FINTEK_F81966_DID, "F81962/F81964/F81966/F81967", { * * * {NOLDN, "Global", {0x28,0x2a,0x2b,0x2c,EOT}, {0x00,0x00,0x00,0x00,EOT}, {.idx = 0x27, .mask = 0xd, .val = 0x1} /* update extra selector */ }, {0x03, "LPT", {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, {NANA,0x03,0x78,0x07,0x03,0xc2,EOT} /* without extra selector */ }, * * * Tested with Fintek F81966 on Asrock IMB-1222 [3]: superiotool r24.05-235-g7ba0cc0f4c Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e (Global) -- ESEL[27h] 0x08 (Port Select Register) -- idx def val 0x27: 0x02 [0x88] 0x28: 0x03 0x03 0x2a: 0x60 0x60 0x2b: 0x00 [0x03] 0x2c: 0x00 [0x01] The changes do not affect the configuration of existing chips, which was tested on the Asrock H110-STX motherboard with Nuvoton NCT5539D (the dump before and after the changes are the same). [1] CB:83004 [2] CB:83019 [3] CB:83107 Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/superiotool/superiotool.c M util/superiotool/superiotool.h 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83196/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead Gerrit-Change-Number: 83196 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: util/superiotool/fintek: Add f81866 register table
by Maxim (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Felix Held, Felix Singer, Maxim, Michał Żygowski, Paul Menzel. Hello Felix Held, Felix Singer, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83004?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/superiotool/fintek: Add f81866 register table ...................................................................... util/superiotool/fintek: Add f81866 register table In accordance with the F81866A datasheet: Release Date: Jan, 2012, Version: V0.14P [1]. Should be added after CB:83196. [1] http://www.jetwaycomputer.com/download/Fintek/F81866_wdt_gpio.zip Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/superiotool/fintek.c 1 file changed, 127 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/83004/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/83004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b Gerrit-Change-Number: 83004 Gerrit-PatchSet: 12 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: util/superiotool/fintek: Add f81966 register table
by Maxim (Code Review) 28 Jun '24

28 Jun '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83019?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/superiotool/fintek: Add f81966 register table ...................................................................... util/superiotool/fintek: Add f81966 register table In accordance with the F81962/F81964/F81966/F81967 datasheet: Release Date: Feb, 2018, Version: V0.18P [1]. Tested on Asrock IMB-1222 [2]. [1] http://www.jetwaycomputer.com/download/Fintek/F81966_wdt_gpio.zip [2] CB:83107 Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/superiotool/fintek.c 1 file changed, 94 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83019/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/83019?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1 Gerrit-Change-Number: 83019 Gerrit-PatchSet: 10 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
by Maxim (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Felix Singer, Martin Roth. Maxim has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83018?usp=email ) Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83018/comment/d1136f9c_d88a0195?us… : PS7, Line 10: https > Putting URLs in the commit message is discouraged as they frequently become stale. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6889ad8ad861465316333ff997956a05b74c5855 Gerrit-Change-Number: 83018 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 Jun 2024 20:46:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[XS] Change in coreboot[main]: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
by Maxim (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Felix Singer, Maxim. Hello Angel Pons, Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83018?usp=email to look at the new patch set (#8). Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id ...................................................................... util/superiotool/fintek: Add missing F81804 name for 0x0215 id "0x1502 F81804 chipset ID, same for F81966" in https://web.archive.org/web/20240628153609/https://github.com/torvalds/ linux/blob/master/drivers/gpio/gpio-f7188x.c Change-Id: I6889ad8ad861465316333ff997956a05b74c5855 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/superiotool/fintek.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83018/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/83018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6889ad8ad861465316333ff997956a05b74c5855 Gerrit-Change-Number: 83018 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com>

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[L] Change in coreboot[main]: mb/intel/tglrvp/dt: Make use of device alias names
by Felix Singer (Code Review) 28 Jun '24

28 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83244?usp=email ) Change subject: mb/intel/tglrvp/dt: Make use of device alias names ...................................................................... mb/intel/tglrvp/dt: Make use of device alias names Also, remove superfluous comments from devices which repeat their name. Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83244 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 142 insertions(+), 145 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 6a7db5f..f03f677 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -162,10 +162,9 @@ }" device domain 0 on - #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref system_agent on end + device ref igpu on end + device ref dptf on # Default DPTF Policy for all tglrvp_up3 boards if not overridden chip drivers/intel/dptf register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" @@ -186,45 +185,44 @@ .granularity = 1000,}" device generic 0 on end end - end # DPTF 0x9A04:U22/0x9A14:U42 + end - device pci 05.0 on end # IPU 0x9A19 - device pci 06.0 on end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 - device pci 08.0 off end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 on end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B + device ref ipu on end + device ref peg on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref gna off end + device ref npk off end + device ref crashlog off end + device ref north_xhci on end + device ref north_xdci on end + device ref tbt_dma0 on end + device ref tbt_dma1 on end + device ref vmd off end - # From PCH EDS(576591) - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - device pci 12.0 on # SensorHUB 0xA0FC + device ref thc0 off end + device ref thc1 off end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""tglrvp_ish.bin"" device generic 0 on end end end - device pci 12.6 off end # GSPI2 0x34FB - device pci 13.0 off end # GSPI3 0xA0FD - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 on end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 on + device ref gspi2 off end + device ref gspi3 off end + device ref south_xhci on end + device ref south_xdci on end + device ref shared_ram on end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end - end # CNVi: WiFi 0xA0F0 - A0F3 + end - device pci 15.0 on # I2C0 0xA0E8 + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC1308"" register "name" = ""RTAM"" @@ -259,58 +257,58 @@ register "property_list[0].integer" = "1" device i2c 1a on end end - end # I2C0 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - device pci 17.0 on end # SATA 0xA0D3 - device pci 19.0 off end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 on end # UART2 0xA0C7 - device pci 1c.0 off end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 on end # RP3 0xA0BA - device pci 1c.3 on + end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref heci2 off end + device ref csme1 off end + device ref csme2 off end + device ref heci3 off end + device ref heci4 off end + device ref sata on end + device ref i2c4 off end + device ref i2c5 on end + device ref uart2 on end + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 on end + device ref pcie_rp4 on chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" register "srcclk_pin" = "2" device generic 0 on end end - end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # RP6 0xA0BD - device pci 1c.6 off end # RP7 0xA0BE - device pci 1c.7 off end # RP8 0xA0BF - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - device pci 1e.0 off end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref pcie_rp9 on end + device ref pcie_rp10 off end + device ref pcie_rp11 on end + device ref pcie_rp12 off end + device ref uart0 off end + device ref uart1 off end + device ref gspi0 on end + device ref gspi1 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" device spi 0 on end end - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden # PMC 0xA0A1 + end + device ref p2sb on end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -331,11 +329,11 @@ end end end - end # PMC - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 on end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + device ref gbe off end + device ref tracehub off end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 5960a3c..03e9c2d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -167,9 +167,9 @@ device domain 0 on #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref system_agent on end + device ref igpu on end + device ref dptf on # Default DPTF Policy for all tglrvp_up4 boards if not overridden chip drivers/intel/dptf register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" @@ -190,45 +190,44 @@ .granularity = 1000,}" device generic 0 on end end - end # DPTF 0x9A02:Y22/0x9A12:Y42 + end - device pci 05.0 on end # IPU 0x9A19 - device pci 06.0 on end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 08.0 off end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 on end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B + device ref ipu on end + device ref peg on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 off end + device ref gna off end + device ref npk off end + device ref crashlog off end + device ref north_xhci on end + device ref north_xdci on end + device ref tbt_dma0 on end + device ref tbt_dma1 on end + device ref vmd off end - # From PCH EDS(576591) - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - device pci 12.0 on # SensorHUB 0xA0FC + device ref thc0 off end + device ref thc1 off end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""tglrvp_ish.bin"" device generic 0 on end end end - device pci 12.6 off end # GSPI2 0x34FB - device pci 13.0 off end # GSPI3 0xA0FD - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 on end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 on + device ref gspi2 off end + device ref gspi3 off end + device ref south_xhci on end + device ref south_xdci on end + device ref shared_ram on end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end - end # CNVi: WiFi 0xA0F0 - A0F3 + end - device pci 15.0 on # I2C0 0xA0E8 + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC1308"" register "name" = ""RTAM"" @@ -263,58 +262,58 @@ register "property_list[0].integer" = "1" device i2c 1a on end end - end # I2C0 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - device pci 17.0 on end # SATA 0xA0D3 - device pci 19.0 off end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 on end # UART2 0xA0C7 - device pci 1c.0 off end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 on end # RP3 0xA0BA - device pci 1c.3 on + end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref heci2 off end + device ref csme1 off end + device ref csme2 off end + device ref heci3 off end + device ref heci4 off end + device ref sata on end + device ref i2c4 off end + device ref i2c5 on end + device ref uart2 on end + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 on end + device ref pcie_rp4 on chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" register "srcclk_pin" = "2" device generic 0 on end end - end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # RP6 0xA0BD - device pci 1c.6 off end # RP7 0xA0BE - device pci 1c.7 off end # RP8 0xA0BF - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - device pci 1e.0 off end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref pcie_rp9 on end + device ref pcie_rp10 off end + device ref pcie_rp11 on end + device ref pcie_rp12 off end + device ref uart0 off end + device ref uart1 off end + device ref gspi0 on end + device ref gspi1 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" device spi 0 on end end - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden # PMC 0xA0A1 + end + device ref p2sb on end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -335,11 +334,11 @@ end end end - end # PMC - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 on end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + device ref gbe off end + device ref tracehub off end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/83244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Gerrit-Change-Number: 83244 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brask/var/bujia: Configure Serial IO UARTs Mode
by 9elements QA (Code Review) 28 Jun '24

28 Jun '24

9elements QA has posted comments on this change by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/83205?usp=email ) Change subject: mb/google/brask/var/bujia: Configure Serial IO UARTs Mode ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/212034 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/212032 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/212031 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/212030 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/212029 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/212028 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/212027 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/212026 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/212025 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/212024 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/212023 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/212022 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/83205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38 Gerrit-Change-Number: 83205 Gerrit-PatchSet: 6 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Jun 2024 19:09:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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