coreboot-gerrit June 2024

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[S] Change in coreboot[main]: commonlib/bsd/lz4_wrapper.c: Fix misaligned access
by Angel Pons (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Arthur Heymans, Julius Werner, Maximilian Brune, Nico Huber, Philipp Hug, Ron Minnich. Angel Pons has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/81910?usp=email ) Change subject: commonlib/bsd/lz4_wrapper.c: Fix misaligned access ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Gerrit-Change-Number: 81910 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 21:47:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: commonlib/bsd/lz4_wrapper.c: Fix misaligned access
by Maximilian Brune (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Julius Werner, Nico Huber, Philipp Hug, Ron Minnich. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/81910?usp=email ) Change subject: commonlib/bsd/lz4_wrapper.c: Fix misaligned access ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81910/comment/f8dd42b3_3b307e70?us… : PS1, Line 18: The coreboot LZ4 decompression code does some misaligned access during : decompression > Hmmm... fine. […] Done File src/commonlib/bsd/lz4_wrapper.c: https://review.coreboot.org/c/coreboot/+/81910/comment/11278048_7535c71a?us… : PS5, Line 10: /* LZ4 comes with its own supposedly portable memory access functions, but they : * seem to be very inefficient in practice (at least on ARM64). Since coreboot : * knows about endianness and allows some basic assumptions (such as unaligned : * access support), we can easily write the ones we need ourselves. */ > This comment seems to be inaccurate now. They now reflect the discussions in the comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/81910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Gerrit-Change-Number: 81910 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 21:36:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: commonlib/bsd/lz4_wrapper.c: Fix misaligned access
by Maximilian Brune (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Julius Werner, Maximilian Brune, Nico Huber, Philipp Hug, Ron Minnich. Hello Angel Pons, Arthur Heymans, Nico Huber, Philipp Hug, Ron Minnich, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81910?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+1 by Arthur Heymans, Code-Review+2 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: commonlib/bsd/lz4_wrapper.c: Fix misaligned access ...................................................................... commonlib/bsd/lz4_wrapper.c: Fix misaligned access Currently the HiFive Unleashed produces the following exception: [DEBUG] Exception: Load address misaligned [DEBUG] Hart ID: 0 [DEBUG] Previous mode: machine [DEBUG] Bad instruction pc: 0x080010d0 [DEBUG] Bad address: 0x08026ab3 [DEBUG] Stored ra: 0x080010c8 [DEBUG] Stored sp: 0x08010cc8 The coreboot LZ4 decompression code does some misaligned access during decompression which the FU540 apparently does not support in SRAM. Make the compiler generate code that adheres to natural alignment by fixing the LZ4_readLE16() function and creating LZ4_readLE32(). Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add --- M src/commonlib/bsd/lz4_wrapper.c 1 file changed, 21 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81910/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Gerrit-Change-Number: 81910 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[M] Change in coreboot[main]: tgl mainboards: Move PCIe root port settings into their device scope
by Felix Singer (Code Review) 29 Jun '24

29 Jun '24

Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83253?usp=email ) Change subject: tgl mainboards: Move PCIe root port settings into their device scope ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/83253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I110cc95d536cb0fd3b5db85b84cca7a96e31401c Gerrit-Change-Number: 83253 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 29 Jun 2024 21:05:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: tgl mainboards: Move audio related settings into hda device scope
by Elyes Haouas (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Felix Singer, Nick Vaccaro. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83251?usp=email ) Change subject: tgl mainboards: Move audio related settings into hda device scope ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd Gerrit-Change-Number: 83251 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 29 Jun 2024 20:09:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/common: Add fpt_support to override CSME and HECI disables
by Sean Rhodes (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83265?usp=email ) Change subject: soc/intel/common: Add fpt_support to override CSME and HECI disables ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/83265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I695fa96c5057303730492139904dfcc1d989880b Gerrit-Change-Number: 83265 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 20:06:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: tgl mainboards: Move genx_dec settings into eSPI device scope
by Felix Singer (Code Review) 29 Jun '24

29 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83247?usp=email ) Change subject: tgl mainboards: Move genx_dec settings into eSPI device scope ...................................................................... tgl mainboards: Move genx_dec settings into eSPI device scope Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83247 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 18 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 0b3568b..df13fef 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -93,12 +93,6 @@ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # NVMe PCIE 9 using clk 0 register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" @@ -508,6 +502,12 @@ end # FPMCU end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1bce4b2..af16f75 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -17,12 +17,6 @@ # CPU replacement check register "CpuReplacementCheck" = "1" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" @@ -303,6 +297,12 @@ end end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7a31098..3a80c51 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -17,12 +17,6 @@ # CPU replacement check register "CpuReplacementCheck" = "1" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" @@ -308,6 +302,12 @@ end end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] -- To view, visit https://review.coreboot.org/c/coreboot/+/83247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Gerrit-Change-Number: 83247 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
by Felix Singer (Code Review) 29 Jun '24

29 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83245?usp=email ) Change subject: tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope ...................................................................... tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/collis/overridetree.cb M src/mainboard/google/volteer/variants/copano/overridetree.cb M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/drobit/overridetree.cb M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/halvor/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/todor/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/google/volteer/variants/volet/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 18 files changed, 210 insertions(+), 173 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8bf1c7d..0b3568b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -90,19 +90,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera - register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" @@ -437,7 +424,24 @@ end # DPTF 0x9A03 device ref gna on end device ref north_xhci on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // Type-A Port A0 + [1] = USB2_PORT_MID(OC_SKIP), // Type-A Port A1 + [2] = USB2_PORT_MID(OC_SKIP), // M.2 WWAN + [3] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C Cl + [4] = USB2_PORT_MID(OC_SKIP), // M.2 Camera + [8] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C Co + [9] = USB2_PORT_MID(OC_SKIP), // M.2 Bluetooth + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC1), // USB3/2 Type A port A0 + [1] = USB3_PORT_DEFAULT(OC2), // USB3/2 Type A port A1 + [2] = USB3_PORT_DEFAULT(OC_SKIP), // M.2 WWAN + [3] = USB3_PORT_DEFAULT(OC_SKIP), // M.2 Camera + }" + end device ref shared_ram on end device ref cnvi_wifi on chip drivers/wifi/generic diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 53ed651..fc5d6ab 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -66,15 +66,6 @@ }, }" - # Disable M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_EMPTY" - - # Type-A / Type-C C1 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" - - # Type-A / Type-C C0 - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" - device domain 0 on device ref dptf on chip drivers/intel/dptf @@ -146,6 +137,12 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [2] = USB2_PORT_EMPTY, // Disable M.2 WWAN + [3] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C1 + [8] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C0 + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/collis/overridetree.cb b/src/mainboard/google/volteer/variants/collis/overridetree.cb index a50274f..ab4137e 100644 --- a/src/mainboard/google/volteer/variants/collis/overridetree.cb +++ b/src/mainboard/google/volteer/variants/collis/overridetree.cb @@ -15,15 +15,6 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # Type-A Port A0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-A Port A1 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port C1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # Type-C Port C0 - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WFC Camera - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type-A Port A0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type-A Port A1 - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" @@ -248,6 +239,20 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC1), // Type-A Port A0 + [1] = USB2_PORT_TYPE_C(OC2), // Type-A Port A1 + [2] = USB2_PORT_TYPE_C(OC0), // Type-C Port C1 + [3] = USB2_PORT_MID(OC_SKIP), // Front Camera + [4] = USB2_PORT_TYPE_C(OC3), // Type-C Port C0 + [5] = USB2_PORT_MID(OC_SKIP), // WFC Camera + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC1), // USB3/2 Type-A Port A0 + [1] = USB3_PORT_DEFAULT(OC2), // USB3/2 Type-A Port A1 + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index 87abc9b..619b203 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -12,13 +12,6 @@ # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" @@ -273,6 +266,15 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), // Type-A / Type-C Port 0 + [2] = USB2_PORT_TYPE_C(OC1), // Type-A / Type-C Port 1 + [3] = USB2_PORT_MID(OC_SKIP), // Front Camera + [4] = USB2_PORT_TYPE_C(OC0), // Type-A / Type-C Port 0 + }" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index cc970f7..c4f915c 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -51,16 +51,6 @@ }, }, }" - #These settings improve the USB2 Port1 eye diagram - register "usb2_ports[3]" = "{ - .enable = 1, - .tx_bias = USB2_BIAS_28P15MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_56P3MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - .type_c = 1, - }" - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" register "tcc_offset" = "8" @@ -255,6 +245,20 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + // These settings improve the USB2 Port4 eye diagram + [3] = { + .enable = 1, + .tx_bias = USB2_BIAS_28P15MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_56P3MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, + }, + [8] = USB2_PORT_TYPE_C(OC_SKIP), + }" + + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index e8bb664..aefe141 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -17,9 +17,6 @@ .tdp_pl4 = 105, }" - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # Type-C port 1 - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" # Type-C port 0 - #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -260,6 +257,11 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [3] = USB2_PORT_TYPE_C(OC0), // Type-C port 1 + [8] = USB2_PORT_TYPE_C(OC3), // Type-C port 0 + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 7bb91ea..2b2f32c 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -59,36 +59,6 @@ }, }" - #Disable Type-A Port A1 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" - - #Disable M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_EMPTY" - - #improve the USB2 Port1 eye diagram - register "usb2_ports[3]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_39P35MV, - .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_39P35MV, - .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, - .type_c = 1, - }" - - #lower camera driving - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_EMP_OFF, - .pre_emp_bias = USB2_BIAS_0MV, - .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, - }" - - #Type-A / Type-C C0 - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" - device domain 0 on device ref dptf on # DPTF Policy for Eldrid board @@ -252,6 +222,35 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [1] = USB2_PORT_EMPTY, // Disable Type-A Port A1 + [2] = USB2_PORT_EMPTY, // Disable M.2 WWAN + + // improve the USB2 Port1 eye diagram + [3] = { + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_39P35MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_39P35MV, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + .type_c = 1, + }, + + // lower camera driving + [4] = { + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_EMP_OFF, + .pre_emp_bias = USB2_BIAS_0MV, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }, + + // Type-A / Type-C C0 + [8] = USB2_PORT_TYPE_C(OC_SKIP), + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 4adf76a..5eef9ef 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -66,15 +66,6 @@ }, }" - # Disable M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_EMPTY" - - # Type-A / Type-C C1 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" - - # Type-A / Type-C C0 - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" - device domain 0 on device ref dptf on chip drivers/intel/dptf @@ -146,6 +137,12 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [2] = USB2_PORT_EMPTY, // Disable M.2 WWAN + [3] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C1 + [8] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C0 + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 138d557..589dfaf 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -1,10 +1,4 @@ chip soc/intel/tigerlake - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 0 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 2 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Reserve for CNVi BT - register "SaGv" = "SaGv_Disabled" device domain 0 on @@ -128,6 +122,14 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [1] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C Port 0 + [3] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C Port 1 + [4] = USB2_PORT_MID(OC_SKIP), // Front Camera + [5] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C Port 2 + [9] = USB2_PORT_MID(OC_SKIP), // Reserve for CNVi BT + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index b74bb23..2229af7 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -4,15 +4,6 @@ register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" - # USB Port Config - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -327,6 +318,16 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // Type-A Port A0 + [3] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C1 + [4] = USB2_PORT_MID(OC_SKIP), // M.2 Camera + [8] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C0 + [9] = USB2_PORT_MID(OC_SKIP), // M.2 Bluetooth + }" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index 62d8190..1942657 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -1,14 +1,5 @@ chip soc/intel/tigerlake - # USB Port Config - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - register "SaGv" = "SaGv_Disabled" register "TcssAuxOri" = "1" @@ -113,6 +104,16 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // Type-A Port A0 + [3] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C C1 + [4] = USB2_PORT_MID(OC_SKIP), // M.2 Camera + [8] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C C0 + [9] = USB2_PORT_MID(OC_SKIP), // M.2 Bluetooth + }" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 4113db7..4b814eb 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -5,15 +5,6 @@ # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" @@ -195,6 +186,19 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), // Type-A / Type-C Port 0 + [1] = USB2_PORT_TYPE_C(OC1), // Type-A / Type-C Port 1 + [2] = USB2_PORT_TYPE_C(OC1), // Type-A / Type-C Port 1 + [3] = USB2_PORT_MID(OC_SKIP), // Front Camera + [4] = USB2_PORT_TYPE_C(OC0), // Type-A / Type-C Port 0 + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-A / Type-C Port 0 + [1] = USB3_PORT_DEFAULT(OC1), // Type-A / Type-C Port 1 + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index f500e9a..c511fed 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -5,21 +5,26 @@ # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "SaGv" = "SaGv_Disabled" # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), // Type-A / Type-C Port 0 + [1] = USB2_PORT_TYPE_C(OC1), // Type-A / Type-C Port 1 + [2] = USB2_PORT_TYPE_C(OC1), // Type-A / Type-C Port 1 + [3] = USB2_PORT_MID(OC_SKIP), // Front Camera + [4] = USB2_PORT_TYPE_C(OC0), // Type-A / Type-C Port 0 + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-A / Type-C Port 0 + [1] = USB3_PORT_DEFAULT(OC1), // Type-A / Type-C Port 1 + }" + end device ref dptf on chip drivers/intel/dptf ## Disable Active Policy diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 4c83c7e..97160ee 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -5,9 +5,6 @@ # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 1 - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 0 - register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" @@ -159,6 +156,11 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [2] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C Port 1 + [4] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C Port 0 + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/volet/overridetree.cb b/src/mainboard/google/volteer/variants/volet/overridetree.cb index 52a198e..7125f40 100644 --- a/src/mainboard/google/volteer/variants/volet/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volet/overridetree.cb @@ -2,9 +2,6 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Cl - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C0 - register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" @@ -185,6 +182,11 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [3] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C Cl + [8] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C0 + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index b517ba2..8367533 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -13,9 +13,6 @@ .tdp_pl4 = 105, }" - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Cl - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C0 - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" @@ -280,6 +277,11 @@ end end device ref south_xhci on + register "usb2_ports" = "{ + [3] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C Cl + [8] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C0 + }" + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index ecad52e..1bce4b2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -14,20 +14,6 @@ # CNVi BT enable/disable register "CnviBtCore" = "true" - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3 - register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - # CPU replacement check register "CpuReplacementCheck" = "1" @@ -206,7 +192,25 @@ end device ref gspi2 off end device ref gspi3 off end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), // Type-C Port1 + [1] = USB2_PORT_EMPTY, // M.2 WWAN + [2] = USB2_PORT_MID(OC3), // M.2 Bluetooth + [3] = USB2_PORT_MID(OC0), // USB3/2 Type A port1 + [4] = USB2_PORT_MID(OC0), // Type-C Port2 + [5] = USB2_PORT_MID(OC3), // Type-C Port3 + [6] = USB2_PORT_MID(OC3), // Type-C Port4 + [7] = USB2_PORT_MID(OC0), // USB3/2 Type A port2 + [8] = USB2_PORT_MID(OC3), // USB2 Type A port3 + [9] = USB2_PORT_MID(OC3), // USB2 Type A port4 + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // USB3/2 Type A port1 + [1] = USB3_PORT_DEFAULT(OC0), // USB3/2 Type A port2 + }" + end device ref south_xdci on end device ref shared_ram on end device ref cnvi_wifi on diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 4a523a7a..7a31098 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -14,21 +14,6 @@ # CNVi BT enable/disable register "CnviBtCore" = "true" - register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used - register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector - # CPU replacement check register "CpuReplacementCheck" = "1" @@ -215,7 +200,26 @@ end device ref gspi2 off end device ref gspi3 off end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC3), // Type-C Port1 + [1] = USB2_PORT_EMPTY, // M.2 WWAN + [2] = USB2_PORT_MID(OC0), // M.2 Bluetooth, USB3/2 Type A Port1 + [3] = USB2_PORT_MID(OC3), // USB3/2 Type A Port 1 + [4] = USB2_PORT_MID(OC3), // Type-C Port2 + [5] = USB2_PORT_MID(OC3), // Type-C Port3 / MECC + [6] = USB2_PORT_EMPTY, // Not used + [7] = USB2_PORT_EMPTY, // Not used + [8] = USB2_PORT_EMPTY, // Not used + [9] = USB2_PORT_MID(OC3), // CNVi/BT + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // USB3/2 Type A port1 + [1] = USB3_PORT_DEFAULT(OC0), // USB3/2 Type A port2 + [3] = USB3_PORT_DEFAULT(OC3), // USB3/USB2 Flex Connector + }" + end device ref south_xdci on end device ref shared_ram on end device ref cnvi_wifi on -- To view, visit https://review.coreboot.org/c/coreboot/+/83245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a Gerrit-Change-Number: 83245 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: tgl mainboards: Move genx_dec settings into eSPI device scope
by Elyes Haouas (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Felix Singer, Nick Vaccaro. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83247?usp=email ) Change subject: tgl mainboards: Move genx_dec settings into eSPI device scope ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Gerrit-Change-Number: 83247 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 29 Jun 2024 19:52:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
by Elyes Haouas (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Felix Singer, Nick Vaccaro. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83245?usp=email ) Change subject: tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a Gerrit-Change-Number: 83245 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 29 Jun 2024 19:46:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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