coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
by Federico Amedeo Izzo (Code Review) 29 Jun '24

29 Jun '24

Federico Amedeo Izzo has posted comments on this change by Federico Amedeo Izzo. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: > I'm on vacation for the next two weeks (till July 17th). […] I uploaded the two logs for two different commits. It's the first time I'm doing this, hope everything's alright. -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 17 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 16:36:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Federico Amedeo Izzo <federico(a)izzo.pro>

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[S] Change in coreboot[main]: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
by Shuo Liu (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82264?usp=email ) Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space ...................................................................... Patch Set 8: (1 comment) File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/82264/comment/a66a6528_60c288fb?us… : PS8, Line 203: soc_fill_uc_holes_in_physical_address_space(addr_space); > Putting MMIO high above the DRAM seems common. And I assume we'll see […] Thanks for the suggestions, I tentatively made https://review.coreboot.org/c/coreboot/+/83264. -- To view, visit https://review.coreboot.org/c/coreboot/+/82264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4be85e79007fd1ccf5882de4dfeaeacd98a4db Gerrit-Change-Number: 82264 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 11:50:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[M] Change in coreboot[main]: cpu/x86/mtrr: Fill holes for above 4G MMIO window
by Shuo Liu (Code Review) 29 Jun '24

29 Jun '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83264?usp=email ) Change subject: cpu/x86/mtrr: Fill holes for above 4G MMIO window ...................................................................... cpu/x86/mtrr: Fill holes for above 4G MMIO window Many SoCs will have MMIO high window above 4G, fill holes for them as well to avoid MTRR segmentation and MTRR register insufficiency. Change-Id: If7d9a91cfb1c5cf1bd21d62775de4eafb7b90aba Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 96 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/83264/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 6d726f5..ae5f379 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -20,6 +20,7 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci_ids.h> +#include <lib.h> #include <memrange.h> #include <string.h> #include <types.h> @@ -159,6 +160,84 @@ range_entry_size(r), range_entry_tag(r)); } +static struct range_entry *detect_mmio_high_window(struct range_entry *entry, + resource_t *base, resource_t *limit) +{ + resource_t mmio_min, mmio_max; + mmio_min = mmio_max = 0; + + struct range_entry *cur, *prev, *ahead; + prev = ahead = NULL; + + for (cur = entry; cur != NULL; cur = cur->next) { + if (!prev) { + prev = cur; + continue; + } + if (cur->begin < RANGE_TO_PHYS_ADDR(RANGE_4GB)) + continue; + + if (cur->tag != MTRR_TYPE_UNCACHEABLE) { + if (mmio_min && mmio_max) + break; + } else { + if (!mmio_min) { + mmio_min = cur->begin; + ahead = prev; + } + mmio_max = cur->end; + } + + prev = cur; + } + + if ((!mmio_min) && (!mmio_max)) + return NULL; + + printk(BIOS_DEBUG, "detected MMIO high window: %llx - %llx\n", mmio_min, mmio_max); + + /* Expand the region downwards for better power of 2 MTRR coverage */ + resource_t low = range_entry_end(ahead); + resource_t high = mmio_min; + resource_t mmio_temp, mmio_base = 0; + resource_t temp = (1ULL << log2_64(mmio_min)); + while (temp) { + mmio_temp = mmio_base + temp; + if (mmio_temp <= high) + mmio_base = mmio_temp; + if (mmio_base >= low) + break; + temp >>= 1; + } + + low = mmio_max; + high = cur->next ? (cur->next->begin - 1) : ((1ULL << cpu_phys_address_size()) - 1); + temp = (1ULL << log2_64(mmio_max)); + resource_t mmio_limit = 0; + while (temp) { + mmio_temp = mmio_limit + temp; + if (mmio_temp <= high) + mmio_limit = mmio_temp; + if (mmio_limit >= low) + break; + temp >>= 1; + } + + /* round the window size to 4KB */ + mmio_limit -= (mmio_limit - mmio_base + 1) & (4 * KiB - 1); + if (mmio_limit < mmio_max) + mmio_limit = mmio_max; + + printk(BIOS_DEBUG, "expanded MMIO high window: %llx - %llx\n", mmio_base, mmio_limit); + + if (base) + *base = mmio_base; + if (limit) + *limit = mmio_limit; + + return cur; +} + static struct memranges *get_physical_address_space(void) { static struct memranges *addr_space; @@ -197,6 +276,23 @@ RANGE_TO_PHYS_ADDR(RANGE_4GB), MTRR_TYPE_UNCACHEABLE); + /* + * Many SoCs will have MMIO high window above 4G, fill holes for + * them as well to avoid MTRR segmentation and MTRR register + * insufficiency */ + struct range_entry *entry = addr_space->entries; + do { + resource_t mmio_high_base = 0; + resource_t mmio_high_limit = 0; + entry = detect_mmio_high_window(entry, + &mmio_high_base, &mmio_high_limit); + if (mmio_high_base >= RANGE_TO_PHYS_ADDR(RANGE_4GB) && + mmio_high_base <= mmio_high_limit) + memranges_fill_holes_from_to(addr_space, mmio_high_base, + mmio_high_limit + 1, + MTRR_TYPE_UNCACHEABLE); + } while (entry); + print_physical_address_space(addr_space, NULL); } -- To view, visit https://review.coreboot.org/c/coreboot/+/83264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d9a91cfb1c5cf1bd21d62775de4eafb7b90aba Gerrit-Change-Number: 83264 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Subrata Banik (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Sowmya Aralguppe, Tarun. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (1 comment) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/84d158e3_9205917d?us… : PS22, Line 352: + 4 > line 354 is already checking for 0 size. I think we should also check for deadbeef, its pretty easy check. > > I assume you triggered a fake crashlog and was able to parse/decode the crashlog data. I have asked for a testcase where we are able to trigger crashlog after every CSE global reset and use the crashlog tool to parse the end result. ideally we don't wish to see any regression. -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 11:09:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[XS] Change in coreboot[main]: soc/sifive/fu540/sdram.c: Remove unused macro
by Elyes Haouas (Code Review) 29 Jun '24

29 Jun '24

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/82927?usp=email ) Change subject: soc/sifive/fu540/sdram.c: Remove unused macro ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/82927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie590df960455d3c7eca320eca1d95eb5d8236fd5 Gerrit-Change-Number: 82927 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Angel Pons (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Nicholas Chin, Nicholas Sudsgaard. Angel Pons has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80411?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Patch Set 22: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 22 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 08:02:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)
by Simon Glass (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Arthur Heymans, Felix Held, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel, Simon Glass. Simon Glass has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Introduce a coreboot Control Block (CCB) ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > and yes, i do see value in having the ccb as an optional mechanism; my concerns are about how the da […] Yes it can be done with FMAP but it does create a lot of new code. I will see what can be done to reduce it. Putting it in the bootblock is easiest to implement, a CBFS file next easiest and its own section somewhat more painful. -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 29 Jun 2024 07:21:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: Makefile.mk: Use one line per *_common flag
by Felix Singer (Code Review) 29 Jun '24

29 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83226?usp=email ) Change subject: Makefile.mk: Use one line per *_common flag ...................................................................... Makefile.mk: Use one line per *_common flag Use one line per *_common flag like it's done elsewhere in the tree. It makes the list of options more readable. Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83226 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M Makefile.mk 1 file changed, 52 insertions(+), 15 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/Makefile.mk b/Makefile.mk index 16b6539..1b658b5 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -475,7 +475,11 @@ COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION endif -CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -I$(obj) +CPPFLAGS_common := -Isrc +CPPFLAGS_common += -Isrc/include +CPPFLAGS_common += -Isrc/commonlib/include +CPPFLAGS_common += -Isrc/commonlib/bsd/include +CPPFLAGS_common += -I$(obj) VBOOT_SOURCE ?= 3rdparty/vboot CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h @@ -493,13 +497,34 @@ CPPFLAGS_ramstage += -Isrc/device/oprom/include endif -CFLAGS_common += -pipe -g -nostdinc -std=gnu11 -CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition -CFLAGS_common += -Wdangling-else -Wmissing-include-dirs -CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie +CFLAGS_common += -pipe +CFLAGS_common += -g +CFLAGS_common += -nostdinc +CFLAGS_common += -std=gnu11 +CFLAGS_common += -nostdlib +CFLAGS_common += -Wall +CFLAGS_common += -Wundef +CFLAGS_common += -Wstrict-prototypes +CFLAGS_common += -Wmissing-prototypes +CFLAGS_common += -Wwrite-strings +CFLAGS_common += -Wredundant-decls +CFLAGS_common += -Wno-trigraphs +CFLAGS_common += -Wimplicit-fallthrough +CFLAGS_common += -Wshadow +CFLAGS_common += -Wdate-time +CFLAGS_common += -Wtype-limits +CFLAGS_common += -Wvla +CFLAGS_common += -Wold-style-definition +CFLAGS_common += -Wdangling-else +CFLAGS_common += -Wmissing-include-dirs +CFLAGS_common += -fno-common +CFLAGS_common += -ffreestanding +CFLAGS_common += -fno-builtin +CFLAGS_common += -fomit-frame-pointer +CFLAGS_common += -fstrict-aliasing +CFLAGS_common += -ffunction-sections +CFLAGS_common += -fdata-sections +CFLAGS_common += -fno-pie CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_common += -Wold-style-declaration @@ -508,16 +533,25 @@ CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack CFLAGS_common += -Wnull-dereference -CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare +CFLAGS_common += -Wlogical-op +CFLAGS_common += -Wduplicated-cond +CFLAGS_common += -Wno-array-compare endif endif ADAFLAGS_common += -gnatp -ADAFLAGS_common += -Wuninitialized -Wall -Werror -ADAFLAGS_common += -pipe -g -nostdinc -ADAFLAGS_common += -Wstrict-aliasing -Wshadow -ADAFLAGS_common += -fno-common -fomit-frame-pointer -ADAFLAGS_common += -ffunction-sections -fdata-sections +ADAFLAGS_common += -Wuninitialized +ADAFLAGS_common += -Wall +ADAFLAGS_common += -Werror +ADAFLAGS_common += -pipe +ADAFLAGS_common += -g +ADAFLAGS_common += -nostdinc +ADAFLAGS_common += -Wstrict-aliasing +ADAFLAGS_common += -Wshadow +ADAFLAGS_common += -fno-common +ADAFLAGS_common += -fomit-frame-pointer +ADAFLAGS_common += -ffunction-sections +ADAFLAGS_common += -fdata-sections ADAFLAGS_common += -fno-pie # Ada warning options: # @@ -557,7 +591,10 @@ # Disable style checks for now ADAFLAGS_common += -gnatyN -LDFLAGS_common := --gc-sections -nostdlib --nmagic -static +LDFLAGS_common := --gc-sections +LDFLAGS_common += -nostdlib +LDFLAGS_common += --nmagic +LDFLAGS_common += -static # Workaround for RISC-V linker bug, merge back into above line when fixed. # https://sourceware.org/bugzilla/show_bug.cgi?id=27180 -- To view, visit https://review.coreboot.org/c/coreboot/+/83226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d Gerrit-Change-Number: 83226 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Angel Pons, Nicholas Chin. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80411?usp=email to look at the new patch set (#22). Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M710s Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/thinkcentre_m710s.md A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg 3 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/80411/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 22 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Angel Pons, Nicholas Chin. Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80411?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Patch Set 21: (5 comments) File Documentation/mainboard/index.md: https://review.coreboot.org/c/coreboot/+/80411/comment/7000b471_efafd923?us… : PS17, Line 106: - [ThinkCentre M710s](lenovo/thinkcentre_m710s) > This needs to be updated for the new toctree format as of commit 35599f9a6671 (Docs: Replace Recommo […] Done File Documentation/mainboard/lenovo/thinkcentre_m710s.md: https://review.coreboot.org/c/coreboot/+/80411/comment/b9a09031_59ee9543?us… : PS20, Line 7: ```eval_rst > As per CB:83117 […] Done https://review.coreboot.org/c/coreboot/+/80411/comment/2811617b_39f4c930?us… : PS20, Line 28: Programming > nit: Flashing Done https://review.coreboot.org/c/coreboot/+/80411/comment/11869b5c_7e9802f9?us… : PS20, Line 30: using the > nit […] Done https://review.coreboot.org/c/coreboot/+/80411/comment/9ee5c40a_9cdf5526?us… : PS20, Line 47: Tianocore's EDK 2 > Does "Tianocore" mean https://github. […] Yes, I just did some testing and MrChromebox's fork seems to work as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 21 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 01:07:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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