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Hello build bot (Jenkins),
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The following approvals got outdated and were removed:
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Change subject: util/ifdtool: Support the DCI enable bit on Skylake/Kaby Lake
......................................................................
util/ifdtool: Support the DCI enable bit on Skylake/Kaby Lake
- DCI can also be enabled from firmware via IOSF-SB
(port 0xb8 byte 4 bit 4).
- Firmware has to set bit 0 of the IA32_DEBUG_INTERFACE
(0xc80) MSR to consent to the CPU being debugged.
- DCI can be used to debug coreboot either using:
- SVT CCA adapter (aka blue box)
- Regular USB3 A-to-A cable with the VCC pin removed
- Setting this bit will cause the ME firmware to enable DCI, before
the big CPU comes out of reset.
- The file "/home/mca/eom" in the ME's MFS file system has to contain
b"\x00" for the ME firmware to honor this bit.
(For DCI enable changing the filesystem is enough, the state of FPFs
does not matter.)
- Tested on Dell OptiPlex 3050 and Lenovo ThinkPad T480
Change-Id: I242484e7008bb453cb9a0dc186c8a75e6c96e3d3
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
---
M util/ifdtool/ifdtool.c
1 file changed, 99 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/82272/4
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82736?usp=email
to look at the new patch set (#3).
Change subject: Makefile.mk: Use Wcast-function-type GCC option
......................................................................
Makefile.mk: Use Wcast-function-type GCC option
Change-Id: I25415d7fd82879889ffaa1bb534ad5d0b174854e
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M Makefile.mk
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/82736/3
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Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82736?usp=email )
Change subject: Makefile.mk: Use Wcast-function-type command option
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82736/comment/05926a18_5ee64adc?us… :
PS2, Line 7: command
> Maybe say GCC?
Acknowledged
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82734?usp=email
to look at the new patch set (#3).
Change subject: Makefile.mk: Use Walloc-size GCC option
......................................................................
Makefile.mk: Use Walloc-size GCC option
Change-Id: Ia26dcf097db125a5a734660d08d875459179241b
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M Makefile.mk
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/82734/3
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Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82734?usp=email )
Change subject: Makefile.mk: Use Walloc-size command option
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82734/comment/4dc8152e_95c1272c?us… :
PS2, Line 7: command
> Maybe say GCC?
to be exact, it's more like "GCC command option", but I have no objection to your suggestion ;)
https://gcc.gnu.org/onlinedocs/gcc-14.1.0/gcc/#toc-GCC-Command-Options
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Attention is currently required from: Angel Pons, Arthur Heymans, Julius Werner, Maximilian Brune, Philipp Hug, Ron Minnich.
Nico Huber has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/81910?usp=email )
Change subject: commonlib/bsd/lz4_wrapper.c: Fix misaligned access
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
File src/commonlib/bsd/lz4_wrapper.c:
https://review.coreboot.org/c/coreboot/+/81910/comment/564fbf68_4f4ee0e9?us… :
PS5, Line 10: /* LZ4 comes with its own supposedly portable memory access functions, but they
: * seem to be very inefficient in practice (at least on ARM64). Since coreboot
: * knows about endianness and allows some basic assumptions (such as unaligned
: * access support), we can easily write the ones we need ourselves. */
> They now reflect the discussions in the comments.
I have a feeling that the orginal comment meant to include LZ4_copy8().
I don't mind the change, though. Seems less complicated than having to
guess what a comment applies to exactly.
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Change subject: mb/msi/ms7d25,ms7e06: Enable discrete TPM module support
......................................................................
Patch Set 5: Code-Review+2
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Change subject: lib: Add Kconfig variable for fw_config default value
......................................................................
Patch Set 6: Code-Review-1
(1 comment)
Patchset:
PS6:
Please file a bug to have more specific discussion which I'm unable to follow here.
I sense you are trying to boot windows SKU with same binary as Chrome SKU hence, you would like to unify things just for it to be unified.
CBI is specific to chrome design and ideally the same shouldn't exist unless implemented now I would like to ensure FW_CBI config is not at all enabled for all windows SKU. The downside would be, all probe function should fail.
to fix that problem, you need a dedicated devicetree file for booting to Windows SKU. There may be more req from Intel which I'm missing here, hence, please don't rush for the review/merge unless we have good understanding of the requirement.
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