June 2024 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[main]: tree: Add some SMBIOS_PROCESSOR_FAMILY macros
by Elyes Haouas (Code Review) June 1, 2024

June 1, 2024

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82648?usp=email ) Change subject: tree: Add some SMBIOS_PROCESSOR_FAMILY macros ...................................................................... tree: Add some SMBIOS_PROCESSOR_FAMILY macros Change-Id: Ibe551a4c83f416ba30326077aa165818cf79c1fd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82648 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/arm64/smbios.c M src/arch/x86/smbios.c M src/include/smbios.h 3 files changed, 9 insertions(+), 3 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/arch/arm64/smbios.c b/src/arch/arm64/smbios.c index a8d0523..f0be956 100644 --- a/src/arch/arm64/smbios.c +++ b/src/arch/arm64/smbios.c @@ -66,8 +66,8 @@ smbios_processor_id(t->processor_id); t->processor_manufacturer = smbios_processor_manufacturer(t->eos); t->processor_version = smbios_processor_name(t->eos); - t->processor_family = 0xfe; /* Use processor_family2 field */ - t->processor_family2 = 0x101; /* ARMv8 */ + t->processor_family = SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2; + t->processor_family2 = SMBIOS_PROCESSOR_FAMILY2_ARMV8; t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL; smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index ef2c19a..4fa8612 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -68,7 +68,7 @@ unsigned int __weak smbios_processor_family(struct cpuid_result res) { - return (res.eax > 0) ? 0x0c : 0x6; + return (res.eax > 0) ? SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO : SMBIOS_PROCESSOR_FAMILY_INTEL486; } static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache) diff --git a/src/include/smbios.h b/src/include/smbios.h index 0fe2b9c..8ef37d8 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -584,7 +584,13 @@ /* defines for processor family */ #define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01 #define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02 +#define SMBIOS_PROCESSOR_FAMILY_INTEL486 0x06 +#define SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO 0x0c #define SMBIOS_PROCESSOR_FAMILY_XEON 0xb3 +#define SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2 0xfe + +/* defines for processor family 2 */ +#define SMBIOS_PROCESSOR_FAMILY2_ARMV8 0x101 /* defines for processor characteristics */ #define PROCESSOR_64BIT_CAPABLE (1 << 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/82648?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe551a4c83f416ba30326077aa165818cf79c1fd Gerrit-Change-Number: 82648 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: [test xcompile] fix scan-build for x86
by Elyes Haouas (Code Review) June 1, 2024

June 1, 2024

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/82575?usp=email ) Change subject: [test xcompile] fix scan-build for x86 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/82575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb81d16c4883004aa2fa2dd0323b935492bafd58 Gerrit-Change-Number: 82575 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Enable USB2 port reset message on Type-C ports
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82730?usp=email to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Enable USB2 port reset message on Type-C ports ...................................................................... soc/intel/meteorlake: Enable USB2 port reset message on Type-C ports Apply commit c6b65c1a811e ("soc/intel/alderlake: Enable USB2 port reset message on Type-C ports") to Meteor Lake. This change is added to address the issue of USB3 ports downgrading to high speed during low power modes and not returning back to super speed. The patch enables port reset event on USB2 ports. This event is is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. Change-Id: Iac702a8d8edd2b3b7e03abcac020be7e45335821 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/include/soc/usb.h 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/82730/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac702a8d8edd2b3b7e03abcac020be7e45335821 Gerrit-Change-Number: 82730 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[M] Change in coreboot[main]: device_tree: Add function to get top of memory from a FDT blob
by Maximilian Brune (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Alper Nebi Yasak, Jakub Czapiga, Nico Huber. Maximilian Brune has posted comments on this change by Alper Nebi Yasak. ( https://review.coreboot.org/c/coreboot/+/80322?usp=email ) Change subject: device_tree: Add function to get top of memory from a FDT blob ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Gerrit-Change-Number: 80322 Gerrit-PatchSet: 7 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Jun 2024 01:41:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: mb/novacustom: add V5x0TU board (Meteor Lake)
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Maciej Pijanowski, Michał Kopeć, Michał Żygowski. Tim Crawford has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82673?usp=email ) Change subject: mb/novacustom: add V5x0TU board (Meteor Lake) ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82673/comment/2913aa90_4f406f05?us… : PS8, Line 28: - DDR5 SODIMM in slot RAM1 > https://review.coreboot. […] I've updated CB:52731 and uploaded CB:82733 for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/82673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771 Gerrit-Change-Number: 82673 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Sat, 01 Jun 2024 01:26:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[M] Change in coreboot[main]: soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Jeremy Soller. Hello Jeremy Soller, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/82733?usp=email to review the following change. Change subject: soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory ...................................................................... soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory Apply CB:75284 to Meteor Lake. CB:52731 introduced support for reading SPD from the EEPROM via SMBus. Replace the now unneeded workaround for DDR5 with filling in the correct channels for DDR5. Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/meteorlake/meminit.c 1 file changed, 24 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/82733/1 diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c index 32ab358..2b2edcc 100644 --- a/src/soc/intel/meteorlake/meminit.c +++ b/src/soc/intel/meteorlake/meminit.c @@ -8,7 +8,7 @@ #define LPX_PHYSICAL_CH_WIDTH 16 #define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH) -#define DDR5_PHYSICAL_CH_WIDTH 32 +#define DDR5_PHYSICAL_CH_WIDTH 64 /* 32*2 */ #define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH) static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) @@ -38,18 +38,16 @@ .num_phys_channels = DDR5_CHANNELS, .phys_to_mrc_map = { [0] = 0, - [1] = 1, - [2] = 4, - [3] = 5, + [1] = 4, }, .md_phy_masks = { /* - * Physical channels 0 and 1 are populated in case of - * half-populated configurations. + * Only channel 0 is populated in case of half-populated + * configuration. */ - .half_channel = BIT(0) | BIT(1), - /* In mixed topologies, channels 2 and 3 are always memory-down. */ - .mixed_topo = BIT(2) | BIT(3), + .half_channel = BIT(0), + /* In mixed topologies, either channel 0 or 1 can be memory-down. */ + .mixed_topo = BIT(0) | BIT(1), }, }, [MEM_TYPE_LP5X] = { @@ -75,7 +73,8 @@ }, }; -static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) +static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + bool expand_channels) { efi_uintn_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, @@ -108,7 +107,16 @@ for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { efi_uintn_t *spd_ptr = spd_upds[ch][dimm]; - *spd_ptr = data->spd[ch][dimm]; + // In DDR5 systems, we need to copy the SPD data such that: + // Channel 0 data is used by channel 0 and 1 + // Channel 2 data is used by channel 2 and 3 + // Channel 4 data is used by channel 4 and 5 + // Channel 6 data is used by channel 6 and 7 + if (expand_channels) + *spd_ptr = data->spd[ch & 6][dimm]; + else + *spd_ptr = data->spd[ch][dimm]; + if (*spd_ptr) enable_channel = 1; } @@ -174,27 +182,12 @@ mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); } -#define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm)) - -static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info) -{ - for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) { - for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { - size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch]; - mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] = - spd_info->smbus[ch].addr_dimm[dimm] << 1; - } - } - mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true); - mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); -} - void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; + bool expand_channels = false; FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; mem_cfg->ECT = mb_cfg->ect; @@ -205,14 +198,7 @@ case MEM_TYPE_DDR5: meminit_ddr(mem_cfg, &mb_cfg->ddr_config); dq_dqs_auto_detect = true; - /* - * TODO: Drop this workaround once SMBus driver in coreboot is updated to - * support DDR5 EEPROM reading. - */ - if (spd_info->topo == MEM_TOPO_DIMM_MODULE) { - ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info); - return; - } + expand_channels = true; break; case MEM_TYPE_LP5X: meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config); @@ -221,9 +207,9 @@ die("Unsupported memory type(%d)\n", mb_cfg->type); } - mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, - half_populated, &data); - mem_init_spd_upds(mem_cfg, &data); + mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, + &data); + mem_init_spd_upds(mem_cfg, &data, expand_channels); mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); } -- To view, visit https://review.coreboot.org/c/coreboot/+/82733?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386 Gerrit-Change-Number: 82733 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>

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[M] Change in coreboot[main]: soc/common/smbus: Support reading SPD5 hubs for DDR5
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Angel Pons, Balaji Manigandan, Balaji Manigandan, Eric Lai, Haribalaraman Ramasubramanian, Jeremy Soller, Kapil Porwal, Karthik Ramasubramanian, Kyösti Mälkki, Maulik Vaghela, Meera Ravindranath, Nick Vaccaro, Patrick Rudolph, Paul Menzel, Raj Astekar, Reka Norman, Rizwan Qureshi, Subrata Banik, Subrata Banik, Tarun Tuli, Tim Wawrzynczak. Tim Crawford has posted comments on this change by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/52731?usp=email ) Change subject: soc/common/smbus: Support reading SPD5 hubs for DDR5 ...................................................................... Patch Set 16: (9 comments) Patchset: PS13: > Yes. We have cherry-picked this in order to remove the workaround in `meminit. […] Done Patchset: PS14: > Adding Intel team to take care of this CL Taking over since no one from Intel responded. PS14: > @Meera, any plan to address this ? Guess not. Patchset: PS16: Intel has seemingly abandoned this work, so I've updated with the changes Jeremy has made while working on the Clevo RPL and MTL units. I've moved Meera to co-author for the original work and made Jeremy the commit author, as he has rewritten it as part of the work for adding support for Clevo L240TU (system76/lemp13). Commit Message: https://review.coreboot.org/c/coreboot/+/52731/comment/3b40b37b_1b66f3d8?us… : PS13, Line 7: Add support for reading spd data via smbus for DDR5 > “Add support for” can be substituted by “Support”: […] Done https://review.coreboot.org/c/coreboot/+/52731/comment/f3abba1b_dd72dcc9?us… : PS13, Line 11: This CL adds support to read the spd5 hub device via smbus. > Please add a blank line above to separate the paragraphs. Acknowledged https://review.coreboot.org/c/coreboot/+/52731/comment/d12a4efb_fa2422d5?us… : PS13, Line 14: TEST=Boot adlrvp DDR5 board to kernel > Before it didn’t work? What RAM modules did you test with? Acknowledged File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/52731/comment/7902c4e7_d4e6cd1a?us… : PS13, Line 10: { 0, 1 }, /* General Configuration section */ : { 2, 2 }, /* General Configuration section */ : { 3, 47 }, /* General Configuration section */ > I see, it's inclusive. So yes, they are contiguous. Probably just copied from the FSP then. […] Removed https://review.coreboot.org/c/coreboot/+/52731/comment/159a2814_4b203d03?us… : PS13, Line 54: /* : * By default,an SPD5 hub accepts 1 byte addressing pointing : * to the first 128 bytes of memory. MR11[2:0] selects the page : * pointer to address the entire 1024 bytes of non-volatile memory. : */ > Please use one of the recommended multi-line comment styles. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52731 Gerrit-PatchSet: 16 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 01 Jun 2024 01:22:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Tim Crawford has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75283?usp=email ) Change subject: lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/75283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bdc4c676a0f571fd8f34e078f6a1c73a2e90a87 Gerrit-Change-Number: 75283 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

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[XS] Change in coreboot[main]: lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Jeremy Soller, Paul Menzel. Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/75283?usp=email ) Change subject: lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bdc4c676a0f571fd8f34e078f6a1c73a2e90a87 Gerrit-Change-Number: 75283 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 01 Jun 2024 01:18:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/common/smbus: Support reading SPD5 hubs for DDR5
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Angel Pons, Balaji Manigandan, Balaji Manigandan, Haribalaraman Ramasubramanian, Jeremy Soller, Kapil Porwal, Karthik Ramasubramanian, Kyösti Mälkki, Maulik Vaghela, Meera Ravindranath, Nick Vaccaro, Patrick Rudolph, Raj Astekar, Reka Norman, Rizwan Qureshi, Subrata Banik, Tarun Tuli, Tim Crawford, Tim Wawrzynczak. Tim Crawford has uploaded a new patch set (#16) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/52731?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/common/smbus: Support reading SPD5 hubs for DDR5 ...................................................................... soc/common/smbus: Support reading SPD5 hubs for DDR5 DDR5 uses a Serial Presence Detect (SPD) with hub function (SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`). Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Co-authored-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/include/spd_bin.h M src/lib/spd_cache.c M src/soc/intel/common/block/smbus/smbuslib.c 3 files changed, 95 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/52731/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/52731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52731 Gerrit-PatchSet: 16 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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