coreboot-gerrit June 2024

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow package power limit clamping
by Anastasios Koutian (Code Review) 30 Jun '24

30 Jun '24

Anastasios Koutian has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83270?usp=email ) Change subject: cpu/intel/model_206ax: Allow package power limit clamping ...................................................................... cpu/intel/model_206ax: Allow package power limit clamping Tested on ThinkPad T420 with the i7-3940XM. Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Signed-off-by: Anastasios Koutian <akoutian2(a)gmail.com> --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c 2 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83270/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Gerrit-Change-Number: 83270 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
by Anastasios Koutian (Code Review) 30 Jun '24

30 Jun '24

Anastasios Koutian has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83271?usp=email ) Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration ...................................................................... cpu/intel/model_206ax: Allow turbo boost ratio limit configuration Tested on ThinkPad T420 with the i7-3940XM. Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad Signed-off-by: Anastasios Koutian <akoutian2(a)gmail.com> --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/83271/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad Gerrit-Change-Number: 83271 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: [WIP] OptiPlex 3050 port
by Máté Kukri (Code Review) 30 Jun '24

30 Jun '24

Attention is currently required from: Angel Pons, Felix Singer. Máté Kukri has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: [WIP] OptiPlex 3050 port ...................................................................... Patch Set 11: (10 comments) File src/mainboard/dell/optiplex_3050/Kconfig: https://review.coreboot.org/c/coreboot/+/82053/comment/70374ab2_8a61fefd?us… : PS11, Line 12: # select INTEL_GMA_HAVE_VBT > Is this a FIXME? Yes https://review.coreboot.org/c/coreboot/+/82053/comment/5d213b0d_5cfaffb2?us… : PS11, Line 30: config PRERAM_CBMEM_CONSOLE_SIZE : hex : default 0xd00 > Is this needed? If not, I'd drop it. If it's worth keeping, I'd remove the type: […] I suspect not, this is probably a copypasta leftover. File src/mainboard/dell/optiplex_3050/acpi/dptf.asl: PS11: > Is this tested? i think i saw a dmesg about it, but otherwise no. File src/mainboard/dell/optiplex_3050/bootblock.c: https://review.coreboot.org/c/coreboot/+/82053/comment/84865eb6_1d856cb5?us… : PS11, Line 55: sch5555_mbox_read(1, 0xb8); > I wonder what these reads do vendor fw also does the reads and similarly discard the results, outside that i have no idea https://review.coreboot.org/c/coreboot/+/82053/comment/9c4560c7_43ee5823?us… : PS11, Line 96: // Changes LED color among a few other things > Is the functioning of these bits known? i think a datasheet for a similar ec discribes SCH555x_RUNTIME_PME_STS, SCH555x_RUNTIME_PME_EN and SCH555x_RUNTIME_LED. SCH555x_RUNTIME_UNK1 is named UNK1 because it's not documented File src/mainboard/dell/optiplex_3050/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82053/comment/d8cf0325_9fc82000?us… : PS11, Line 36: register "SendVrMbxCmd" = "2" > Is this copy-pasta? yes https://review.coreboot.org/c/coreboot/+/82053/comment/72300c8b_a14579ff?us… : PS11, Line 76: # ME interface is 'off' to avoid HECI reset delay due to HAP > Would be nice to auto-disable at runtime. yes indeed, although the bootguard bypass is currently only tested to work in HAP mode (it should be possible to make it work otherwise in theory) https://review.coreboot.org/c/coreboot/+/82053/comment/196ba264_2b414e8d?us… : PS11, Line 110: register "SerialIoDevMode" = "{ [PchSerialIoIndexUart0] = PchSerialIoPci, }" > ```suggestion […] Fix applied. File src/mainboard/dell/optiplex_3050/include/gpio.h: https://review.coreboot.org/c/coreboot/+/82053/comment/f0c5e1e8_e6ae2790?us… : PS11, Line 15: /* Pad configuration was generated automatically using intelp2m utility */ > intelp2m has some command-line args to generate pretty macros, I think you have to tell it to ignore […] I am planning on re-writing the GPIO table based on schematic. File src/mainboard/dell/optiplex_3050/romstage.c: https://review.coreboot.org/c/coreboot/+/82053/comment/3c23a0b9_81b2dc2a?us… : PS11, Line 24: * FIXME: do we need this? */ > I think this is used with HDA. I think it should be auto-configured. I'll test if this can be removed when i add audio -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 11 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 13:22:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: arch/x86/cpu_common: Add cpu_get_c_substate_support
by Angel Pons (Code Review) 30 Jun '24

30 Jun '24

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/78224?usp=email ) Change subject: arch/x86/cpu_common: Add cpu_get_c_substate_support ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/78224/comment/79d9c1d0_a42208cf?us… : PS3, Line 200: !(cpuid_ecx(5) & CPUID_FEATURE_MONITOR_MWAIT) || (state > 4)) Is this Intel-specific? -- To view, visit https://review.coreboot.org/c/coreboot/+/78224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie57e87609ea5d6ec6f37154e8b84f1e9574aa4a9 Gerrit-Change-Number: 78224 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 13:21:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
by Anastasios Koutian (Code Review) 30 Jun '24

30 Jun '24

Anastasios Koutian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83271?usp=email ) Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration ...................................................................... cpu/intel/model_206ax: Allow turbo boost ratio limit configuration Tested on ThinkPad T420 with the i7-3940XM. Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad Signed-off-by: Anastasios Koutian <akoutian2(a)gmail.com> --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/83271/1 diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index aa4c0ef..40d0fd3 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -56,6 +56,11 @@ /* PSI states only have an effect when in Package C3 or higher */ struct psi_state pp0_psi[3]; /* Power states for Primary Plane (Icc) */ struct psi_state pp1_psi[3]; /* Power states for Secondary Plane (IAXG) */ + + int turbo_ratio_limit_1c; /* Turbo Ratio Limit for 1 core active */ + int turbo_ratio_limit_2c; /* Turbo Ratio Limit for 2 cores active */ + int turbo_ratio_limit_3c; /* Turbo Ratio Limit for 3 cores active */ + int turbo_ratio_limit_4c; /* Turbo Ratio Limit for 4 cores acrive */ }; #endif /* __CPU_INTEL_MODEL_206AX_CHIP_H__ */ diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 2338f29..defc935 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -46,6 +46,7 @@ #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) +#define PLATFORM_INFO_SET_TURBO_RATIO_LIMIT (1 << 28) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index dd71d0f..3207304 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -175,6 +175,33 @@ } } +static void configure_turbo_ratio_limits(struct cpu_intel_model_206ax_config *conf) +{ + msr_t msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + + if(conf->turbo_ratio_limit_1c) { + msr.lo &= ~0xff; + msr.lo |= (conf->turbo_ratio_limit_1c); + } + + if(conf->turbo_ratio_limit_2c) { + msr.lo &= ~(0xff << 8); + msr.lo |= (conf->turbo_ratio_limit_2c << 8); + } + + if(conf->turbo_ratio_limit_3c) { + msr.lo &= ~(0xff << 16); + msr.lo |= (conf->turbo_ratio_limit_3c << 16); + } + + if(conf->turbo_ratio_limit_4c) { + msr.lo &= ~(0xff << 24); + msr.lo |= (conf->turbo_ratio_limit_4c << 24); + } + + wrmsr(MSR_TURBO_RATIO_LIMIT, msr); +} + static void configure_c_states(struct device *dev) { struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info; @@ -298,6 +325,13 @@ msr.lo |= PP1_CURRENT_LIMIT_LOCK; wrmsr(MSR_PP1_CURRENT_CONFIG, msr); } + + msr = rdmsr(MSR_PLATFORM_INFO); + if(msr.lo & PLATFORM_INFO_SET_TURBO_RATIO_LIMIT) { + configure_turbo_ratio_limits(conf); + } else { + printk(BIOS_NOTICE, "%s: Programmable ratio limit for turbo mode is disabled\n", dev_path(dev)); + } } static void configure_thermal_target(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/83271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad Gerrit-Change-Number: 83271 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow package power limit clamping
by Anastasios Koutian (Code Review) 30 Jun '24

30 Jun '24

Anastasios Koutian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83270?usp=email ) Change subject: cpu/intel/model_206ax: Allow package power limit clamping ...................................................................... cpu/intel/model_206ax: Allow package power limit clamping Tested on ThinkPad T420 with the i7-3940XM. Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Signed-off-by: Anastasios Koutian <akoutian2(a)gmail.com> --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83270/1 diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index e20dd1a..aa4c0ef 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -3,6 +3,8 @@ #ifndef __CPU_INTEL_MODEL_206AX_CHIP_H__ #define __CPU_INTEL_MODEL_206AX_CHIP_H__ +#include "stdbool.h" + /* Keep this in sync with acpi.c */ enum cpu_acpi_level { CPU_ACPI_DISABLED = 0, @@ -44,7 +46,9 @@ int tcc_offset; /* TCC Activation Offset */ int pl1; /* Long-term power limit*/ + bool pl1_clamp; /* Long-term power limit clamping limitation */ int pl2; /* Short-term power limit*/ + bool pl2_clamp; /* Short-term power limit clamping limitation */ int pp0_current_limit; /* Primary Plane Current Limit (Icc) in Amps */ int pp1_current_limit; /* Secondary Plane Current Limit (IAXG) in Amps */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index f4eefa3..dd71d0f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -141,18 +141,26 @@ /* Set long term power limit to TDP */ limit.lo |= tdp & PKG_POWER_LIMIT_MASK; } + if(conf->pl2_clamp) { + printk(BIOS_DEBUG, "%s: Enabling PL1 clamping limitation\n", dev_path(dev)); + limit.lo |= PKG_POWER_LIMIT_CLAMP; + } limit.lo |= PKG_POWER_LIMIT_EN; limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; limit.hi = 0; if(conf->pl2){ - printk(BIOS_DEBUG, "%s: setting PL2 to %u microwatts\n", dev_path(dev), conf->pl2); + printk(BIOS_DEBUG, "%s: Enabling PL2 clamping limitation\n", dev_path(dev)); limit.hi |= ((conf->pl2 * power_unit) / 1000000) & PKG_POWER_LIMIT_MASK; } else { /* Set short term power limit to 1.25 * TDP */ limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; } + if(conf->pl2_clamp) { + printk(BIOS_DEBUG, "Enabling PL2 clamping limitation\n"); + limit.hi |= PKG_POWER_LIMIT_CLAMP; + } limit.hi |= PKG_POWER_LIMIT_EN; /* Power limit 2 time is only programmable on SNB EP/EX */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Gerrit-Change-Number: 83270 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow PL1/PL2 configuration
by Anastasios Koutian (Code Review) 30 Jun '24

30 Jun '24

Anastasios Koutian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83269?usp=email ) Change subject: cpu/intel/model_206ax: Allow PL1/PL2 configuration ...................................................................... cpu/intel/model_206ax: Allow PL1/PL2 configuration Tested on ThinkPad T420 with the i7-3940XM. Change-Id: I064af25ec4805fae755eea52c4c9c6d4386c0aee Signed-off-by: Anastasios Koutian <akoutian2(a)gmail.com> --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/northbridge/intel/sandybridge/northbridge.c 4 files changed, 22 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83269/1 diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 9080e2f..e20dd1a 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -42,6 +42,10 @@ enum cpu_acpi_level acpi_c3; int tcc_offset; /* TCC Activation Offset */ + + int pl1; /* Long-term power limit*/ + int pl2; /* Short-term power limit*/ + int pp0_current_limit; /* Primary Plane Current Limit (Icc) in Amps */ int pp1_current_limit; /* Secondary Plane Current Limit (IAXG) in Amps */ diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 9a2fefb..2338f29 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -129,7 +129,7 @@ void intel_model_206ax_finalize_smm(void); /* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); +void set_power_limits(u8 power_limit_1_time, struct device *); int cpu_config_tdp_levels(void); static inline u8 cpu_stepping(void) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 8a4dd3f..f4eefa3 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -94,8 +94,9 @@ * Configure processor power limits if possible * This must be done AFTER set of BIOS_RESET_CPL */ -void set_power_limits(u8 power_limit_1_time) +void set_power_limits(u8 power_limit_1_time, struct device *dev) { + struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->upstream->children->chip_info; msr_t msr = rdmsr(MSR_PLATFORM_INFO); msr_t limit; unsigned int power_unit; @@ -132,16 +133,26 @@ power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - /* Set long term power limit to TDP */ limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + if(conf->pl1) { + printk(BIOS_DEBUG, "%s: setting PL1 to %u microwatts\n", dev_path(dev), conf->pl1); + limit.lo |= ((conf->pl1 * power_unit) / 1000000) & PKG_POWER_LIMIT_MASK; + } else { + /* Set long term power limit to TDP */ + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + } limit.lo |= PKG_POWER_LIMIT_EN; limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; - /* Set short term power limit to 1.25 * TDP */ limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + if(conf->pl2){ + printk(BIOS_DEBUG, "%s: setting PL2 to %u microwatts\n", dev_path(dev), conf->pl2); + limit.hi |= ((conf->pl2 * power_unit) / 1000000) & PKG_POWER_LIMIT_MASK; + } else { + /* Set short term power limit to 1.25 * TDP */ + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + } limit.hi |= PKG_POWER_LIMIT_EN; /* Power limit 2 time is only programmable on SNB EP/EX */ diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 3db9086..efafac9 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -351,7 +351,7 @@ /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - set_power_limits(28); + set_power_limits(28, dev); /* * CPUs with configurable TDP also need power limits set in MCHBAR. -- To view, visit https://review.coreboot.org/c/coreboot/+/83269?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I064af25ec4805fae755eea52c4c9c6d4386c0aee Gerrit-Change-Number: 83269 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com>

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[L] Change in coreboot[main]: [WIP] OptiPlex 3050 port
by Angel Pons (Code Review) 30 Jun '24

30 Jun '24

Attention is currently required from: Felix Singer, Máté Kukri. Angel Pons has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: [WIP] OptiPlex 3050 port ...................................................................... Patch Set 11: Code-Review+1 (15 comments) File src/mainboard/dell/optiplex_3050/Kconfig: https://review.coreboot.org/c/coreboot/+/82053/comment/88209e4b_27467b66?us… : PS11, Line 12: # select INTEL_GMA_HAVE_VBT Is this a FIXME? https://review.coreboot.org/c/coreboot/+/82053/comment/bcb01e2a_c6cef7ee?us… : PS11, Line 30: config PRERAM_CBMEM_CONSOLE_SIZE : hex : default 0xd00 Is this needed? If not, I'd drop it. If it's worth keeping, I'd remove the type: ```suggestion config PRERAM_CBMEM_CONSOLE_SIZE default 0xd00 ``` File src/mainboard/dell/optiplex_3050/acpi/dptf.asl: PS11: Is this tested? File src/mainboard/dell/optiplex_3050/bootblock.c: https://review.coreboot.org/c/coreboot/+/82053/comment/670598bb_c6b0f214?us… : PS11, Line 55: sch5555_mbox_read(1, 0xb8); I wonder what these reads do https://review.coreboot.org/c/coreboot/+/82053/comment/6c9317b3_f825d0c7?us… : PS11, Line 93: // Super I/O early init will map Runtime and EMI registers nit: Consistent C vs C++ comment style? https://review.coreboot.org/c/coreboot/+/82053/comment/c9fc9131_23375059?us… : PS11, Line 96: // Changes LED color among a few other things Is the functioning of these bits known? File src/mainboard/dell/optiplex_3050/cmos.default: https://review.coreboot.org/c/coreboot/+/82053/comment/462142ff_3ec89067?us… : PS11, Line 6: nmi=Enable Not implemented for this platform, please drop File src/mainboard/dell/optiplex_3050/cmos.layout: https://review.coreboot.org/c/coreboot/+/82053/comment/30750e79_e0de7f6e?us… : PS11, Line 21: 408 1 e 1 nmi Not implemented for this platform, please drop File src/mainboard/dell/optiplex_3050/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82053/comment/f5b762a1_2695b549?us… : PS11, Line 36: register "SendVrMbxCmd" = "2" Is this copy-pasta? https://review.coreboot.org/c/coreboot/+/82053/comment/e911ff03_f7ce46eb?us… : PS11, Line 76: # ME interface is 'off' to avoid HECI reset delay due to HAP Would be nice to auto-disable at runtime. https://review.coreboot.org/c/coreboot/+/82053/comment/5a74ea7c_11e6e552?us… : PS11, Line 110: register "SerialIoDevMode" = "{ [PchSerialIoIndexUart0] = PchSerialIoPci, }" ```suggestion register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" ``` File src/mainboard/dell/optiplex_3050/dsdt.asl: https://review.coreboot.org/c/coreboot/+/82053/comment/fea6fae1_c422f42f?us… : PS11, Line 17: Scope (\_SB) { : Device (PCI0) : { nit: Be consistent with starting brace placement File src/mainboard/dell/optiplex_3050/include/gpio.h: https://review.coreboot.org/c/coreboot/+/82053/comment/87de652a_43516af6?us… : PS11, Line 15: /* Pad configuration was generated automatically using intelp2m utility */ intelp2m has some command-line args to generate pretty macros, I think you have to tell it to ignore unknown values or something (the `1 << 1` stuff) https://review.coreboot.org/c/coreboot/+/82053/comment/edae5c06_a901c3d4?us… : PS11, Line 87: PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ > `code indent should use tabs where possible` Please fix. File src/mainboard/dell/optiplex_3050/romstage.c: https://review.coreboot.org/c/coreboot/+/82053/comment/d593782e_39e6253a?us… : PS11, Line 24: * FIXME: do we need this? */ I think this is used with HDA. I think it should be auto-configured. -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 11 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 12:16:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: [WIP] OptiPlex 3050 port
by Máté Kukri (Code Review) 30 Jun '24

30 Jun '24

1 0

[L] Change in coreboot[main]: [WIP] OptiPlex 3050 port
by Máté Kukri (Code Review) 30 Jun '24

30 Jun '24

Attention is currently required from: Máté Kukri. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82053?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [WIP] OptiPlex 3050 port ...................................................................... [WIP] OptiPlex 3050 port - Boots Linux - SMSC SCH5553 SIO/EC + Early EC init + HWM init implemented + Console on serial port tested + TODO: late HWM init for fan control (fan runs at low speed now) - Realtek Gigabit LAN works - WiFi slot works - NVMe SSD slot works - Extra: LPSS UART0 + Stock FW sets undocumented power gating bit, RTC battery needs to be pulled for it to work. + Signals exposed on test points on the back of the board. FIXME: add documentation about this - Needs 'deguard' to bypass BootGuard + See https://review.coreboot.org/plugins/gitiles/deguard - TODO: audio - TODO: cleanup GPIO table and device tree Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> --- A src/mainboard/dell/optiplex_3050/Kconfig A src/mainboard/dell/optiplex_3050/Kconfig.name A src/mainboard/dell/optiplex_3050/Makefile.mk A src/mainboard/dell/optiplex_3050/acpi/dptf.asl A src/mainboard/dell/optiplex_3050/acpi/ec.asl A src/mainboard/dell/optiplex_3050/acpi/superio.asl A src/mainboard/dell/optiplex_3050/board_info.txt A src/mainboard/dell/optiplex_3050/bootblock.c A src/mainboard/dell/optiplex_3050/cmos.default A src/mainboard/dell/optiplex_3050/cmos.layout A src/mainboard/dell/optiplex_3050/devicetree.cb A src/mainboard/dell/optiplex_3050/dsdt.asl A src/mainboard/dell/optiplex_3050/gma-mainboard.ads A src/mainboard/dell/optiplex_3050/include/gpio.h A src/mainboard/dell/optiplex_3050/mainboard.c A src/mainboard/dell/optiplex_3050/ramstage.c A src/mainboard/dell/optiplex_3050/romstage.c A src/mainboard/dell/optiplex_3050/sch5555_ec.c A src/mainboard/dell/optiplex_3050/sch5555_ec.h 19 files changed, 839 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 11 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com>

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