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Change subject: mb: source site-local mainboard Kconfig.name and Kconfig files
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> i'd say that the advantage to have that source statement everywhere is both uniformity and that it d […]
Is there a way to achieve equivalent functionality without having to modify all `src/mainboard/*/Kconfig` files?
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Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
......................................................................
Patch Set 17:
(1 comment)
Patchset:
PS17:
> Thank you very much. […]
coreboot logs the time spent printing, it doesn't seem to be that high. That being said, I know ADL FSP is atrociously slow (IIRC, so much that Google has struggled to achieve sub-second firmware boot times for Chromebooks).
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Change subject: lib: Add Kconfig variable for fw_config default value
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83153/comment/b21e37a7_fa33e454?us… :
PS3, Line 9: This CONFIG_FW_CONFIG_DEFAULT_VALUE flag is default to
Thank you.
> … when CBI fw_config value cannot be read from all sources such as Chrome EC and VPD
What is the effect of this situation? System does not boot? Some component does not work?
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Change subject: soc/intel/common: Add fpt_support to override CSME and HECI disables
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Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83265/comment/9c9a5c3c_4d530e1f?us… :
PS1, Line 9: Intels FPT (Flash Programming Tool) can be used to flash coreboot via the EFI
> `Possible unwrapped commit description (prefer a maximum 72 chars per line)`
Please fix.
https://review.coreboot.org/c/coreboot/+/83265/comment/9a36aba9_b0cfd67a?us… :
PS1, Line 15:
Please add TEST=.
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Change subject: ec/google/chromeec: Stop checking CBI for UCSI
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83252/comment/2e70073e_a5c94b50?us… :
PS1, Line 9: Use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled.
> See https://chromium-review.googlesource. […]
Thank you. Please update the commit message, as they have to be self-contained.
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Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
......................................................................
Patch Set 17:
(1 comment)
Patchset:
PS17:
> I uploaded the two logs for two different commits. […]
Thank you very much.
1. https://review.coreboot.org/plugins/gitiles/board-status/+/d2df631729544b9a…
2. https://review.coreboot.org/plugins/gitiles/board-status/+/73bab87c09851459…
$ git grep "Total Time" aoostar/wtr_r1/
aoostar/wtr_r1/24.05-171-gc9302d5d39/2024-06-07T06_16_27Z/coreboot_timestamps.txt:Total Time: 2,292,748
aoostar/wtr_r1/24.05-384-g0486f2b3bb/2024-06-28T22_11_31Z/coreboot_timestamps.txt:Total Time: 2,070,133
```
$ git grep CONFIG_CONSOLE_SERIAL= aoostar/wtr_r1/
aoostar/wtr_r1/24.05-171-gc9302d5d39/2024-06-07T06_16_27Z/config.short.txt:CONFIG_CONSOLE_SERIAL=y
aoostar/wtr_r1/24.05-171-gc9302d5d39/2024-06-07T06_16_27Z/config.txt:CONFIG_CONSOLE_SERIAL=y
aoostar/wtr_r1/24.05-384-g0486f2b3bb/2024-06-28T22_11_31Z/config.short.txt:CONFIG_CONSOLE_SERIAL=y
aoostar/wtr_r1/24.05-384-g0486f2b3bb/2024-06-28T22_11_31Z/config.txt:CONFIG_CONSOLE_SERIAL=y
```
Two seconds is quite long and probably caused by the serial console. Sorry for not writing it earlier. If you find time, it’d be great if you did both things with serial console disable so the lowest boot time is documented. I am marking this comment as resolved nevertheless. Big thanks again for the port and the uploads.
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Change subject: Makefile.mk: Use Walloc-size command option
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82734/comment/4db36bca_ace0778d?us… :
PS2, Line 7: command
Maybe say GCC?
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Change subject: Makefile.mk: Use Walloc-size command option
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Patch Set 2: Code-Review+2
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