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Pratikkumar V Prajapati has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email )
Change subject: soc/intel: Adapt crashlog IP to also support 64-bit
......................................................................
Patch Set 22: Code-Review+1
(1 comment)
File src/soc/intel/meteorlake/crashlog.c:
https://review.coreboot.org/c/coreboot/+/83106/comment/65d58229_ddc58c94?us… :
PS22, Line 352: + 4
> Dont we need to check for 0xdeadbeef […]
line 354 is already checking for 0 size. I think we should also check for deadbeef, its pretty easy check.
I assume you triggered a fake crashlog and was able to parse/decode the crashlog data.
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Change subject: ec/google/chromeec: Stop checking CBI for UCSI
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83252/comment/a9258f82_593f6eae?us… :
PS1, Line 9: Use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled.
> Please starte by describing the problem.
See https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/5664227
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Change subject: src/lib: Add Kconfig variable for fw_config default value
......................................................................
Patch Set 3:
(1 comment)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/83153/comment/62de21f4_07823207?us… :
PS2, Line 548: 0x00000
> > I change default value to UNDEFINED_FW_CONFIG and this won't be used unless config. […]
Subrata, I assume you mean FW_CONFIG_SOURCE_CHROMEEC_CBI. Yes. we set this flag off in our build for Windows EC and also for simulation environment and intend not to use Chrome EC. In fw_config.h, it has this define:
#define UNDEFINED_FW_CONFIG ~((uint64_t)0) -> 0xffffffffffffffff
The same value is used for CONFIG_FW_CONFIG_DEFAULT_VALUE as default in Kconfig so that even all bits are '1', but then this flag is not provisioned. If not overridden in config.<board>, no code flow is changed.
In addition, in our standalone make build, we don't have project config.star like the one in cros environment. Also, during PO, we used Windows EC and also we had issue with Chrome EC and not able to get CBI command back then. This flag is used so that we can have at least fw_config value other than UNDEFINED_FW_CONFIG to move forward.
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Change subject: util/superiotool/fintek: Add f81866 register table
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83004/comment/5e187d5f_b2ac2cef?us… :
PS9, Line 12: 1
Putting URLs in the commit message is discouraged as they frequently become stale as the website changes. If you do want to add the URL here, please use an archive.org link.
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Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
......................................................................
Patch Set 7:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/83018/comment/d701de94_9bba645b?us… :
PS7, Line 10: https
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Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83018/comment/1e9591d6_b7a876cd?us… :
PS6, Line 7: utils
> nit: util
Thx
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Hello Angel Pons, Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83018?usp=email
to look at the new patch set (#7).
Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
......................................................................
util/superiotool/fintek: Add missing F81804 name for 0x0215 id
"0x1502 F81804 chipset ID, same for F81966" in
https://github.com/torvalds/linux/blob/master/drivers/gpio/gpio-f7188x.c
Change-Id: I6889ad8ad861465316333ff997956a05b74c5855
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M util/superiotool/fintek.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83018/7
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