coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: drivers/spi/acpi: Add generic property list
by Kun Liu (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Eric Lai, Felix Held, Jian Tong, Paul Menzel, Shelley Chen, Subrata Banik. Kun Liu has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/83139?usp=email ) Change subject: drivers/spi/acpi: Add generic property list ...................................................................... Patch Set 10: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83139/comment/ba96b8ec_5386e0b6?us… : PS9, Line 8: > Please start by describing the problem. Done https://review.coreboot.org/c/coreboot/+/83139/comment/eb0a6bc2_f11c6695?us… : PS9, Line 14: TEST=emerge-brox coreboot > Any commands you ran? local build bios,and verify that the correct transfer of hid-report-addr to the touch driver. File src/drivers/spi/acpi/chip.h: https://review.coreboot.org/c/coreboot/+/83139/comment/fe52f5a7_ccb64f77?us… : PS9, Line 8: #define MAX_GENERIC_PROPERTY_LIST 10 > Why 10? Please elaborate in the commit. This is a universal code. If only one attribute is defined for the vendor Goodix, in the future, if other vendors need to define multiple attributes, it cannot be met. MAX_GENERIC-PROPERTY-LIST needs to be modified, defined as 10 here, which basically meets the attribute requirements of all vendors. In the future, other projects only need to add the vendor's attributes in the devicetree without further modification. -- To view, visit https://review.coreboot.org/c/coreboot/+/83139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Gerrit-Change-Number: 83139 Gerrit-PatchSet: 10 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Jun 2024 11:34:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: [Don't Merge] Test Patch to remove CSE CBMEM ID
by Subrata Banik (Code Review) 28 Jun '24

28 Jun '24

Subrata Banik has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/83259?usp=email ) Change subject: [Don't Merge] Test Patch to remove CSE CBMEM ID ...................................................................... [Don't Merge] Test Patch to remove CSE CBMEM ID Change-Id: I48a9d1e11c6312fd541dffd885f607738f566f21 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M payloads/libpayload/libc/coreboot.c M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/83259/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48a9d1e11c6312fd541dffd885f607738f566f21 Gerrit-Change-Number: 83259 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: drivers/spi/acpi: Add generic property list
by Kun Liu (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Eric Lai, Felix Held, Jian Tong, Kun Liu, Shelley Chen, Subrata Banik. Hello Eric Lai, Jian Tong, Karthik Ramasubramanian, Shelley Chen, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83139?usp=email to look at the new patch set (#10). Change subject: drivers/spi/acpi: Add generic property list ...................................................................... drivers/spi/acpi: Add generic property list The touchscreen vendor (Goodix) needs to use this value (hid-report-addr) in the touch driver, and this value needs to be changed later.So add generic property list to allow populating vendor specific device properties to ACPI SSDT table. BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/drivers/spi/acpi/acpi.c M src/drivers/spi/acpi/chip.h 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/83139/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/83139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Gerrit-Change-Number: 83139 Gerrit-PatchSet: 10 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
by Lean Sheng Tan (Code Review) 28 Jun '24

28 Jun '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83136?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC ...................................................................... soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC For Gen1 SoCs, the range starting from the end of VTd BAR to the end of 32-bit domain MMIO resource window is reserved for unknown devices. Get them reserved. TEST=Build and boot on intel/archercity CRB Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/spr/ioat.c 2 files changed, 26 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index 117de9c..a68c764 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -7,6 +7,7 @@ #include <device/pci_ids.h> #include <soc/pci_devs.h> #include <intelblocks/acpi.h> +#include <intelblocks/vtd.h> #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/soc_util.h> @@ -54,6 +55,13 @@ if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) domain_mem_window_from_to(dev, index++, sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1); + + /* Declare domain reserved MMIO */ + uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(pcidev_on_root(0, 0)); + if ((reserved_mmio >= sr->PciResourceMem32Base) && + (reserved_mmio <= sr->PciResourceMem32Limit)) + mmio_range(dev, index++, reserved_mmio, + sr->PciResourceMem32Limit - reserved_mmio + 1); } /* diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index a0babee..ac968d1 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -8,6 +8,7 @@ #include <defs_iio.h> #include <hob_iiouds.h> #include <intelblocks/acpi.h> +#include <intelblocks/vtd.h> #include <soc/acpi.h> #include <IioPcieConfigUpd.h> @@ -29,7 +30,7 @@ #endif }; -static void create_ioat_domain(const union xeon_domain_path dp, struct bus *const upstream, +static struct device *const create_ioat_domain(const union xeon_domain_path dp, struct bus *const upstream, const unsigned int bus_base, const unsigned int bus_limit, const resource_t mem32_base, const resource_t mem32_limit, const resource_t mem64_base, const resource_t mem64_limit, @@ -66,6 +67,8 @@ if (mem64_base <= mem64_limit) domain_mem_window_from_to(domain, index++, mem64_base, mem64_limit + 1); + + return domain; } void create_ioat_domains(const union xeon_domain_path path, @@ -130,6 +133,18 @@ mem64_limit = sr->PciResourceMem64Limit; bus_base = sr->BusBase; bus_limit = bus_base; - create_ioat_domain(path, bus, bus_base, bus_limit, sr->PciResourceMem32Base, sr->PciResourceMem32Limit, - mem64_base, mem64_limit, DOMAIN_TYPE_DINO, pci_segment_group); + struct device *const dev = create_ioat_domain(path, bus, bus_base, bus_limit, + sr->PciResourceMem32Base, sr->PciResourceMem32Limit, + mem64_base, mem64_limit, DOMAIN_TYPE_DINO, pci_segment_group); + + /* Declare domain reserved MMIO */ + uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(pcidev_on_root(0, 0)); + if ((reserved_mmio >= sr->PciResourceMem32Base) && + (reserved_mmio <= sr->PciResourceMem32Limit)) { + int index = 0; + for (struct resource *res = dev->resource_list; res; res = res->next) + index++; + mmio_range(dev, index, reserved_mmio, + sr->PciResourceMem32Limit - reserved_mmio + 1); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/83136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Gerrit-Change-Number: 83136 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically
by Lean Sheng Tan (Code Review) 28 Jun '24

28 Jun '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82431?usp=email ) Change subject: soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically ...................................................................... soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically vtd_probe_bar_size is used to decide the BAR size. TEST=Build and boot on intel/archercity CRB Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c 3 files changed, 22 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 5fd5dc6..3f4c77e 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -90,4 +90,6 @@ void unlock_pam_regions(void); +size_t vtd_probe_bar_size(struct device *dev); + #endif /* _CHIP_COMMON_H_ */ diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index d2d4622..9645191 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -51,6 +51,20 @@ NUM_MAP_ENTRIES }; +size_t vtd_probe_bar_size(struct device *dev) +{ + uint32_t id = pci_read_config32(dev, PCI_VENDOR_ID); + assert(id == (PCI_VID_INTEL | (MMAP_VTD_CFG_REG_DEVID << 16))); + + uint32_t val = pci_read_config32(dev, VTD_BAR_CSR); + pci_write_config32(dev, VTD_BAR_CSR, (uint32_t)(-4 * KiB)); + size_t size = (~(pci_read_config32(dev, VTD_BAR_CSR) & ((uint32_t)(-4 * KiB)))) + 1; + assert(size != 0); + pci_write_config32(dev, VTD_BAR_CSR, val); + + return size; +} + static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"), [MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"), @@ -211,7 +225,8 @@ mc_report_map_entries(dev, &mc_values[0]); if (mc_values[VTDBAR_REG]) { - res = mmio_range(dev, VTD_BAR_CSR, mc_values[VTDBAR_REG], 8 * KiB); + res = mmio_range(dev, VTD_BAR_CSR, mc_values[VTDBAR_REG], + vtd_probe_bar_size(dev)); LOG_RESOURCE("vtd_bar", dev, res); } diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index a0bbbff..22f8b6f 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -272,12 +272,13 @@ printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base, vtd_probe_bar_size(iommu)); } else { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd_4k(current, 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base, + vtd_probe_bar_size(iommu)); } // Add PCH IOAPIC -- To view, visit https://review.coreboot.org/c/coreboot/+/82431?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c Gerrit-Change-Number: 82431 Gerrit-PatchSet: 21 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: acpi: Add support for DRHD size reporting
by Lean Sheng Tan (Code Review) 28 Jun '24

28 Jun '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82429?usp=email ) Change subject: acpi: Add support for DRHD size reporting ...................................................................... acpi: Add support for DRHD size reporting VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD sizes larger than 4KB. If the value in the field is N, the size of the register set is 2^N 4 KB pages. Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying to use the beyond 4KB part of the DRHD BAR if they exist. They need the DRHD size field to set up page mapping before access those registers. Re-add acpi_create_dmar_drhd with a size parameter to support the needs. TEST=Build and boot on intel/archercity CRB Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpi_dmar.c M src/include/acpi/acpi.h 2 files changed, 22 insertions(+), 2 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c index 20a100d..67bca55 100644 --- a/src/acpi/acpi_dmar.c +++ b/src/acpi/acpi_dmar.c @@ -2,7 +2,9 @@ #include <acpi/acpi.h> #include <arch/ioapic.h> +#include <assert.h> #include <cpu/cpu.h> +#include <lib.h> #include <version.h> void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, @@ -37,8 +39,23 @@ } unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags, - u16 segment, u64 bar) + u16 segment, u64 bar) { + return acpi_create_dmar_drhd(current, flags, segment, bar, 4 * KiB); +} + +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, + u16 segment, u64 bar, size_t size) +{ + /* + * Refer to Intel® Virtualization Technology for Directed I/O + * Architecture Specification Revision 4.1, + * size is at least 1 page and max 2^15 pages, 4 KiB each, and the bar + * should be aligned with size. + */ + assert(4 * KiB <= size && size <= (1 << 15) * 4 * KiB && IS_POWER_OF_2(size)); + assert(IS_ALIGNED(bar, size)); + dmar_entry_t *drhd = (dmar_entry_t *)current; memset(drhd, 0, sizeof(*drhd)); drhd->type = DMAR_DRHD; @@ -46,6 +63,7 @@ drhd->flags = flags; drhd->segment = segment; drhd->bar = bar; + drhd->size = log2_64(size) - 12; return drhd->length; } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 469d672..a36e65c 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -638,7 +638,7 @@ u16 type; u16 length; u8 flags; - u8 reserved; + u8 size; u16 segment; u64 bar; } __packed dmar_entry_t; @@ -1851,6 +1851,8 @@ unsigned long (*acpi_fill_dmar)(unsigned long)); unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags, u16 segment, u64 bar); +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, + u16 segment, u64 bar, size_t size); unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, u64 bar, u64 limit); unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, -- To view, visit https://review.coreboot.org/c/coreboot/+/82429?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Gerrit-Change-Number: 82429 Gerrit-PatchSet: 18 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: Makefile.mk: Use one line per *_common flag
by Maximilian Brune (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth. Maximilian Brune has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83226?usp=email ) Change subject: Makefile.mk: Use one line per *_common flag ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > By the paste, I've sorted CFLAGS by kind and alphabetically (https://review.coreboot. […] I would prefer that to be a separate commit, since it is easier for review. Now I can easily see that no option has been forgotten, since the order is the same. And in the separate commit I just have to see that no more lines were added than removed (or vice versa) to see that it is good to go. -- To view, visit https://review.coreboot.org/c/coreboot/+/83226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d Gerrit-Change-Number: 83226 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 28 Jun 2024 11:26:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/cmn/cse: Make ME firmware version query function static
by Subrata Banik (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Eric Lai, Nick Vaccaro, Pranava Y N. Hello Eric Lai, Nick Vaccaro, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83257?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cmn/cse: Make ME firmware version query function static ...................................................................... soc/intel/cmn/cse: Make ME firmware version query function static This change modifies the get_me_fw_version() function to be statically scoped within src/soc/intel/common/block/cse/cse.c, as it is only used by the print_me_fw_version() function in the same file. The function declaration is also removed from intelblocks/cse.h. The order of the function definitions in cse.c was also changed to be more logical, with the now static helper function get_me_fw_version() defined first, before it is used. TEST=Able to build google/rex. Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 18 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83257/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846 Gerrit-Change-Number: 83257 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: [Don't Merge]
by Subrata Banik (Code Review) 28 Jun '24

28 Jun '24

Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83259?usp=email ) Change subject: [Don't Merge] ...................................................................... Patch Set 1: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48a9d1e11c6312fd541dffd885f607738f566f21 Gerrit-Change-Number: 83259 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 28 Jun 2024 11:23:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: [Don't Merge]
by Subrata Banik (Code Review) 28 Jun '24

28 Jun '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83259?usp=email ) Change subject: [Don't Merge] ...................................................................... [Don't Merge] Test Patch to remove CSE CBMEM ID Change-Id: I48a9d1e11c6312fd541dffd885f607738f566f21 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M payloads/libpayload/libc/coreboot.c M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/83259/1 diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 7873426..d9424fa 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -262,12 +262,14 @@ case CBMEM_ID_MEM_CHIP_INFO: info->mem_chip_base = cbmem_entry->address; break; +#if 0 case CBMEM_ID_CSE_BP_INFO: info->cse_bp_info = cbmem_entry->address; break; case CBMEM_ID_CSE_INFO: info->cse_info = cbmem_entry->address; break; +#endif default: break; } diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 4e3a446..63156ca 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1541,7 +1541,7 @@ } } } - +#if 0 static void preram_create_cbmem_cse_info(int is_recovery) { if (!CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) @@ -1566,7 +1566,7 @@ } CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info); - +#endif static void ramstage_cse_misc_ops(void *unused) { if (acpi_get_sleep_type() == ACPI_S3) -- To view, visit https://review.coreboot.org/c/coreboot/+/83259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48a9d1e11c6312fd541dffd885f607738f566f21 Gerrit-Change-Number: 83259 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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