coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
by Maxim (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Felix Singer, Maxim. Hello Angel Pons, Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83018?usp=email to look at the new patch set (#7). Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id ...................................................................... util/superiotool/fintek: Add missing F81804 name for 0x0215 id "0x1502 F81804 chipset ID, same for F81966" in https://github.com/torvalds/linux/blob/master/drivers/gpio/gpio-f7188x.c Change-Id: I6889ad8ad861465316333ff997956a05b74c5855 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/superiotool/fintek.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83018/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/83018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6889ad8ad861465316333ff997956a05b74c5855 Gerrit-Change-Number: 83018 Gerrit-PatchSet: 7 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Angel Pons (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Nicholas Sudsgaard. Angel Pons has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80411?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Patch Set 20: Code-Review+1 (5 comments) File Documentation/mainboard/lenovo/thinkcentre_m710s.md: https://review.coreboot.org/c/coreboot/+/80411/comment/a9cb37b7_635c24d5?us… : PS17, Line 200: * DRM issue when using EDK 2 and libgfxinit > Unfortunately I don't remember what error message I was receiving in `dmesg` (I know... […] Ah, DRM as in https://en.wikipedia.org/wiki/Direct_Rendering_Manager and not https://en.wikipedia.org/wiki/Digital_rights_management In any case, I see you've dropped the section so I'll resolve this. File Documentation/mainboard/lenovo/thinkcentre_m710s.md: https://review.coreboot.org/c/coreboot/+/80411/comment/ceb70ccf_6d146132?us… : PS20, Line 7: ```eval_rst As per CB:83117 ```suggestion ```{eval-rst} ``` https://review.coreboot.org/c/coreboot/+/80411/comment/f7ab4bd3_50fe0a71?us… : PS20, Line 28: Programming nit: Flashing https://review.coreboot.org/c/coreboot/+/80411/comment/0c4cb070_5d7feee6?us… : PS20, Line 30: using the nit ```suggestion The flash chip cannot be flashed internally when running vendor firmware, and must ``` https://review.coreboot.org/c/coreboot/+/80411/comment/51ea1414_6aa75b9f?us… : PS20, Line 47: Tianocore's EDK 2 Does "Tianocore" mean https://github.com/tianocore/edk2 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 20 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Fri, 28 Jun 2024 13:34:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Sowmya Aralguppe (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Tarun. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (1 comment) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/c15c3e2b_7b475745?us… : PS22, Line 352: + 4 > Why do we need to add 4 here? […] Dont we need to check for 0xdeadbeef >> My understanding is this - pls correct if wrong Various dielets store crash record in its own SRAM and the offset and size is stored in the header . During DISCOVERY- the size and the offset is read and while COLLECTING the crash record- need to check for invalid crash record data . For example if we take the example of PUNIT (the 1st in the count) First we read PUNIT_SRAM_DISCOVERY_0 and get the child count and then loop count number of times Inside the loop read PUNIT_SRAM_DISCOVERY_1 (which is bar address + 0x1f78) we will get the size and offset Get PUINT crashlog record located at (address = dev10 MMIO base + Offset in PUNIT_SRAM_DISCOVERY_1 ) Check if PUNIT crashlog record is valid (the first DWORD is not 0 nor 0xdeadbeef && consumed bit is not set), collect all crashlog data) Since we are not reading the crash data and only populating the discovery table struct we donot need to check for 0xdeadbeef or 0 values Why do we need to add 4 here >> 31:0 default 32'h0 RO OFFSET Offset based on Access Type. This will have the DVSEC/MMIO address for the given crashlog sram. 63:32 default 32'h800 RO/V DATA_BUFFER_SIZE Size in DWORDS of the CRashlog SRAM here we are reading the upper 32 bytes and to check if size is zero ( and it will not be zero as default values for storage SRAM is 0x800) while collecting the crash record data from the sram address we need to check if the value is 0 or deadbeef -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Jun 2024 13:20:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Angel Pons. Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80411?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Patch Set 20: (18 comments) File Documentation/mainboard/lenovo/thinkcentre_m710s.md: https://review.coreboot.org/c/coreboot/+/80411/comment/a8e2776a_e0012b65?us… : PS17, Line 5: that even dummies could follow through > Thanks for the detailed review! […] Done https://review.coreboot.org/c/coreboot/+/80411/comment/8aceee93_3a40a3a9?us… : PS17, Line 12: ```eval_rst : Start by following the :doc:`tutorial <../../tutorial/part1>` until step 3. : ``` > Wouldn't it be nice to have a tutorial for "installing" coreboot onto any board, instead of having t […] Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/3eab2081_19552632?us… : PS17, Line 22: # Take 2 images of your original flash image : flashrom -p internal -r vendor.rom : flashrom -p internal -r vendor.rom.backup > That won't work properly because the ME region is not readable by the host. Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/44bffc64_71cfbb93?us… : PS17, Line 26: # Compare the images to see if there is any differences (should be none) : sha1sum vendor.rom vendor.rom.backup > This is unnecessary. Just tell flashrom to verify the file against the flash chip contents: […] Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/d9965d27_c5a7b230?us… : PS17, Line 16: ### Step 2 - Preserving the original flash image (IMPORTANT) : : Before proceeding, it is **VERY IMPORTANT** to keep the original (vendor) flash image. : Without this, it would be very difficult to recover from mistakes during : flashing (or if you decide coreboot is not for you). : : # Take 2 images of your original flash image : flashrom -p internal -r vendor.rom : flashrom -p internal -r vendor.rom.backup : : # Compare the images to see if there is any differences (should be none) : sha1sum vendor.rom vendor.rom.backup : : # Make the images immutable to prevent accidental modification/deletion : chattr +i vendor.rom vendor.rom.backup : # Check whether the 'i' flag is set : lsattr vendor.rom vendor.rom.backup : : # To be absolutely sure you can attempt to modifiy/delete the images : # You should get 'Operation not permitted' : echo "test" > vendor.rom : rm -f vendor.rom : : If you ever need to undo the installation, simply flash this image. : As long as you do this, flashing coreboot is not as scary as it sounds. :) > This is not mainboard specific. It doesn't belong in here. Done https://review.coreboot.org/c/coreboot/+/80411/comment/911aa949_6ebe1993?us… : PS17, Line 44: Let's also use a layout file to be sure that we only modify the BIOS region : of your flash chip. This makes things simpler and reduces and chance of messing : up your flash chip. > Adding the `--ifd -i bios` arguments to flashrom achieves the same effect and is a lot less error-pr […] Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/eeeae4db_bb3a3097?us… : PS17, Line 64: coreboot provides an easy way of configuration by using a TUI menu. To open this : run the following command: : : make menuconfig : : While it should be quite intuitive, the navigation is written at the top if you : get stuck. : : Every mainboard is different and you need to instruct coreboot to build for : Lenovo ThinkCentre M710s specifically. : : Mainboard ---> : Mainboard vendor (Lenovo) ---> : Mainboard model (ThinkCentre M710s) ---> > It would be much better to have generic "how to build a coreboot image" instructions instead of havi […] Done https://review.coreboot.org/c/coreboot/+/80411/comment/66d0ab48_2e384148?us… : PS17, Line 81: Now you can choose the payload that you are going to use: : : * SeaBIOS : * Tianocore's EDK 2 (choose this if unsure) : : It is highly recommend not choosing anything else, as they have not been tested : and are most likely not going to work. > I wouldn't tell people to use any payloads, just document what has been tested on this board and is […] Done https://review.coreboot.org/c/coreboot/+/80411/comment/61f6062f_f6c53dac?us… : PS17, Line 98: Tianocore's EDK II payload (Official edk2 repository) ---> > But why wasn't the temptation (what you wrote below) resisted here? MrChromebox's edk2 is the defaul […] Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/be0a08c2_f5aa5025?us… : PS17, Line 79: ### Step 2 - Choosing the payload : : Now you can choose the payload that you are going to use: : : * SeaBIOS : * Tianocore's EDK 2 (choose this if unsure) : : It is highly recommend not choosing anything else, as they have not been tested : and are most likely not going to work. : : #### SeaBIOS : : Payload ---> : Payload to add (SeaBIOS) ---> : : #### EDK 2 : : Payload ---> : Payload to add (edk2 payload) ---> : Tianocore's EDK II payload (Official edk2 repository) ---> : : While understandable, it is recommended to resist the temptation of doing any : additional configuration if this is your first time building coreboot. > Not mainboard specific. Done https://review.coreboot.org/c/coreboot/+/80411/comment/08d551cf_2ba1c064?us… : PS17, Line 103: ### Step 3 - Building coreboot : : Finally, save your changes and build coreboot (this should only take a couple of minutes). : : make -j$(nproc) > Not mainboard specific. Done https://review.coreboot.org/c/coreboot/+/80411/comment/25461248_41eae2ee?us… : PS17, Line 133: **Make sure you attach the clip using the correct pin configurations** (page 6 of : the datasheet or the image above), as it may **damage your chip** if done incorrectly. : How to do this depends on your programmer of choice and refer to other : documentation which can be found on the internet. > Not mainboard specific. Done https://review.coreboot.org/c/coreboot/+/80411/comment/ae73368b_13f6b215?us… : PS17, Line 138: While [not recommended](https://libreboot.org/docs/install/spi.html#do-not-use-ch341a) : the CH431A programmer seems to be very popular. However, it can be slightly : confusing at first. Here is the pinout and which half to use ([datasheet](https://www.alldatasheet.com/datasheet-pdf/pdf/1132609/ETC2/CH34…). : : ![](ch341a_pinout.jpg) > Not mainboard specific. […] Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/bfe25357_7bcd382e?us… : PS17, Line 148: 'W25Q64BV/W25Q64CV/W25Q64FV' > I don't think flashrom has support for `W25Q64JV` specifically (at least when I wrote the documentat […] I now use the correct chip definition: `W25Q64JV-.Q`. https://review.coreboot.org/c/coreboot/+/80411/comment/e14962db_2afb3ed9?us… : PS17, Line 160: In the unfortunate case, where your machine does not seem to boot, first check : for any mistakes. > What constitutes a mistake? Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/ab6d727b_5ac9302f?us… : PS17, Line 161: If you are confident that you did not make any mistakes : reach out to the :doc:`community <../../community/forums>` for some help. > And if you made mistakes, what? I really don't like how this section reads. Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/ddb96bdb_f9cec0a6?us… : PS17, Line 165: ## Updating : : Luckily, once you have coreboot, updating can be done internally using the following command: : : flashrom -p internal --fmap -i COREBOOT -w build/coreboot.rom > Any reason to update coreboot using the fmap here? Acknowledged https://review.coreboot.org/c/coreboot/+/80411/comment/7b5cd13c_36d38aba?us… : PS17, Line 200: * DRM issue when using EDK 2 and libgfxinit > What does "DRM issue" mean? Unfortunately I don't remember what error message I was receiving in `dmesg` (I know... I should have noted that down). I tried to replicate the issue running Ubuntu 22.04 LiveCD but everything seems to work fine now. -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 20 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Jun 2024 12:53:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: Makefile.mk: Use Walloc-size command option
by Elyes Haouas (Code Review) 28 Jun '24

28 Jun '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82734?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Makefile.mk: Use Walloc-size command option ...................................................................... Makefile.mk: Use Walloc-size command option Change-Id: Ia26dcf097db125a5a734660d08d875459179241b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/82734/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia26dcf097db125a5a734660d08d875459179241b Gerrit-Change-Number: 82734 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Makefile.mk: Use Wcast-function-type command option
by Elyes Haouas (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82736?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Makefile.mk: Use Wcast-function-type command option ...................................................................... Makefile.mk: Use Wcast-function-type command option Change-Id: I25415d7fd82879889ffaa1bb534ad5d0b174854e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/82736/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82736?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25415d7fd82879889ffaa1bb534ad5d0b174854e Gerrit-Change-Number: 82736 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Angel Pons, Nicholas Sudsgaard. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80411?usp=email to look at the new patch set (#20). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M710s Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/thinkcentre_m710s.md A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg 3 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/80411/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 20 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: Makefile.mk: Use one line per *_common flag
by Elyes Haouas (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Felix Singer, Martin L Roth. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83226?usp=email ) Change subject: Makefile.mk: Use one line per *_common flag ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d Gerrit-Change-Number: 83226 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Jun 2024 12:44:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 28 Jun '24

28 Jun '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83260?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M710s Change-Id: I55bd61d99631af48dc6863992dca54ae406667c2 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/thinkcentre_m710s.md A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg 3 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/83260/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 519d888..ab09743 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -103,6 +103,7 @@ - [Mainboard codenames](lenovo/codenames.md) - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) - [R60](lenovo/r60.md) +- [ThinkCentre M710s](lenovo/thinkcentre_m710s) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) - [vboot](lenovo/vboot.md) diff --git a/Documentation/mainboard/lenovo/thinkcentre_m710s.md b/Documentation/mainboard/lenovo/thinkcentre_m710s.md new file mode 100644 index 0000000..925375c --- /dev/null +++ b/Documentation/mainboard/lenovo/thinkcentre_m710s.md @@ -0,0 +1,80 @@ +# Lenovo ThinkCentre M710s + +This page provides technical documentation on [Lenovo ThinkCentre M710s]. + +## Flash chip + +```eval_rst ++----------+-------------+ +| Type | Value | ++==========+=============+ +| Socketed | yes | ++----------+-------------+ +| Model | W25Q64JV-.Q | ++----------+-------------+ +| Size | 8MiB | ++----------+-------------+ +| Package | SOIC-8 | ++----------+-------------+ +``` + +The flash chip is divided into the following regions. + + 00000000:00000fff fd + 00200000:007fffff bios + 00003000:001fffff me + 00001000:00002fff gbe + +## Programming + +The flash chip cannot be flashed internally using the vendor firmware, and must +be flashed externally using a programmer of your choice. + +Steps on how to open the chassis and get access to the mainboard are described +in the [hardware maintenance manual]. Follow the steps shown from +"[Removing the computer cover]" until step 1 of "[Replacing the storage drive]". + +The SPI flash should be easy to identify and the location is shown in the image +below. See the [datasheet] and [flashing firmware tutorial] for more information. + +![](thinkcentre_m710s_spi_location.jpg) + +## Status + +### Working + * Ubuntu 22.04.1 (Linux 6.5.0) using payloads: + * SeaBIOS + * Tianocore's EDK 2 + * Internal flashing (from coreboot) + * PEG (PCIe Graphics) + * PCIe + * SATA + * M.2 SSD + * M.2 WLAN (+ Bluetooth) + * LAN + * USB + * Memory card reader + * CPU fan + * VGA + * Display ports + * Audio (output) + * COM1 + * TPM + +### Not working + * Super I/O not well supported (there may be some minor issues) + * Power button LED + * ME cleaner + +### Untested + * Audio (input) + * COM2 header + * LPT header + * PS/2 keyboard and mouse + +[Lenovo ThinkCentre M710s]: https://www.lenovo.com/us/en/p/desktops/thinkcentre/m-series-sff/thinkcentr… +[hardware maintenance manual]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf +[Removing the computer cover]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf#page… +[Replacing the storage drive]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf#page… +[datasheet]: https://www.winbond.com/hq/support/documentation/?__locale=en&line=/product… +[flashing firmware tutorial]: ../../tutorial/flashing_firmware/index.md diff --git a/Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg b/Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg new file mode 100644 index 0000000..5995ee8 --- /dev/null +++ b/Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/83260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55bd61d99631af48dc6863992dca54ae406667c2 Gerrit-Change-Number: 83260 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[M] Change in coreboot[main]: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
by Sergii Dmytruk (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Arthur Heymans, Krystian Hebel, Sergii Dmytruk. Hello Krystian Hebel, Martin L Roth, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67065?usp=email to look at the new patch set (#38). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER ...................................................................... 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER Signing is performed with test keys by default, set CONFIG_SIGNING_KEYS_DIR to non-empty value to use other keys. Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M .gitmodules A 3rdparty/open-power-signing-utils M Makefile.mk M src/soc/ibm/power9/Kconfig M src/soc/ibm/power9/Makefile.mk 5 files changed, 55 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/67065/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/67065?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Gerrit-Change-Number: 67065 Gerrit-PatchSet: 38 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Georgi Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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