coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

1 participants
3066 discussions

[M] Change in coreboot[main]: [TEST][WIP]soc/amd: factor out common gpp_clk_setup implementation
by Varshit Pandya (Code Review) 01 Feb '24

01 Feb '24

Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80285?usp=email ) Change subject: [TEST][WIP]soc/amd: factor out common gpp_clk_setup implementation ...................................................................... [TEST][WIP]soc/amd: factor out common gpp_clk_setup implementation Starting with PHX Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- A src/soc/amd/common/block/gpp_clk/Kconfig A src/soc/amd/common/block/gpp_clk/Makefile.mk A src/soc/amd/common/block/gpp_clk/gpp_clk.c A src/soc/amd/common/block/include/amdblocks/gpp_clk.h M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/fch.c 6 files changed, 83 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/80285/1 diff --git a/src/soc/amd/common/block/gpp_clk/Kconfig b/src/soc/amd/common/block/gpp_clk/Kconfig new file mode 100644 index 0000000..eb192ef --- /dev/null +++ b/src/soc/amd/common/block/gpp_clk/Kconfig @@ -0,0 +1,4 @@ +config SOC_AMD_COMMON_BLOCK_GPP_CLK + bool + help + Select this option to use AMD common GPP support. diff --git a/src/soc/amd/common/block/gpp_clk/Makefile.mk b/src/soc/amd/common/block/gpp_clk/Makefile.mk new file mode 100644 index 0000000..3c85d97 --- /dev/null +++ b/src/soc/amd/common/block/gpp_clk/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_GPP_CLK) += gpp_clk.c diff --git a/src/soc/amd/common/block/gpp_clk/gpp_clk.c b/src/soc/amd/common/block/gpp_clk/gpp_clk.c new file mode 100644 index 0000000..d6d8610 --- /dev/null +++ b/src/soc/amd/common/block/gpp_clk/gpp_clk.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/gpp_clk.h> +#include <amdblocks/pci_clk_req.h> + +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ +void gpp_clk_setup_common(enum gpp_clk_req *gpp_clk_config, size_t gpp_clk_config_num, int available_clk) +{ + /* look-up table to be able to iterate over the PCIe clock output settings */ + const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { + GPP_CLK0_REQ_SHIFT, + GPP_CLK1_REQ_SHIFT, + GPP_CLK2_REQ_SHIFT, + GPP_CLK3_REQ_SHIFT, + GPP_CLK4_REQ_SHIFT, + GPP_CLK5_REQ_SHIFT, + GPP_CLK6_REQ_SHIFT, + }; + + uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); + + pcie_gpp_dxio_update_clk_req_config(gpp_clk_config, gpp_clk_config_num); + for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { + gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); + /* + * The remapping of values is done so that the default of the enum used for the + * devicetree settings is the clock being enabled, so that a missing devicetree + * configuration for this will result in an always active clock and not an + * inactive PCIe clock output. Only the configuration for the clock outputs + * available on the package is provided via the devicetree; the rest is + * switched off unconditionally. + */ + switch (i < available_clk ? gpp_clk_config[i] : GPP_CLK_OFF) { + case GPP_CLK_REQ: + gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); + break; + case GPP_CLK_OFF: + gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); + break; + case GPP_CLK_ON: + default: + gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); + } + } + + misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); +} + diff --git a/src/soc/amd/common/block/include/amdblocks/gpp_clk.h b/src/soc/amd/common/block/include/amdblocks/gpp_clk.h new file mode 100644 index 0000000..db1cd1a --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/gpp_clk.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_GPP_H +#define AMD_BLOCK_GPP_H + +#include <amdblocks/pci_clk_req.h> + +#define GPP_CLK_CNTRL 0x00 +#define GPP_CLK0_REQ_SHIFT 0 +#define GPP_CLK1_REQ_SHIFT 2 +#define GPP_CLK4_REQ_SHIFT 4 +#define GPP_CLK2_REQ_SHIFT 6 +#define GPP_CLK3_REQ_SHIFT 8 +#define GPP_CLK5_REQ_SHIFT 10 +#define GPP_CLK6_REQ_SHIFT 12 +#define GPP_CLK_OUTPUT_COUNT 7 +#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) +#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) +#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) +#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift)) + +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ +void gpp_clk_setup_common(enum gpp_clk_req *gpp_clk_config, size_t gpp_clk_config_num, int available_clk); + +#endif /* AMD_BLOCK_GPP_H */ diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index fd40231..7d25406 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -44,6 +44,7 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES + select SOC_AMD_COMMON_BLOCK_GPP_CLK select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index c2f0558..afda533 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/gpp_clk.h> #include <amdblocks/pci_clk_req.h> #include <amdblocks/reset.h> #include <amdblocks/smi.h> @@ -126,46 +127,7 @@ static void gpp_clk_setup(void) { struct soc_amd_phoenix_config *cfg = config_of_soc(); - - /* look-up table to be able to iterate over the PCIe clock output settings */ - const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { - GPP_CLK0_REQ_SHIFT, - GPP_CLK1_REQ_SHIFT, - GPP_CLK2_REQ_SHIFT, - GPP_CLK3_REQ_SHIFT, - GPP_CLK4_REQ_SHIFT, - GPP_CLK5_REQ_SHIFT, - GPP_CLK6_REQ_SHIFT, - }; - - uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - - pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], - ARRAY_SIZE(cfg->gpp_clk_config)); - for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { - gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); - /* - * The remapping of values is done so that the default of the enum used for the - * devicetree settings is the clock being enabled, so that a missing devicetree - * configuration for this will result in an always active clock and not an - * inactive PCIe clock output. Only the configuration for the clock outputs - * available on the package is provided via the devicetree; the rest is - * switched off unconditionally. - */ - switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) { - case GPP_CLK_REQ: - gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); - break; - case GPP_CLK_OFF: - gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); - break; - case GPP_CLK_ON: - default: - gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); - } - } - - misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); + gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config), GPP_CLK_OUTPUT_AVAILABLE); } static void cgpll_clock_gate_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/80285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447 Gerrit-Change-Number: 80285 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: mb/up/squared: Make mini PCIe port mode configurable
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Reto Buerki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80261?usp=email ) Change subject: mb/up/squared: Make mini PCIe port mode configurable ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80261/comment/f512adf8_e708df3b : PS1, Line 11: Thank you for the patch. Could you elaborate, if the vendor firmware has the same option, or if it autodetects the mode? Patchset: PS1: Nice. Thank you for pushing this upstream. -- To view, visit https://review.coreboot.org/c/coreboot/+/80261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Gerrit-Change-Number: 80261 Gerrit-PatchSet: 1 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Thu, 01 Feb 2024 14:15:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: Add MTCL function to ACPI SSDT tables
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Cliff Huang, David Ruth, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80170?usp=email ) Change subject: Add MTCL function to ACPI SSDT tables ...................................................................... Patch Set 14: (2 comments) File src/drivers/wifi/generic/mtcl.c: https://review.coreboot.org/c/coreboot/+/80170/comment/199f722c_b2a4114b : PS14, Line 9: WIFI_MTCL_CBFS_DEFAULT_FILENAME "wifi_mtcl.hex" > This is the filename inside CBFS, as hardcoded in the Makefile.mk, isn't it? > The Kconfig is for the file path on the build host. i got confused with CONFIG_WIFI_MTCL_CBFS_FILEPATH which is a host file path https://review.coreboot.org/c/coreboot/+/80170/comment/f4a76bb7_bb97214c : PS14, Line 10: #define MAX_VERSION 2 : #define MAX_SUPPORT_STATE 2 : #define COUNTRY_LIST_SIZE 6 : #define NAME_SIZE 4 : #define MTCL_NAME "MTCL" > The API user doesn't need to know this, so I'd say no. for sure, for a moment i thought the header file is local to this directory -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 14 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 13:50:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: mb/google/brox: Enable HDA Codec ALC256
by Poornima Tom (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Paul Menzel, Shelley Chen, Vamshi Krishna Gopal, Vamshi Krishna Gopal. Poornima Tom has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79723?usp=email ) Change subject: mb/google/brox: Enable HDA Codec ALC256 ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79723/comment/3b075c50_a549d8da : PS5, Line 14: To verify HDA on Brox > Yes, I saw the device in sysfs: […] Thanks. Changed the Test desscription based on your test result in the new commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/79723?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1edd5aee053debe39b34048266703031c088cd00 Gerrit-Change-Number: 79723 Gerrit-PatchSet: 7 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 13:47:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Poornima Tom <poornima.tom(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: mb/google/brox: Enable HDA Codec ALC256
by Poornima Tom (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Paul Menzel, Poornima Tom, Shelley Chen, Vamshi Krishna Gopal, Vamshi Krishna Gopal. Hello Paul Menzel, Shelley Chen, Vamshi Krishna Gopal, Vamshi Krishna Gopal, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79723?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+1 by Vamshi Krishna Gopal, Code-Review+2 by Shelley Chen, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/brox: Enable HDA Codec ALC256 ...................................................................... mb/google/brox: Enable HDA Codec ALC256 On Brox, HDA Codec used is ALC256. Add verb table for the same. Also, add the related device tree changes for HDA related registers. Realtek High Definition Audio Configuration- Version : 5.0.3.1 BUG=b:317398558 BRANCH=None TEST=verified HDA on Brox. HDA Sound cards detected. Headphone working verified. Device listed under sysfs as below: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ID 256 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Change-Id: I1edd5aee053debe39b34048266703031c088cd00 Signed-off-by: Poornima Tom <poornima.tom(a)intel.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/Makefile.mk A src/mainboard/google/brox/hda_verb.c M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 4 files changed, 123 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/79723/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/79723?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1edd5aee053debe39b34048266703031c088cd00 Gerrit-Change-Number: 79723 Gerrit-PatchSet: 7 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: Add MTCL function to ACPI SSDT tables
by Nico Huber (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Cliff Huang, David Ruth, Lance Zhao, Subrata Banik, Subrata Banik, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80170?usp=email ) Change subject: Add MTCL function to ACPI SSDT tables ...................................................................... Patch Set 14: Code-Review+1 (4 comments) Patchset: PS14: One (hopefully) last thing: As USE_MTCL is `default n`, `mtcl.c` isn't covered by the CI. You can enable it by placing a config file (for any board you like) in `configs/` with `CONFIG_USE_MTCL=y`. The file name needs to match the board's Kconfig name (in lowercase), e.g. for CONFIG_BOARD_GOOGLE_REEF, files matching `config.google_reef*` are considered. (You could also add it to an existing file.) File src/drivers/wifi/generic/mtcl.c: https://review.coreboot.org/c/coreboot/+/80170/comment/bf34efcc_8a301a8b : PS14, Line 9: WIFI_MTCL_CBFS_DEFAULT_FILENAME "wifi_mtcl.hex" > nit: can we use `WIFI_MTCL_CBFS_FILEPATH` config directly here ? (instead of defining a new macro)? […] This is the filename inside CBFS, as hardcoded in the Makefile.mk, isn't it? The Kconfig is for the file path on the build host. https://review.coreboot.org/c/coreboot/+/80170/comment/00e4834e_1257ecd1 : PS14, Line 10: #define MAX_VERSION 2 : #define MAX_SUPPORT_STATE 2 : #define COUNTRY_LIST_SIZE 6 : #define NAME_SIZE 4 : #define MTCL_NAME "MTCL" > nit: wondering if moving these macros into mtcl.h makes sense. […] The API user doesn't need to know this, so I'd say no. File src/include/mtcl.h: PS14: Could move this to the wifi/generic/ driver, as it's only used there now. -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 14 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 13:09:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Config TCSS AUX according fw_config
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Dolan Liu, Eric Lai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Subrata Banik, Weimin Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80259?usp=email ) Change subject: mb/google/nissa/var/anraggar: Config TCSS AUX according fw_config ...................................................................... Patch Set 7: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80259/comment/e2a9fa05_4b61ad44 : PS7, Line 7: according according to https://review.coreboot.org/c/coreboot/+/80259/comment/046ae1d0_5d7c7dc9 : PS7, Line 8: Please start by describing the problem. https://review.coreboot.org/c/coreboot/+/80259/comment/16542495_c12ddf8e : PS7, Line 9: connect connects https://review.coreboot.org/c/coreboot/+/80259/comment/f77f2183_54578640 : PS7, Line 9: mini-build What is “mini-build”? https://review.coreboot.org/c/coreboot/+/80259/comment/f31f9389_ef789b6e : PS7, Line 9: add so add https://review.coreboot.org/c/coreboot/+/80259/comment/b6765522_d757bc96 : PS7, Line 10: feild field -- To view, visit https://review.coreboot.org/c/coreboot/+/80259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d Gerrit-Change-Number: 80259 Gerrit-PatchSet: 7 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 12:49:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: drivers/intel/gma: Add missing parentheses to brightness ACPI
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Felix Held, Felix Singer, Jonathon Hall. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80260?usp=email ) Change subject: drivers/intel/gma: Add missing parentheses to brightness ACPI ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Gerrit-Change-Number: 80260 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Feb 2024 12:03:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: i2c/drivers/generic: Add support for including a rotation matrix
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Sean Rhodes. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80179?usp=email ) Change subject: i2c/drivers/generic: Add support for including a rotation matrix ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80179/comment/aa0d92de_8590b484 : PS2, Line 14: linux It’d be great if you referenced the driver. https://review.coreboot.org/c/coreboot/+/80179/comment/52dc127d_78fc4ec0 : PS2, Line 16: How did you test this? -- To view, visit https://review.coreboot.org/c/coreboot/+/80179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4a940d999a0e300a6fe21269f18bab6e3c0523c Gerrit-Change-Number: 80179 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 01 Feb 2024 12:01:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/rex/var/karis: Follow rex0 CNVi/PCIe switching
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jack Lai, Jakub Czapiga, Kapil Porwal, Mac Chiang, Tarun, Tyler Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80215?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex/var/karis: Follow rex0 CNVi/PCIe switching ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80215/comment/d1d6156e_8861d53e : PS5, Line 9: Follow reference design rex0, keep the GPIO settings of CNVi/PCIe. Why? What are the problems with the current one, and why was this tried in the first place? -- To view, visit https://review.coreboot.org/c/coreboot/+/80215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id23a2cfe0639f2d423980db9badc16c1477434d1 Gerrit-Change-Number: 80215 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jack Lai <jack.lai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Jack Lai <jack.lai(a)intel.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 12:00:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2024