coreboot-gerrit February 2024

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[S] Change in coreboot[main]: soc/amd/*/root_complex: use unsigned long for resource index
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80267?usp=email ) Change subject: soc/amd/*/root_complex: use unsigned long for resource index ...................................................................... soc/amd/*/root_complex: use unsigned long for resource index Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0f58e32a535326116460545287cc59aaf94166a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80267 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/include/amdblocks/root_complex.h M src/soc/amd/common/fsp/fsp_report_resources.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 7 files changed, 7 insertions(+), 7 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Varshit Pandya: Looks good to me, approved diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index ad23306..20cea05 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -104,7 +104,7 @@ static void read_resources(struct device *dev) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned int idx = 0; + unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); diff --git a/src/soc/amd/common/block/include/amdblocks/root_complex.h b/src/soc/amd/common/block/include/amdblocks/root_complex.h index d774af0..0eef5e8 100644 --- a/src/soc/amd/common/block/include/amdblocks/root_complex.h +++ b/src/soc/amd/common/block/include/amdblocks/root_complex.h @@ -27,6 +27,6 @@ signed int get_iohc_fabric_id(struct device *domain); -void read_fsp_resources(struct device *dev, unsigned int *idx); +void read_fsp_resources(struct device *dev, unsigned long *idx); #endif /* AMD_BLOCK_ROOT_COMPLEX_H */ diff --git a/src/soc/amd/common/fsp/fsp_report_resources.c b/src/soc/amd/common/fsp/fsp_report_resources.c index bcc0715..37049fb 100644 --- a/src/soc/amd/common/fsp/fsp_report_resources.c +++ b/src/soc/amd/common/fsp/fsp_report_resources.c @@ -7,7 +7,7 @@ #include <fsp/util.h> #include <types.h> -void read_fsp_resources(struct device *dev, unsigned int *idx) +void read_fsp_resources(struct device *dev, unsigned long *idx) { const uint32_t mem_usable = (uintptr_t)cbmem_top(); const struct hob_header *hob_iterator; diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 10c3285..9b53a56 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -119,7 +119,7 @@ static void read_resources(struct device *dev) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned int idx = 0; + unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 706cc2e..886b54e 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -147,7 +147,7 @@ static void read_resources(struct device *dev) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned int idx = 0; + unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index ba263d5..82216ae 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -119,7 +119,7 @@ static void read_resources(struct device *dev) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned int idx = 0; + unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index f347dd0..0edd245 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -104,7 +104,7 @@ static void read_resources(struct device *dev) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned int idx = 0; + unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); -- To view, visit https://review.coreboot.org/c/coreboot/+/80267?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f58e32a535326116460545287cc59aaf94166a0 Gerrit-Change-Number: 80267 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/common/data_fabric/domain: use unsigned long for resource index
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80266?usp=email ) Change subject: soc/amd/common/data_fabric/domain: use unsigned long for resource index ...................................................................... soc/amd/common/data_fabric/domain: use unsigned long for resource index Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I60ac0e30627001698565b7256421780f9a94bf65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80266 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/root_complex.h M src/soc/amd/common/block/root_complex/non_pci_resources.c 3 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Varshit Pandya: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 7bcc01b..8533dff 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -78,7 +78,7 @@ return true; } -static void report_data_fabric_mmio(struct device *domain, unsigned int idx, +static void report_data_fabric_mmio(struct device *domain, unsigned long idx, resource_t mmio_base, resource_t mmio_limit) { struct resource *res; @@ -89,7 +89,7 @@ } /* Tell the resource allocator about the usable MMIO ranges configured in the data fabric */ -static void add_data_fabric_mmio_regions(struct device *domain, unsigned int *idx) +static void add_data_fabric_mmio_regions(struct device *domain, unsigned long *idx) { const signed int iohc_dest_fabric_id = get_iohc_fabric_id(domain); union df_mmio_control ctrl; @@ -140,7 +140,7 @@ } } -static void report_data_fabric_io(struct device *domain, unsigned int idx, +static void report_data_fabric_io(struct device *domain, unsigned long idx, resource_t io_base, resource_t io_limit) { struct resource *res; @@ -151,7 +151,7 @@ } /* Tell the resource allocator about the usable I/O space */ -static void add_data_fabric_io_regions(struct device *domain, unsigned int *idx) +static void add_data_fabric_io_regions(struct device *domain, unsigned long *idx) { const signed int iohc_dest_fabric_id = get_iohc_fabric_id(domain); union df_io_base base_reg; @@ -193,7 +193,7 @@ void amd_pci_domain_read_resources(struct device *domain) { - unsigned int idx = 0; + unsigned long idx = 0; add_data_fabric_io_regions(domain, &idx); diff --git a/src/soc/amd/common/block/include/amdblocks/root_complex.h b/src/soc/amd/common/block/include/amdblocks/root_complex.h index dd0e68a..d774af0 100644 --- a/src/soc/amd/common/block/include/amdblocks/root_complex.h +++ b/src/soc/amd/common/block/include/amdblocks/root_complex.h @@ -20,7 +20,7 @@ unsigned long res_idx; /* Use NON_PCI_RES_IDX_AUTO or a specific resource index */ }; -void read_non_pci_resources(struct device *domain, unsigned int *idx); +void read_non_pci_resources(struct device *domain, unsigned long *idx); uint32_t get_iohc_misc_smn_base(struct device *domain); const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count); diff --git a/src/soc/amd/common/block/root_complex/non_pci_resources.c b/src/soc/amd/common/block/root_complex/non_pci_resources.c index 31f4eb0..54f3de2 100644 --- a/src/soc/amd/common/block/root_complex/non_pci_resources.c +++ b/src/soc/amd/common/block/root_complex/non_pci_resources.c @@ -7,7 +7,7 @@ #define IOHC_MMIO_EN BIT(0) -void read_non_pci_resources(struct device *domain, unsigned int *idx) +void read_non_pci_resources(struct device *domain, unsigned long *idx) { const uint32_t iohc_misc_base = get_iohc_misc_smn_base(domain); const struct non_pci_mmio_reg *regs; -- To view, visit https://review.coreboot.org/c/coreboot/+/80266?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60ac0e30627001698565b7256421780f9a94bf65 Gerrit-Change-Number: 80266 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource index
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80265?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource index ...................................................................... vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource index Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct and the functions to report the resources. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iccc2e0556ce8688d933506e0db5cc4b83c66ac76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80265 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/amd/opensil/genoa_poc/memmap.c M src/vendorcode/amd/opensil/genoa_poc/opensil.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index 4e5b457..8b54b5f 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -84,7 +84,7 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL); // This assumes holes are allocated -int add_opensil_memmap(struct device *dev, int idx) +unsigned long add_opensil_memmap(struct device *dev, unsigned long idx) { ram_from_to(dev, idx++, 0, 0xa0000); mmio_from_to(dev, idx++, 0xa0000, 0xc0000); // legacy VGA diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h index 473238d..77b3c4b 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h @@ -8,7 +8,7 @@ void SIL_STATUS_report(const char *function, const int status); // Add the memory map to dev, starting at index idx, returns last use idx -int add_opensil_memmap(struct device *dev, int idx); +unsigned long add_opensil_memmap(struct device *dev, unsigned long idx); // Fill in FADT from openSIL void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); -- To view, visit https://review.coreboot.org/c/coreboot/+/80265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccc2e0556ce8688d933506e0db5cc4b83c66ac76 Gerrit-Change-Number: 80265 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/common,genoa_poc/domain: rework check for 1st domain
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79996?usp=email ) Change subject: soc/amd/common,genoa_poc/domain: rework check for 1st domain ...................................................................... soc/amd/common,genoa_poc/domain: rework check for 1st domain Previously the code checked if the first downstream bus of the domain was bus 0 in segment group 0 to only run certain code for the first domain. Instead check if the domain number is 0 which should make the code a bit easier to understand. TEST=add_opensil_memmap still gets called exactly once on Onyx Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id8cc0078843e5e0361a53ba897cde508cee16aad Reviewed-on: https://review.coreboot.org/c/coreboot/+/79996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/genoa_poc/domain.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index f17346f..7bcc01b 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -254,7 +254,7 @@ acpigen_resource_producer_bus_number(domain->downstream->secondary, domain->downstream->max_subordinate); - if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) { + if (domain->path.domain.domain == 0) { /* ACPI 6.4.2.5 I/O Port Descriptor */ acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, PCI_IO_CONFIG_PORT_COUNT, 1); diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 57e020a..653e2d2 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -18,7 +18,7 @@ amd_pci_domain_read_resources(domain); // We only want to add the DRAM memory map once - if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) { + if (domain->path.domain.domain == 0) { /* 0x1000 is a large enough first index to be sure to not overlap with the resources added by amd_pci_domain_read_resources */ add_opensil_memmap(domain, 0x1000); -- To view, visit https://review.coreboot.org/c/coreboot/+/79996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8cc0078843e5e0361a53ba897cde508cee16aad Gerrit-Change-Number: 79996 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/nissa: Create yavista variant
by Garen Wu (Code Review) 01 Feb '24

01 Feb '24

Garen Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80284?usp=email ) Change subject: mb/google/nissa: Create yavista variant ...................................................................... mb/google/nissa: Create yavista variant Create the yavista variant of the nissa reference board by copying the template files to a new directory named for the variant. BUG=b:321583226 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVISTA Change-Id: I34af51ebd0638f89333e0098c25f805e3619863b Signed-off-by: wu.garen <wu.garen(a)inventec.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/yavista/include/variant/ec.h A src/mainboard/google/brya/variants/yavista/include/variant/gpio.h A src/mainboard/google/brya/variants/yavista/memory/Makefile.mk A src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/yavista/overridetree.cb 8 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/80284/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index dae3f16..4cad7c0 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -583,6 +583,7 @@ default 0x1 if BOARD_GOOGLE_DOCHI default 0x0 if BOARD_GOOGLE_QUANDISO default 0x0 if BOARD_GOOGLE_ANRAGGAR + default 0x0 if BOARD_GOOGLE_YAVISTA config DRIVER_TPM_I2C_ADDR hex @@ -666,6 +667,7 @@ default "Dochi" if BOARD_GOOGLE_DOCHI default "Anraggar" if BOARD_GOOGLE_ANRAGGAR default "Xol" if BOARD_GOOGLE_XOL + default "Yavista" if BOARD_GOOGLE_YAVISTA config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -720,6 +722,7 @@ default "dochi" if BOARD_GOOGLE_DOCHI default "anraggar" if BOARD_GOOGLE_ANRAGGAR default "xol" if BOARD_GOOGLE_XOL + default "yavista" if BOARD_GOOGLE_YAVISTA config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index dcdf3c7..7e923be 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -155,3 +155,6 @@ config BOARD_GOOGLE_XOL bool "-> Xol" + +config BOARD_GOOGLE_YAVISTA + bool "-> Yavista" diff --git a/src/mainboard/google/brya/variants/yavista/include/variant/ec.h b/src/mainboard/google/brya/variants/yavista/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h b/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk new file mode 100644 index 0000000..a9f9ab7 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/yaviks/memory/ src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt new file mode 100644 index 0000000..1be3fe0 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/yaviks/memory/ src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt + +DRAM Part Name ID to assign + diff --git a/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt new file mode 100644 index 0000000..73c95bf --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt @@ -0,0 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name + diff --git a/src/mainboard/google/brya/variants/yavista/overridetree.cb b/src/mainboard/google/brya/variants/yavista/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/80284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34af51ebd0638f89333e0098c25f805e3619863b Gerrit-Change-Number: 80284 Gerrit-PatchSet: 1 Gerrit-Owner: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: util/ifdtool: Add a new switch -E to protect GPR0
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Stefan Reinauer, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80235?usp=email ) Change subject: util/ifdtool: Add a new switch -E to protect GPR0 ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Patchset: PS6: Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/80235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Gerrit-Change-Number: 80235 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 10:22:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: util/ifdtool: Add a new switch -E to protect GPR0
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Paul Menzel, Stefan Reinauer. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80235?usp=email ) Change subject: util/ifdtool: Add a new switch -E to protect GPR0 ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80235/comment/2bae1a07_d40819e0 : PS5, Line 7: Add new cmdline to enable GPR0 protection > Maybe: […] Acknowledged https://review.coreboot.org/c/coreboot/+/80235/comment/bb865e4e_31aafaa7 : PS5, Line 9: IFD Tool > I have not seen that spelling – only ifdtool. Acknowledged https://review.coreboot.org/c/coreboot/+/80235/comment/79269e9c_7cf74c0a : PS5, Line 11: Additionally, perform some code refactoring while adding support > It’d be great, if you added a blank line between paragraphs. Acknowledged https://review.coreboot.org/c/coreboot/+/80235/comment/2cd2bbb8_58165990 : PS5, Line 13: > Can you point to a document, where more information about GPR0 protection can be found? Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Gerrit-Change-Number: 80235 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 09:11:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/byra/var/anraggar: Set WLAN device type back to pci
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80278?usp=email ) Change subject: mb/google/byra/var/anraggar: Set WLAN device type back to pci ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80278/comment/7a246cba_3382e253 : PS8, Line 10: ("mb/google/byra/var/*: Set WLAN device type back to pci"). Set the WLAN device type to pci uniformly. Please wrap the line at 72 characters. https://review.coreboot.org/c/coreboot/+/80278/comment/7382a8a8_063dd3e1 : PS8, Line 11: Commit messages need to be self-sufficient. Please state the problem and the solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/80278?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a33362e28c3b9027e9cc5a2e11dc0c316acbd69 Gerrit-Change-Number: 80278 Gerrit-PatchSet: 8 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 08:45:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/dochi: Adjust I2C3 to ensure touchscreen is work.
by Morris Hsu (Code Review) 01 Feb '24

01 Feb '24

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80283?usp=email ) Change subject: mb/google/brya/var/dochi: Adjust I2C3 to ensure touchscreen is work. ...................................................................... mb/google/brya/var/dochi: Adjust I2C3 to ensure touchscreen is work. Tune I2C3 frequency. BUG=b:318339970 TEST=emerge-brya coreboot chromeos-bootimage and touchpanel function is normal. Change-Id: I7d702aee46e754480b15ea5087f8c678d3b0e4ec Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dochi/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/80283/1 diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb index 880b7bc..671eeff 100644 --- a/src/mainboard/google/brya/variants/dochi/overridetree.cb +++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb @@ -75,6 +75,12 @@ .rise_time_ns = 550, .fall_time_ns = 400, .data_hold_time_ns = 50, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 110, + .sda_hold = 40, + } }, .i2c[5] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/80283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d702aee46e754480b15ea5087f8c678d3b0e4ec Gerrit-Change-Number: 80283 Gerrit-PatchSet: 1 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: util/ifdtool: Add new cmdline to enable GPR0 protection
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Stefan Reinauer, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80235?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: util/ifdtool: Add new cmdline to enable GPR0 protection ...................................................................... Patch Set 5: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80235/comment/a76ef596_4fe370bf : PS5, Line 7: Add new cmdline to enable GPR0 protection Maybe: > Add new switch -E to protect GPR0 https://review.coreboot.org/c/coreboot/+/80235/comment/6cdce12c_c803d389 : PS5, Line 9: IFD Tool I have not seen that spelling – only ifdtool. https://review.coreboot.org/c/coreboot/+/80235/comment/2dd6bc72_7a0ae47e : PS5, Line 11: Additionally, perform some code refactoring while adding support It’d be great, if you added a blank line between paragraphs. https://review.coreboot.org/c/coreboot/+/80235/comment/acbdf667_49bf2100 : PS5, Line 13: Can you point to a document, where more information about GPR0 protection can be found? -- To view, visit https://review.coreboot.org/c/coreboot/+/80235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Gerrit-Change-Number: 80235 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 07:38:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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