coreboot-gerrit February 2024

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[M] Change in coreboot[master]: mb/google/nissa: Create yavista variant
by Garen Wu (Code Review) 01 Feb '24

01 Feb '24

Garen Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80282?usp=email ) Change subject: mb/google/nissa: Create yavista variant ...................................................................... mb/google/nissa: Create yavista variant Create the yavista variant of the nissa reference board by copying the template files to a new directory named for the variant. BUG=b:321583226 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVISTA Change-Id: I09f733188f8c8de9d60ac83f0a55ea78fb07b187 Signed-off-by: wu.garen <wu.garen(a)inventec.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/yavista/include/variant/ec.h A src/mainboard/google/brya/variants/yavista/include/variant/gpio.h A src/mainboard/google/brya/variants/yavista/memory/Makefile.mk A src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/yavista/overridetree.cb 8 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/80282/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index dae3f16..4cad7c0 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -583,6 +583,7 @@ default 0x1 if BOARD_GOOGLE_DOCHI default 0x0 if BOARD_GOOGLE_QUANDISO default 0x0 if BOARD_GOOGLE_ANRAGGAR + default 0x0 if BOARD_GOOGLE_YAVISTA config DRIVER_TPM_I2C_ADDR hex @@ -666,6 +667,7 @@ default "Dochi" if BOARD_GOOGLE_DOCHI default "Anraggar" if BOARD_GOOGLE_ANRAGGAR default "Xol" if BOARD_GOOGLE_XOL + default "Yavista" if BOARD_GOOGLE_YAVISTA config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -720,6 +722,7 @@ default "dochi" if BOARD_GOOGLE_DOCHI default "anraggar" if BOARD_GOOGLE_ANRAGGAR default "xol" if BOARD_GOOGLE_XOL + default "yavista" if BOARD_GOOGLE_YAVISTA config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index dcdf3c7..7e923be 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -155,3 +155,6 @@ config BOARD_GOOGLE_XOL bool "-> Xol" + +config BOARD_GOOGLE_YAVISTA + bool "-> Yavista" diff --git a/src/mainboard/google/brya/variants/yavista/include/variant/ec.h b/src/mainboard/google/brya/variants/yavista/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h b/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk new file mode 100644 index 0000000..a9f9ab7 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/yaviks/memory/ src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt new file mode 100644 index 0000000..1be3fe0 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/yaviks/memory/ src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt + +DRAM Part Name ID to assign + diff --git a/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt new file mode 100644 index 0000000..73c95bf --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt @@ -0,0 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name + diff --git a/src/mainboard/google/brya/variants/yavista/overridetree.cb b/src/mainboard/google/brya/variants/yavista/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/80282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09f733188f8c8de9d60ac83f0a55ea78fb07b187 Gerrit-Change-Number: 80282 Gerrit-PatchSet: 1 Gerrit-Owner: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: libpayload: Switch to commonlib ipchksum() algorithm
by Jakub Czapiga (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Julius Werner. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80253?usp=email ) Change subject: libpayload: Switch to commonlib ipchksum() algorithm ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8d323ce9f8d946758619761b4b22d54bce222b6 Gerrit-Change-Number: 80253 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 06:50:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: tests: Add some more ipchksum() test cases
by Jakub Czapiga (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Julius Werner. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80252?usp=email ) Change subject: tests: Add some more ipchksum() test cases ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39b4d3f1bb833894985649872329eec88a02a22c Gerrit-Change-Number: 80252 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 06:49:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa: Create yavista variant
by Garen Wu (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Garen Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80281?usp=email ) Change subject: mb/google/nissa: Create yavista variant ...................................................................... mb/google/nissa: Create yavista variant Create the yavista variant of the nissa reference board by copying the template files to a new directory named for the variant. BUG=b:321583226 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVISTA Change-Id: I276a2b2f5a6d8e613992defb791e872902d91fec Signed-off-by: wu.garen <wu.garen(a)inventec.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/yavista/include/variant/ec.h A src/mainboard/google/brya/variants/yavista/include/variant/gpio.h A src/mainboard/google/brya/variants/yavista/memory/Makefile.mk A src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/yavista/overridetree.cb 8 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/80281/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index dae3f16..91bc0b8 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -583,6 +583,7 @@ default 0x1 if BOARD_GOOGLE_DOCHI default 0x0 if BOARD_GOOGLE_QUANDISO default 0x0 if BOARD_GOOGLE_ANRAGGAR + default 0x0 if BOARD_GOOGLE_YAVISTA config DRIVER_TPM_I2C_ADDR hex @@ -666,6 +667,7 @@ default "Dochi" if BOARD_GOOGLE_DOCHI default "Anraggar" if BOARD_GOOGLE_ANRAGGAR default "Xol" if BOARD_GOOGLE_XOL + default "Yavista" if BOARD_GOOGLE_YAVISTA config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -720,6 +722,7 @@ default "dochi" if BOARD_GOOGLE_DOCHI default "anraggar" if BOARD_GOOGLE_ANRAGGAR default "xol" if BOARD_GOOGLE_XOL + default "yaviks" if BOARD_GOOGLE_YAVISTA config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index dcdf3c7..7e923be 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -155,3 +155,6 @@ config BOARD_GOOGLE_XOL bool "-> Xol" + +config BOARD_GOOGLE_YAVISTA + bool "-> Yavista" diff --git a/src/mainboard/google/brya/variants/yavista/include/variant/ec.h b/src/mainboard/google/brya/variants/yavista/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h b/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk new file mode 100644 index 0000000..a9f9ab7 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/yaviks/memory/ src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt new file mode 100644 index 0000000..1be3fe0 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/yaviks/memory/ src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt + +DRAM Part Name ID to assign + diff --git a/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt new file mode 100644 index 0000000..73c95bf --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt @@ -0,0 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name + diff --git a/src/mainboard/google/brya/variants/yavista/overridetree.cb b/src/mainboard/google/brya/variants/yavista/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/80281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I276a2b2f5a6d8e613992defb791e872902d91fec Gerrit-Change-Number: 80281 Gerrit-PatchSet: 1 Gerrit-Owner: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/rex/variants/deku: Add H58G66BK7BX067 to RAM ID table
by Garen Wu (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eran Mitrani, Kapil Porwal, Kevin Chiu, Subrata Banik, Tony Huang. Hello build bot (Jenkins), Kevin Chiu, Eran Mitrani, Tony Huang, Subrata Banik, Kapil Porwal, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/80280?usp=email to review the following change. Change subject: mb/google/rex/variants/deku: Add H58G66BK7BX067 to RAM ID table ...................................................................... mb/google/rex/variants/deku: Add H58G66BK7BX067 to RAM ID table Add RAM ID for H58G66BK7BX067 0 (0000) BUG=b:322528721 BRANCH=firmware-rex-15709.B TEST=Run part_id_gen tool without any errors Change-Id: I31538988d1329d9e2f45d862eb0ae05c0d6a179e Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80230 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eran Mitrani <mitrani(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/deku/memory/Makefile.mk M src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt M src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/80280/1 diff --git a/src/mainboard/google/rex/variants/deku/memory/Makefile.mk b/src/mainboard/google/rex/variants/deku/memory/Makefile.mk index 9620b9c..e7518ed 100644 --- a/src/mainboard/google/rex/variants/deku/memory/Makefile.mk +++ b/src/mainboard/google/rex/variants/deku/memory/Makefile.mk @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build2560620659/b001/exe/part_id_gen MTL lp5 src/mainboard/google/rex/variants/deku/memory src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/deku/memory src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 0(0b0000) Parts = MT62F2G32D4DS-026 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 0(0b0000) Parts = MT62F2G32D4DS-026 WT:B, H58G66BK7BX067 diff --git a/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt index 21b3f69..0e3a06a 100644 --- a/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt +++ b/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build2560620659/b001/exe/part_id_gen MTL lp5 src/mainboard/google/rex/variants/deku/memory src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/deku/memory src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt DRAM Part Name ID to assign MT62F2G32D4DS-026 WT:B 0 (0000) +H58G66BK7BX067 0 (0000) diff --git a/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt index 53ec721..0871f3c 100644 --- a/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt +++ b/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt @@ -10,3 +10,4 @@ # Part Name MT62F2G32D4DS-026 WT:B +H58G66BK7BX067 -- To view, visit https://review.coreboot.org/c/coreboot/+/80280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31538988d1329d9e2f45d862eb0ae05c0d6a179e Gerrit-Change-Number: 80280 Gerrit-PatchSet: 1 Gerrit-Owner: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: Add MTCL function to ACPI SSDT tables
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Cliff Huang, David Ruth, Lance Zhao, Nico Huber, Paul Menzel, Subrata Banik, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80170?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Add MTCL function to ACPI SSDT tables ...................................................................... Patch Set 14: (2 comments) File src/drivers/wifi/generic/mtcl.c: https://review.coreboot.org/c/coreboot/+/80170/comment/e06bb933_efe9128d : PS14, Line 9: WIFI_MTCL_CBFS_DEFAULT_FILENAME "wifi_mtcl.hex" nit: can we use `WIFI_MTCL_CBFS_FILEPATH` config directly here ? (instead of defining a new macro)? just update the default value directly to the WIFI_MTCL_CBFS_FILEPATH config https://review.coreboot.org/c/coreboot/+/80170/comment/0a8e4ff1_7215ac42 : PS14, Line 10: #define MAX_VERSION 2 : #define MAX_SUPPORT_STATE 2 : #define COUNTRY_LIST_SIZE 6 : #define NAME_SIZE 4 : #define MTCL_NAME "MTCL" nit: wondering if moving these macros into mtcl.h makes sense.? -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 14 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 05:17:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: WIP: mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 01 Feb '24

01 Feb '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80279?usp=email ) Change subject: WIP: mainboard/lenovo: Add ThinkCentre M710s ...................................................................... WIP: mainboard/lenovo: Add ThinkCentre M710s Working: - Can boot Ubuntu LiveCD using SeaBIOS as a payload - PCIe - M2 SSD - SATA - USB - LAN - CPU fan - VGA (DP bridge) - COM1 - libgfxinit (probably?) - TPM Not Working / Not Tested: - TianoCore - M2 WLAN - PS/2 keyboard and mouse - Audio - Display port - Memory card reader - PCIe clock related things and AER issues - SuperIO related things Won't Test: - COM2 header - LPT header Change-Id: Ic75164af96b05c2a15d7feaa71f231d2b3b0d922 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- A src/mainboard/lenovo/thinkcentre_m710s/Kconfig A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c A src/mainboard/lenovo/thinkcentre_m710s/data.vbt A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl A src/mainboard/lenovo/thinkcentre_m710s/early_init.c A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m710s/gpio.h A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c A src/mainboard/lenovo/thinkcentre_m710s/romstage.c 15 files changed, 563 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80279/1 diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig new file mode 100644 index 0000000..3996915 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_LENOVO_THINKCENTRE_M710S + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select SUPERIO_ITE_IT8728F + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + +config MAINBOARD_DIR + default "lenovo/thinkcentre_m710s" + +config MAINBOARD_PART_NUMBER + default "ThinkCentre M710s" + +endif # BOARD_LENOVO_THINKCENTRE_M710S diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name new file mode 100644 index 0000000..5a78582 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_LENOVO_THINKCENTRE_M710S + bool "ThinkCentre M710s" diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk b/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk new file mode 100644 index 0000000..5224305 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += bootblock.c + +ramstage-y += early_init.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl b/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt b/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt new file mode 100644 index 0000000..8379586 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://psref.lenovo.com/syspool/Sys/PDF/ThinkCentre/ThinkCentre_M710_SFF/T… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c b/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c new file mode 100644 index 0000000..77b0a96 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +#include "gpio.h" + +void bootblock_mainboard_init(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/lenovo/thinkcentre_m710s/data.vbt b/src/mainboard/lenovo/thinkcentre_m710s/data.vbt new file mode 100644 index 0000000..4855687 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb new file mode 100644 index 0000000..d4ffdd3 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + # FSP Configuration + register "eist_enable" = "true" + + device cpu_cluster 0 on end + device domain 0 on + device ref system_agent on end + device ref peg0 on # PCIE16X + #register "PcieRpClkReqSupport[0]" = "true" + #register "PcieRpClkReqNumber[0]" = "2" + #register "PcieRpClkSrcNumber[0]" = "0" + end + device ref igpu on end + device ref south_xhci on + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB30 A + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB30 B + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # F_USB30_1 A + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # F_USB30_1 B + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # F_USB30_2 A + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # F_USB30_2 B + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + register "usb2_ports[7]" = "USB2_PORT_MID(OC5)" # USB_LAN A + register "usb2_ports[8]" = "USB2_PORT_MID(OC5)" # USB_LAN B + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F_USB1 (pins 5, 7) + register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # F_USB1 (pins 6, 8) + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # F_USB2 (pins 5, 7) + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB30 A + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB30 B + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # F_USB30_1 A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # F_USB30_1 B + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # F_USB30_2 A + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)" # F_USB30_2 B + end + device ref thermal on end + device ref heci1 on end + device ref sata on + register "SataMode" = "SATA_AHCI" + register "SataSalpSupport" = "true" + register "SataPortsEnable[0]" = "true" # SATA1 + register "SataPortsEnable[1]" = "true" # SATA2 + register "SataPortsEnable[2]" = "true" # SATA3 + end + device ref pcie_rp5 on # USB_LAN + register "PcieRpEnable[4]" = "true" + register "PcieRpLtrEnable[4]" = "true" + #register "PcieRpClkReqSupport[4]" = "true" + #register "PcieRpClkReqNumber[4]" = "5" + #register "PcieRpClkSrcNumber[4]" = "5" + register "PcieRpAdvancedErrorReporting[4]" = "true" + end + device ref pcie_rp7 on # PCIE1X_2 + register "PcieRpEnable[6]" = "true" + register "PcieRpLtrEnable[6]" = "true" + #register "PcieRpClkReqSupport[6]" = "true" + #register "PcieRpClkReqNumber[6]" = "7" + #register "PcieRpClkSrcNumber[6]" = "7" + register "PcieRpAdvancedErrorReporting[6]" = "true" + end + device ref pcie_rp8 on # PCIE1X_1 + register "PcieRpEnable[7]" = "true" + register "PcieRpLtrEnable[7]" = "true" + #register "PcieRpClkReqSupport[7]" = "true" + #register "PcieRpClkReqNumber[7]" = "8" + #register "PcieRpClkSrcNumber[7]" = "8" + register "PcieRpAdvancedErrorReporting[7]" = "true" + end + device ref pcie_rp11 on # M2_WIFI + register "PcieRpEnable[10]" = "true" + register "PcieRpLtrEnable[10]" = "true" + #register "PcieRpClkReqSupport[10]" = "true" + #register "PcieRpClkReqNumber[10]" = "1" + #register "PcieRpClkSrcNumber[10]" = "1" + register "PcieRpAdvancedErrorReporting[10]" = "true" + end + device ref pcie_rp21 on # M2_SSD + register "PcieRpEnable[20]" = "true" + register "PcieRpLtrEnable[20]" = "true" + #register "PcieRpClkReqSupport[20]" = "true" + #register "PcieRpClkReqNumber[20]" = "6" + #register "PcieRpClkSrcNumber[20]" = "2" + register "PcieRpAdvancedErrorReporting[20]" = "true" + end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip superio/ite/it8728f + # CPU_FAN + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "35" + register "FAN1.smart.tmp_start" = "60" + register "FAN1.smart.tmp_full" = "85" + register "FAN1.smart.tmp_delta" = "2" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "24" + + device pnp 2e.0 off end + device pnp 2e.1 on + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # TODO + device pnp 2e.3 off end # TODO + device pnp 2e.4 off end # TODO + device pnp 2e.5 off end # TODO + device pnp 2e.6 off end # TODO + device pnp 2e.7 off end # TODO + end + chip drivers/pc80/tpm + device pnp c31.0 on end + end + end + device ref pmc on end + device ref hda on end + device ref smbus on end + device ref gbe on end # USB_LAN (Maps to PCIe Root Port 5) + end +end diff --git a/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl b/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl new file mode 100644 index 0000000..184fee0 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/thinkcentre_m710s/early_init.c b/src/mainboard/lenovo/thinkcentre_m710s/early_init.c new file mode 100644 index 0000000..3c81c80 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/early_init.c @@ -0,0 +1,14 @@ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x23, 0x49); + ite_reg_write(GPIO_DEV, 0x71, 0x09); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads b/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads new file mode 100644 index 0000000..36094f5 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- TODO + ports : constant Port_List := + (DP1, + DP2, + DP3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/thinkcentre_m710s/gpio.h b/src/mainboard/lenovo/thinkcentre_m710s/gpio.h new file mode 100644 index 0000000..1cd7d25 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/gpio.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_CFG_GPO(GPP_A20, 1, PLTRST), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 1, PLTRST), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_B3, NONE), + _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_GPO(GPP_B12, 1, DEEP), + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_NC(GPP_B19, NONE), + _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + PAD_CFG_GPO(GPP_C13, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 0, PLTRST), + PAD_NC(GPP_D15, NONE), + _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_G12, NONE), + PAD_NC(GPP_G13, NONE), + PAD_NC(GPP_G14, NONE), + PAD_NC(GPP_G15, NONE), + PAD_NC(GPP_G16, NONE), + PAD_NC(GPP_G17, NONE), + PAD_NC(GPP_G18, NONE), + PAD_NC(GPP_G19, NONE), + PAD_CFG_GPO(GPP_G20, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_G21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_G22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_G23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Group GPP_H ------- */ + _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPO(GPP_H4, 1, PLTRST), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_NC(GPP_H18, NONE), + PAD_NC(GPP_H19, NONE), + _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + _PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPD7, 1, PWROK), + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPD11, 1, PWROK), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPO(GPP_I5, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c b/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c new file mode 100644 index 0000000..f18aa0c --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +#define REALTEK_ACL662_VENDOR_ID 0x10ec0662 +#define REALTEK_ACL662_SUBSYSTEM_ID 0x17aa3102 +#define REALTEK_ACL662_CODEC 0 +#define REALTEK_ACL662_PIN_CFG(pin, val) \ + AZALIA_PIN_CFG(REALTEK_ACL662_CODEC, pin, val) + +#define INTEL_KBL_HDMI_VENDOR_ID 0x8086280b +#define INTEL_KBL_HDMI_SUBSYSTEM_ID 0x80860101 +#define INTEL_KBL_HDMI_CODEC 2 +#define INTEL_KBL_HDMI_PIN_CFG(pin, val) \ + AZALIA_PIN_CFG(INTEL_KBL_HDMI_CODEC, pin, val) + +const u32 cim_verb_data[] = { + REALTEK_ACL662_VENDOR_ID, + REALTEK_ACL662_SUBSYSTEM_ID, + 12, + AZALIA_SUBVENDOR(REALTEK_ACL662_CODEC, REALTEK_ACL662_SUBSYSTEM_ID), + REALTEK_ACL662_PIN_CFG(0x12, 0x40000000), + REALTEK_ACL662_PIN_CFG(0x14, 0x01014010), + REALTEK_ACL662_PIN_CFG(0x15, 0x90170120), + REALTEK_ACL662_PIN_CFG(0x16, 0x411111f0), + REALTEK_ACL662_PIN_CFG(0x18, 0x01a19030), + REALTEK_ACL662_PIN_CFG(0x19, 0x02a11040), + REALTEK_ACL662_PIN_CFG(0x1a, 0x0181303f), + REALTEK_ACL662_PIN_CFG(0x1b, 0x0221101f), + REALTEK_ACL662_PIN_CFG(0x1c, 0x411111f0), + REALTEK_ACL662_PIN_CFG(0x1d, 0x4047c62b), + REALTEK_ACL662_PIN_CFG(0x1e, 0x411111f0), + + INTEL_KBL_HDMI_VENDOR_ID, + INTEL_KBL_HDMI_SUBSYSTEM_ID, + 4, + AZALIA_SUBVENDOR(INTEL_KBL_HDMI_CODEC, INTEL_KBL_HDMI_SUBSYSTEM_ID), + INTEL_KBL_HDMI_PIN_CFG(0x05, 0x58560010), + INTEL_KBL_HDMI_PIN_CFG(0x06, 0x18560020), + INTEL_KBL_HDMI_PIN_CFG(0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/thinkcentre_m710s/romstage.c b/src/mainboard/lenovo/thinkcentre_m710s/romstage.c new file mode 100644 index 0000000..65cd625 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <stdint.h> +#include <string.h> + +#include <soc/romstage.h> +#include <spd_bin.h> + +const u16 rcomp_resistors[] = {121, 75, 100}; +const u16 rcomp_targets[] = {50, 26, 20, 20, 26}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + struct spd_block blk = { + .addr_map = {0x50, 0x51, 0x52, 0x53}, + }; + + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr01 = (uintptr_t) blk.spd_array[1]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[2]; + mem_cfg->MemorySpdPtr11 = (uintptr_t) blk.spd_array[3]; + dump_spd_info(&blk); + + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80279?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic75164af96b05c2a15d7feaa71f231d2b3b0d922 Gerrit-Change-Number: 80279 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80277?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits ...................................................................... Patch Set 2: (15 comments) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/80277/comment/b7cac58d_5d46c73c : PS2, Line 62: Starting with FSP specification 2.4 they can be 64-bits. i thought u said elsewhere that FSP 2.4 also supports 32-bit? base don line#58, I'm unable to follow how can one select 32-bit flow of FSP2.4? File src/drivers/intel/fsp2_0/debug.c: https://review.coreboot.org/c/coreboot/+/80277/comment/a99d878f_bd6645fc : PS2, Line 94: efi_return_status_t need to include `#include <efi/efi_datatype.h>` https://review.coreboot.org/c/coreboot/+/80277/comment/94fc20ac_b4afbb7a : PS2, Line 97: status why not use `size_t status` directly ? File src/drivers/intel/fsp2_0/include/fsp/api.h: https://review.coreboot.org/c/coreboot/+/80277/comment/d533c158_ac7a74d7 : PS2, Line 11: #define __efiapi EFIAPI why not inside `efi_datatype.h` file ? File src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h: https://review.coreboot.org/c/coreboot/+/80277/comment/5af5574e_b4bbae99 : PS2, Line 13: #include <efi/efi_datatype.h> order ? File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/80277/comment/aa66f7a4_94cfe2a2 : PS2, Line 39: #if CONFIG(PLATFORM_USES_FSP2_4) look at line #36, i don;t think u need a guard here as well. we are not using sizeof(fsp_header) anywhere IMO File src/drivers/intel/fsp2_0/include/fsp/soc_binding.h: https://review.coreboot.org/c/coreboot/+/80277/comment/8cd4782c_ddb89ade : PS2, Line 8: #if CONFIG(VENDOR_INTEL) why Intel? this is UEFI calling convention and nothing SoC vendor specific also use edi_datatype.h for keeping UEFI specific declaration File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/80277/comment/1472693a_20af67e1 : PS2, Line 282: efi_return_status_t size_t? File src/include/efi/efi_datatype.h: https://review.coreboot.org/c/coreboot/+/80277/comment/026ab103_0a14713b : PS2, Line 81: statuses ??? https://review.coreboot.org/c/coreboot/+/80277/comment/da9a9bfc_123a4adc : PS2, Line 88: _Static_assert(sizeof(size_t) == sizeof(efi_return_status_t), : "Unexpected EFI_STATUS size"); if u use `size_t` over `efi_return_status_t` then I don't believe u need this logic File src/soc/intel/xeon_sp/bootblock.c: https://review.coreboot.org/c/coreboot/+/80277/comment/7648b325_394a4246 : PS2, Line 5: #include <fsp/util.h> please submit this cl separately https://review.coreboot.org/c/coreboot/+/80277/comment/aba490be_58eccd89 : PS2, Line 9: #include <soc/iomap.h> same https://review.coreboot.org/c/coreboot/+/80277/comment/6fd5b5ba_9a5d1e1f : PS2, Line 10: #include <console/console.h> : #include <cpu/x86/mtrr.h> this is also out of order https://review.coreboot.org/c/coreboot/+/80277/comment/cdb7e30c_9249f016 : PS2, Line 12: #include <intelblocks/lpc_lib.h> same https://review.coreboot.org/c/coreboot/+/80277/comment/2fdf612b_9c1fc96b : PS2, Line 15: #include <soc/bootblock.h> same -- To view, visit https://review.coreboot.org/c/coreboot/+/80277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99 Gerrit-Change-Number: 80277 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 04:42:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: [Squash]: Add ACPI BDAT support
by Shuo Liu (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Anil Kumar K, Arthur Heymans, Bora Guvendik, Chen, Gang C, Cliff Huang, Gaggery, Jamie Ryu, Jérémy Compostella, Kane Chen, Karthik Ramasubramanian, Krishna P Bhat D, Lance Zhao, Pratikkumar V Prajapati, Ravishankar Sarawadi, Ronak Kanabar, Subrata Banik, Tim Wawrzynczak, V Sowmya, Wonkyu Kim. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77255?usp=email ) Change subject: [Squash]: Add ACPI BDAT support ...................................................................... Patch Set 14: (4 comments) Patchset: PS14: Hello, we are from server coreboot team and would like to adopt this change, with some comments. Could you please check? File src/soc/intel/common/block/acpi/acpi_bdat.c: https://review.coreboot.org/c/coreboot/+/77255/comment/acebef54_ff25913d : PS14, Line 175: memcpy(next_block, schema_data, data_size); Can we make sure in ACPI BDAT spec, all schema data are not pointers? if no pointers, the directly copy could be a pattern to apply. File src/soc/intel/common/block/include/intelblocks/acpi_bdat.h: https://review.coreboot.org/c/coreboot/+/77255/comment/dee03acd_63b636f2 : PS14, Line 66: EFI_GUID schema_hob_guids[MAX_SCHEMA_LIST_LENGTH]; Can we use base/size instead? a.k.a. some customers will create schema by themselves instead of reading HOBs from FSP (e.g. to create something beyonds FSP created HOBs, by reading registers in coreboot codes, which might be private codes, or public codes), thus giving customers some flexibility in their implementation instead of raising requests to FSP. https://review.coreboot.org/c/coreboot/+/77255/comment/d29a4a4e_3fbcad4d : PS14, Line 67: } bdat_schema_list_hob; Can we rename it as bdat_schema_list? a.k.a. an intel platform might use arbitrary way to collect the schema list but may not from a hob. -- To view, visit https://review.coreboot.org/c/coreboot/+/77255?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5eb57f65ef5f24458f09587b7c7694156f2ed1ce Gerrit-Change-Number: 77255 Gerrit-PatchSet: 14 Gerrit-Owner: Gaggery <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Gaggery <gaggery.tsai(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 04:39:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: Docs: Replace Recommonmark with MyST Parser
by Nicholas Chin (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73158?usp=email ) Change subject: Docs: Replace Recommonmark with MyST Parser ...................................................................... Patch Set 6: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/73158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804 Gerrit-Change-Number: 73158 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 04:31:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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