coreboot-gerrit February 2024

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[L] Change in coreboot[main]: lib: Move IP checksum to commonlib
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Angel Pons, Jakub Czapiga, Julius Werner, Jérémy Compostella, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80251?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: lib: Move IP checksum to commonlib ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80251/comment/cd684045_5d90b360 : PS2, Line 16: calculatted calculated? -- To view, visit https://review.coreboot.org/c/coreboot/+/80251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Gerrit-Change-Number: 80251 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 11:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: commonlib: Add assembly optimization for ipchksum() on arm64
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80254?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: commonlib: Add assembly optimization for ipchksum() on arm64 ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80254/comment/c5f9764c_139b33af : PS2, Line 10: to take advantage of larger load : sizes and the add-with-carry instruction Excuse my ignorance, but why can’t the compilers do that themselves? https://review.coreboot.org/c/coreboot/+/80254/comment/7b2020f7_84cc71a7 : PS2, Line 12: by more than 20x Thank you for documenting this. Do you also have absolute timestamps? (I have no idea, where `ipchksum()` is used.) -- To view, visit https://review.coreboot.org/c/coreboot/+/80254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c7bbc9d7a1cd083ced62fe9222592243a796077 Gerrit-Change-Number: 80254 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 11:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Config TCSS AUX according fw_config
by Weimin Wu (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Dolan Liu, Eric Lai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Subrata Banik. Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80259?usp=email ) Change subject: mb/google/nissa/var/anraggar: Config TCSS AUX according fw_config ...................................................................... Patch Set 7: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/80259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d Gerrit-Change-Number: 80259 Gerrit-PatchSet: 7 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 11:50:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80277?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80277/comment/1048e24c_a2317f61 : PS2, Line 39: In addition, this commit sets`PLATFORM_USES_FSP2_X86_32' to `n' by : default if FSP 2.4 is enabled as 64-bits FSP should be norm moving : forward. Maybe make that a separate commit, so it also gets more exposure. https://review.coreboot.org/c/coreboot/+/80277/comment/923021c0_f84e6204 : PS2, Line 42: Have you done any tests yet? Is there a difference in boot time, for example? -- To view, visit https://review.coreboot.org/c/coreboot/+/80277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99 Gerrit-Change-Number: 80277 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 11:48:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Add MTCL function to ACPI SSDT tables
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Cliff Huang, David Ruth, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80170?usp=email ) Change subject: Add MTCL function to ACPI SSDT tables ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80170/comment/cc365c7d_744b0e8d : PS14, Line 7: Add MTCL function to ACPI SSDT tables Please prefix with `drivers/wifi:`. -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 14 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 11:47:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/amd: factor out memmap from root_complex
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80272?usp=email ) Change subject: soc/amd: factor out memmap from root_complex ...................................................................... soc/amd: factor out memmap from root_complex Now that the SoC-specific memory map is reported on the domain device instead of the northbridge device, factor out the read_soc_memmap_resources function from root_complex.c to new memmap.c file. For now each SoC still has its own memmap.c file, but the plan is to eventually have a common implementation that works for all AMD family 17h+ SoCs. For that I'll still need to look closer into the differences between the FSP and the openSIL integration though. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80272 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/Makefile.mk A src/soc/amd/cezanne/memmap.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/Makefile.mk A src/soc/amd/glinda/memmap.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/Makefile.mk A src/soc/amd/mendocino/memmap.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/Makefile.mk A src/soc/amd/phoenix/memmap.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/Makefile.mk A src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/root_complex.c 15 files changed, 494 insertions(+), 479 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index 163f777..73be4aa 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -25,6 +25,7 @@ ramstage-y += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c new file mode 100644 index 0000000..6c8e932 --- /dev/null +++ b/src/soc/amd/cezanne/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 876f790..0fb086f 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -1,17 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -48,96 +42,6 @@ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (86KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (64KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk index 4570e07..1211c45 100644 --- a/src/soc/amd/glinda/Makefile.mk +++ b/src/soc/amd/glinda/Makefile.mk @@ -29,6 +29,7 @@ ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c diff --git a/src/soc/amd/glinda/memmap.c b/src/soc/amd/glinda/memmap.c new file mode 100644 index 0000000..d347bae --- /dev/null +++ b/src/soc/amd/glinda/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 9d83f6f..36942bf 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Update for Glinda */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -63,96 +57,6 @@ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk index cc44358..a72116e 100644 --- a/src/soc/amd/mendocino/Makefile.mk +++ b/src/soc/amd/mendocino/Makefile.mk @@ -27,6 +27,7 @@ ramstage-y += fsp_misc_data_hob.c ramstage-y += fsp_s_params.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c ramstage-y += manifest.c diff --git a/src/soc/amd/mendocino/memmap.c b/src/soc/amd/mendocino/memmap.c new file mode 100644 index 0000000..d347bae --- /dev/null +++ b/src/soc/amd/mendocino/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 5561240..3247eb4 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Check if this is still correct */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/amd_misc_data.h> @@ -91,96 +85,6 @@ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index 26e9102..feb9b1a 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -31,6 +31,7 @@ ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += soc_util.c ramstage-y += xhci.c diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c new file mode 100644 index 0000000..432d850 --- /dev/null +++ b/src/soc/amd/phoenix/memmap.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + if (CONFIG(PLATFORM_USES_FSP2_0)) + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 4a657f8..4ce5f2a 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Update for Phoenix */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -63,97 +57,6 @@ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - if (CONFIG(PLATFORM_USES_FSP2_0)) - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk index 94d7f7bb..3fcd47f 100644 --- a/src/soc/amd/picasso/Makefile.mk +++ b/src/soc/amd/picasso/Makefile.mk @@ -26,6 +26,7 @@ ramstage-y += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += pcie_gpp.c ramstage-y += root_complex.c ramstage-y += sata.c diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c new file mode 100644 index 0000000..7ec7adf --- /dev/null +++ b/src/soc/amd/picasso/memmap.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/memmap.h> +#include <amdblocks/iomap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 1e702ab..d4e8401 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -1,18 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> -#include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <assert.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <stdint.h> @@ -48,93 +41,6 @@ }, \ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (86KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (64KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} static void root_complex_init(struct device *dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/80272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9 Gerrit-Change-Number: 80272 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: soc/amd/phoenix/root_complex: make read_fsp_resources call conditional
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80271?usp=email ) Change subject: soc/amd/phoenix/root_complex: make read_fsp_resources call conditional ...................................................................... soc/amd/phoenix/root_complex: make read_fsp_resources call conditional Only call read_fsp_resources if PLATFORM_USES_FSP2_0 is selected in Kconfig. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic63e0904ad04dbecfac1be4d59abbb8d4f9f11d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80271 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/phoenix/root_complex.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 1394b2c..4a657f8 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -150,7 +150,8 @@ /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - read_fsp_resources(dev, idx); + if (CONFIG(PLATFORM_USES_FSP2_0)) + read_fsp_resources(dev, idx); } static void root_complex_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/80271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic63e0904ad04dbecfac1be4d59abbb8d4f9f11d0 Gerrit-Change-Number: 80271 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80270?usp=email ) Change subject: soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources ...................................................................... soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the legacy PCI config space access is needed on all AMD SoCs, implement a common add_pci_cfg_resources function that reports both and gets called from amd_pci_domain_read_resources and don't report those in the SoC- specific code any more. The only functional change is that on Genoa now the IO ports used for the legacy PCI config space access get reserved. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c 7 files changed, 8 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 2586740..876f790 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -111,8 +111,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000); @@ -134,8 +132,6 @@ */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 6573557..f5d7216 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -191,6 +191,12 @@ } } +static void add_pci_cfg_resources(struct device *domain, unsigned long *idx) +{ + fixed_io_range_reserved(domain, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + mmconf_resource(domain, (*idx)++); +} + void amd_pci_domain_read_resources(struct device *domain) { unsigned long idx = 0; @@ -203,6 +209,8 @@ /* Only add the SoC's DRAM memory map and fixed resources once */ if (domain->path.domain.domain == 0) { + add_pci_cfg_resources(domain, &idx); + read_soc_memmap_resources(domain, &idx); } } diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 37d189e..9d83f6f 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -126,8 +126,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000); @@ -149,8 +147,6 @@ */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 7291058..5561240 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -154,8 +154,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000); @@ -177,8 +175,6 @@ */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 3e61df1..1394b2c 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -126,8 +126,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000); @@ -149,8 +147,6 @@ */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index ffe4f66..1e702ab 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -111,8 +111,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000); @@ -132,8 +130,6 @@ * cbmem_top() accounts for low UMA and TSEG if they are used. */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index 1e633d9..39b27ec 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -114,8 +114,6 @@ if (mem_usable != top_mem) reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem); - mmconf_resource(dev, (*idx)++); - // Check if we're done if (top_of_mem <= 0x100000000) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/80270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850 Gerrit-Change-Number: 80270 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: pass resource index as pointer
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80269?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: pass resource index as pointer ...................................................................... vc/amd/opensil/genoa_poc/memmap: pass resource index as pointer To make add_opensil_memmap match the other function that are directly or indirectly called by amd_pci_domain_read_resources, pass the resource index as a pointer instead of passing it by value and then returning the new resource index. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80269 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/genoa_poc/domain.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c M src/vendorcode/amd/opensil/genoa_poc/opensil.h 3 files changed, 17 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index b34d2e3..711dfc3 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -15,7 +15,7 @@ void read_soc_memmap_resources(struct device *domain, unsigned long *idx) { - *idx = add_opensil_memmap(domain, *idx); + add_opensil_memmap(domain, idx); } static void genoa_domain_set_resources(struct device *domain) diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index 8b54b5f..1e633d9 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -84,11 +84,11 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL); // This assumes holes are allocated -unsigned long add_opensil_memmap(struct device *dev, unsigned long idx) +void add_opensil_memmap(struct device *dev, unsigned long *idx) { - ram_from_to(dev, idx++, 0, 0xa0000); - mmio_from_to(dev, idx++, 0xa0000, 0xc0000); // legacy VGA - reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); // Option ROM + ram_from_to(dev, (*idx)++, 0, 0xa0000); + mmio_from_to(dev, (*idx)++, 0xa0000, 0xc0000); // legacy VGA + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); // Option ROM uint32_t mem_usable = (uintptr_t)cbmem_top(); uintptr_t early_reserved_dram_start, early_reserved_dram_end; @@ -98,33 +98,33 @@ early_reserved_dram_end = e->base + e->size; // 1MB - bottom of DRAM reserved for early coreboot usage - ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start); + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); // DRAM reserved for early coreboot usage - reserved_ram_from_to(dev, idx++, early_reserved_dram_start, + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); // top of DRAM consumed early - low top usable RAM // cbmem_top() accounts for low UMA and TSEG if they are used. - ram_from_to(dev, idx++, early_reserved_dram_end, + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); // Account for UMA and TSEG const uint32_t top_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 1 * MiB); if (mem_usable != top_mem) - reserved_ram_from_to(dev, idx++, mem_usable, top_mem); + reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem); - mmconf_resource(dev, idx++); + mmconf_resource(dev, (*idx)++); // Check if we're done if (top_of_mem <= 0x100000000) - return idx; + return; // Holes in upper DRAM // This assumes all the holes in upper DRAM are continuous get_hole_info(); if (hole_info == NULL) - return idx; + return; uint64_t lowest_upper_hole_base = top_of_mem; uint64_t highest_upper_hole_end = 0x100000000; for (int hole = 0; hole < n_holes; hole++) { @@ -135,16 +135,14 @@ lowest_upper_hole_base = MIN(lowest_upper_hole_base, hole_info[hole].Base); highest_upper_hole_end = MAX(highest_upper_hole_end, hole_info[hole].Base + hole_info[hole].Size); if (hole_info[hole].Type == UMA) - mmio_range(dev, idx++, hole_info[hole].Base, hole_info[hole].Size); + mmio_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size); else - reserved_ram_range(dev, idx++, hole_info[hole].Base, hole_info[hole].Size); + reserved_ram_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size); } - ram_from_to(dev, idx++, 0x100000000, lowest_upper_hole_base); + ram_from_to(dev, (*idx)++, 0x100000000, lowest_upper_hole_base); // Do we need this? if (top_of_mem > highest_upper_hole_end) - ram_from_to(dev, idx++, highest_upper_hole_end, top_of_mem); - - return idx; + ram_from_to(dev, (*idx)++, highest_upper_hole_end, top_of_mem); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h index 77b3c4b..e225522 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h @@ -8,7 +8,7 @@ void SIL_STATUS_report(const char *function, const int status); // Add the memory map to dev, starting at index idx, returns last use idx -unsigned long add_opensil_memmap(struct device *dev, unsigned long idx); +void add_opensil_memmap(struct device *dev, unsigned long *idx); // Fill in FADT from openSIL void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); -- To view, visit https://review.coreboot.org/c/coreboot/+/80269?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d Gerrit-Change-Number: 80269 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: soc/amd: rework DRAM and fixed resource reporting
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80268?usp=email ) Change subject: soc/amd: rework DRAM and fixed resource reporting ...................................................................... soc/amd: rework DRAM and fixed resource reporting Introduce read_soc_memmap_resources which gets called by amd_pci_domain_read_resources for the first domain of the SoC to report the DRAM and PCI config space access resources to the allocator. For Genoa this allows to use amd_pci_domain_read_resources as read_resources in the genoa_pci_domain_ops instead of needing to wrap that call to be able to call add_opensil_memmap for the first domain. For the other family 17h+ SoCs the moves the reporting of the DRAM resources and the PCI config space access resources from the northbridge device to the domain device. TEST=Resources still get reported on Mandolin, but now under the domain instead of the northbridge PCI device Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib19fd94e06fa3a1d95ade7fafe22db013045a942 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80268 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/root_complex.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 8 files changed, 80 insertions(+), 90 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 20cea05..2586740 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -101,10 +101,9 @@ * | DRAM | * +--------------------------------+ 0x0 */ -static void read_resources(struct device *dev) +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -112,38 +111,35 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - /* The root complex has no PCI BARs implemented, so there's no need to call - pci_dev_read_resources for it */ - - fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); /* 0x0 - 0x9ffff */ - ram_range(dev, idx++, 0, 0xa0000); + ram_range(dev, (*idx)++, 0, 0xa0000); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start); + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end); + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); /* * top of DRAM consumed early - low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable); + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, idx++); + mmconf_resource(dev, (*idx)++); /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - read_fsp_resources(dev, &idx); + read_fsp_resources(dev, idx); } static void root_complex_init(struct device *dev) @@ -175,7 +171,9 @@ } struct device_operations cezanne_root_complex_operations = { - .read_resources = read_resources, + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .init = root_complex_init, diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 8533dff..6573557 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -200,6 +200,11 @@ add_data_fabric_mmio_regions(domain, &idx); read_non_pci_resources(domain, &idx); + + /* Only add the SoC's DRAM memory map and fixed resources once */ + if (domain->path.domain.domain == 0) { + read_soc_memmap_resources(domain, &idx); + } } static void write_ssdt_domain_io_producer_range_helper(const char *domain_name, diff --git a/src/soc/amd/common/block/include/amdblocks/root_complex.h b/src/soc/amd/common/block/include/amdblocks/root_complex.h index 0eef5e8..cac659e 100644 --- a/src/soc/amd/common/block/include/amdblocks/root_complex.h +++ b/src/soc/amd/common/block/include/amdblocks/root_complex.h @@ -22,6 +22,8 @@ void read_non_pci_resources(struct device *domain, unsigned long *idx); +void read_soc_memmap_resources(struct device *domain, unsigned long *idx); + uint32_t get_iohc_misc_smn_base(struct device *domain); const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count); diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 653e2d2..b34d2e3 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -13,16 +13,9 @@ #define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0 -static void genoa_domain_read_resources(struct device *domain) +void read_soc_memmap_resources(struct device *domain, unsigned long *idx) { - amd_pci_domain_read_resources(domain); - - // We only want to add the DRAM memory map once - if (domain->path.domain.domain == 0) { - /* 0x1000 is a large enough first index to be sure to not overlap with the - resources added by amd_pci_domain_read_resources */ - add_opensil_memmap(domain, 0x1000); - } + *idx = add_opensil_memmap(domain, *idx); } static void genoa_domain_set_resources(struct device *domain) @@ -74,7 +67,7 @@ } struct device_operations genoa_pci_domain_ops = { - .read_resources = genoa_domain_read_resources, + .read_resources = amd_pci_domain_read_resources, .set_resources = genoa_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, .init = genoa_domain_init, diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 9b53a56..37d189e 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -116,10 +116,9 @@ * | DRAM | * +--------------------------------+ 0x0 */ -static void read_resources(struct device *dev) +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -127,38 +126,35 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - /* The root complex has no PCI BARs implemented, so there's no need to call - pci_dev_read_resources for it */ - - fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); /* 0x0 - 0x9ffff */ - ram_range(dev, idx++, 0, 0xa0000); + ram_range(dev, (*idx)++, 0, 0xa0000); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start); + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end); + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); /* * top of DRAM consumed early - low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable); + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, idx++); + mmconf_resource(dev, (*idx)++); /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - read_fsp_resources(dev, &idx); + read_fsp_resources(dev, idx); } static void root_complex_init(struct device *dev) @@ -205,7 +201,9 @@ } struct device_operations glinda_root_complex_operations = { - .read_resources = read_resources, + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .init = root_complex_init, diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 886b54e..7291058 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -144,10 +144,9 @@ * | DRAM | * +--------------------------------+ 0x0 */ -static void read_resources(struct device *dev) +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -155,38 +154,35 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - /* The root complex has no PCI BARs implemented, so there's no need to call - pci_dev_read_resources for it */ - - fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); /* 0x0 - 0x9ffff */ - ram_range(dev, idx++, 0, 0xa0000); + ram_range(dev, (*idx)++, 0, 0xa0000); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start); + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end); + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); /* * top of DRAM consumed early - low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable); + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, idx++); + mmconf_resource(dev, (*idx)++); /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - read_fsp_resources(dev, &idx); + read_fsp_resources(dev, idx); } static void root_complex_init(struct device *dev) @@ -366,7 +362,9 @@ } struct device_operations mendocino_root_complex_operations = { - .read_resources = read_resources, + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .init = root_complex_init, diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 82216ae..3e61df1 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -116,10 +116,9 @@ * | DRAM | * +--------------------------------+ 0x0 */ -static void read_resources(struct device *dev) +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -127,38 +126,35 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - /* The root complex has no PCI BARs implemented, so there's no need to call - pci_dev_read_resources for it */ - - fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); /* 0x0 - 0x9ffff */ - ram_range(dev, idx++, 0, 0xa0000); + ram_range(dev, (*idx)++, 0, 0xa0000); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start); + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end); + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); /* * top of DRAM consumed early - low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable); + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, idx++); + mmconf_resource(dev, (*idx)++); /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - read_fsp_resources(dev, &idx); + read_fsp_resources(dev, idx); } static void root_complex_init(struct device *dev) @@ -205,7 +201,9 @@ } struct device_operations phoenix_root_complex_operations = { - .read_resources = read_resources, + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .init = root_complex_init, diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 0edd245..ffe4f66 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -101,10 +101,9 @@ * | DRAM | * +--------------------------------+ 0x0 */ -static void read_resources(struct device *dev) +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) { uint32_t mem_usable = (uintptr_t)cbmem_top(); - unsigned long idx = 0; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -112,36 +111,33 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; - /* The root complex has no PCI BARs implemented, so there's no need to call - pci_dev_read_resources for it */ - - fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); /* 0x0 - 0x9ffff */ - ram_range(dev, idx++, 0, 0xa0000); + ram_range(dev, (*idx)++, 0, 0xa0000); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); /* 1MB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start); + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end); + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); /* top of DRAM consumed early - low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable); + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - mmconf_resource(dev, idx++); + mmconf_resource(dev, (*idx)++); /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - read_fsp_resources(dev, &idx); + read_fsp_resources(dev, idx); } static void root_complex_init(struct device *dev) @@ -182,7 +178,9 @@ } struct device_operations picasso_root_complex_operations = { - .read_resources = read_resources, + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .init = root_complex_init, -- To view, visit https://review.coreboot.org/c/coreboot/+/80268?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib19fd94e06fa3a1d95ade7fafe22db013045a942 Gerrit-Change-Number: 80268 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2024