coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: drivers/uart/pl011: Enhance struct documentation
by Nico Huber (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Maximilian Brune. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80180?usp=email ) Change subject: drivers/uart/pl011: Enhance struct documentation ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File src/drivers/uart/pl011.h: https://review.coreboot.org/c/coreboot/+/80180/comment/ac48949d_e3dd7dec : PS1, Line 15: u32 ilpr; // offset: 0x20 Low-Power Counter Register The `i' seems to be for IrDA specifically, so please mention. https://review.coreboot.org/c/coreboot/+/80180/comment/1a16db5f_c88ee28e : PS1, Line 34: u32 cellid3; // offset: 0xFFC UART CellID3 Register Maybe it's just me, but I wouldn't repeat "Register" on every line. -- To view, visit https://review.coreboot.org/c/coreboot/+/80180?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58409b23e3790a052d3bc0ecf6a6bede15b4d76f Gerrit-Change-Number: 80180 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 16:49:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/wifi: Add MTCL function to ACPI SSDT
by David Ruth (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Arthur Heymans, Cliff Huang, David Ruth, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80170?usp=email to look at the new patch set (#16). Change subject: drivers/wifi: Add MTCL function to ACPI SSDT ...................................................................... drivers/wifi: Add MTCL function to ACPI SSDT The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Add src/drivers/wifi/generic/mtcl.c to abstract functionaltity related to MTCL * Add write_mtcl_aml function to convert the byte data into the format expected by the MTCL functionality in the Linux kernel. * Add validate_mtcl function to validate that the byte data read in from a file is in the expected format. * Add write_mtcl_function function to read a binary file called "wifi_mtcl".hex" from cbfs, then call validate_mtcl to verify that it is in an expected format, and if so write the aml via acpigen * Add config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Add config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Add config flag CONFIG_WIFI_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.hex" * Add a call to write_mtcl_function to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for MTK WiFi devices when USE_MTCL is enabled. BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.hex blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth(a)chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 --- A configs/config.google_yaviks_cros M src/drivers/wifi/generic/Kconfig M src/drivers/wifi/generic/Makefile.mk M src/drivers/wifi/generic/acpi.c A src/drivers/wifi/generic/mtcl.c M src/include/device/pci_ids.h A src/include/mtcl.h M src/mainboard/google/brya/Kconfig 8 files changed, 240 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 16 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/wifi: Add MTCL function to ACPI SSDT
by David Ruth (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Arthur Heymans, Cliff Huang, David Ruth, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80170?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: drivers/wifi: Add MTCL function to ACPI SSDT ...................................................................... drivers/wifi: Add MTCL function to ACPI SSDT The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Add src/drivers/wifi/generic/mtcl.c to abstract functionaltity related to MTCL * Add write_mtcl_aml function to convert the byte data into the format expected by the MTCL functionality in the Linux kernel. * Add validate_mtcl function to validate that the byte data read in from a file is in the expected format. * Add write_mtcl_function function to read a binary file called "wifi_mtcl".hex" from cbfs, then call validate_mtcl to verify that it is in an expected format, and if so write the aml via acpigen * Add config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Add config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Add config flag CONFIG_WIFI_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.hex" * Add a call to write_mtcl_function to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for MTK WiFi devices when USE_MTCL is enabled. BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.hex blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth(a)chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 --- A configs/config.google_yaviks_cros M src/drivers/wifi/generic/Kconfig M src/drivers/wifi/generic/Makefile.mk M src/drivers/wifi/generic/acpi.c A src/drivers/wifi/generic/mtcl.c M src/include/device/pci_ids.h A src/include/mtcl.h 7 files changed, 239 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/80170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Gerrit-Change-Number: 80170 Gerrit-PatchSet: 15 Gerrit-Owner: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: David Ruth <druth(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/volteer/drobit: Add a board-specific VBT file
by Nico Huber (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Arthur Heymans, Matt DeVillier, Nick Vaccaro. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80183?usp=email ) Change subject: mb/google/volteer/drobit: Add a board-specific VBT file ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80183?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie25a77be5204dfc8b888082492a285973843037c Gerrit-Change-Number: 80183 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 01 Feb 2024 16:40:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/up/squared: Make mini PCIe port mode configurable
by Reto Buerki (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Paul Menzel. Reto Buerki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80261?usp=email ) Change subject: mb/up/squared: Make mini PCIe port mode configurable ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80261/comment/08b8aac3_68c34e89 : PS1, Line 11: > I tried to answer this question with the sentence below in the commit message. […] Done Patchset: PS2: I changed the commit message accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/80261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Gerrit-Change-Number: 80261 Gerrit-PatchSet: 2 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 16:29:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reto Buerki <reet(a)codelabs.ch> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/up/squared: Make mini PCIe port mode configurable
by Reto Buerki (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80261?usp=email to look at the new patch set (#2). Change subject: mb/up/squared: Make mini PCIe port mode configurable ...................................................................... mb/up/squared: Make mini PCIe port mode configurable Add ENABLE_MSATA config knob and pad configuration to put Mini PCIe port into mSATA mode. The vendor firmware's "Chipset->Mini PCIe / mSATA Switch" option has been used together with the output of inteltool and intel2pm to deduce the exact pad configuration. Note: the vendor firmware does not autodetect the mode, and the default setting for the port is "Mini PCIe". Tested with Kingston SUV500MS120G mSATA SSD. Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Signed-off-by: Reto Buerki <reet(a)codelabs.ch> --- M src/mainboard/up/squared/Kconfig M src/mainboard/up/squared/gpio.h M src/mainboard/up/squared/romstage.c 3 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/80261/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Gerrit-Change-Number: 80261 Gerrit-PatchSet: 2 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/up/squared: Make mini PCIe port mode configurable
by Reto Buerki (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Paul Menzel. Reto Buerki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80261?usp=email ) Change subject: mb/up/squared: Make mini PCIe port mode configurable ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80261/comment/43f0caab_e9feeb01 : PS1, Line 11: > Thank you for the patch. […] I tried to answer this question with the sentence below in the commit message. The vendor firmware has the option "Chipset->Mini PCIe / mSATA Switch" with a default of "Mini PCIe", it does not autodetect the mode. Will try to make the commit message more precise. Patchset: PS1: Thank you for the review! -- To view, visit https://review.coreboot.org/c/coreboot/+/80261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Gerrit-Change-Number: 80261 Gerrit-PatchSet: 1 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 16:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in em100[main]: em100: free device list when calling em100 --list
by Name of user not set (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Jakub Czapiga, Stefan Reinauer. c.koehne(a)beckhoff.com has posted comments on this change. ( https://review.coreboot.org/c/em100/+/80248?usp=email ) Change subject: em100: free device list when calling em100 --list ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hi, I've found you in the git history. Hope you're the right people to review this change. Thanks! -- To view, visit https://review.coreboot.org/c/em100/+/80248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: main Gerrit-Change-Id: Id1849bb69d534928016256dd01e9550ef414d330 Gerrit-Change-Number: 80248 Gerrit-PatchSet: 1 Gerrit-Owner: c.koehne(a)beckhoff.com Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2024 15:37:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80287?usp=email ) Change subject: vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h ...................................................................... vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h Provide 3 separate functions for each openSIL time point instead of one, so that we don't need the xSIM-api header file to be included in opensil.h to decouple the coreboot code more form the openSIL code. This will allow to create an openSIL stub implementation to already get most of the coreboot-side SoC code in place before the openSIL source code is done and released. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc --- M src/soc/amd/genoa_poc/chip.c M src/vendorcode/amd/opensil/genoa_poc/opensil.h M src/vendorcode/amd/opensil/genoa_poc/ramstage.c 3 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/80287/1 diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c index d397800..13ede84 100644 --- a/src/soc/amd/genoa_poc/chip.c +++ b/src/soc/amd/genoa_poc/chip.c @@ -11,7 +11,7 @@ default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; setup_opensil(); - opensil_entry(SIL_TP1); + opensil_xSIM_timepoint_1(); fch_init(chip_info); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h index e225522..334903f 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h @@ -4,7 +4,6 @@ #define _OPENSIL_H_ #include <acpi/acpi.h> -#include <xSIM-api.h> void SIL_STATUS_report(const char *function, const int status); // Add the memory map to dev, starting at index idx, returns last use idx @@ -15,6 +14,8 @@ void configure_mpio(void); void setup_opensil(void); -void opensil_entry(SIL_TIMEPOINT timepoint); +void opensil_xSIM_timepoint_1(void); +void opensil_xSIM_timepoint_2(void); +void opensil_xSIM_timepoint_3(void); #endif diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c index 11289bb..758b284 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c @@ -129,7 +129,7 @@ configure_mpio(); } -void opensil_entry(SIL_TIMEPOINT timepoint) +static void opensil_entry(SIL_TIMEPOINT timepoint) { SIL_STATUS ret; SIL_TIMEPOINT tp = (uintptr_t)timepoint; @@ -160,4 +160,19 @@ } } +void opensil_xSIM_timepoint_1(void) +{ + opensil_entry(SIL_TP1); +} + +void opensil_xSIM_timepoint_2(void) +{ + opensil_entry(SIL_TP2); +} + +void opensil_xSIM_timepoint_3(void) +{ + opensil_entry(SIL_TP3); +} + /* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80287?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc Gerrit-Change-Number: 80287 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd: commonize PCI root IOAPIC initialization
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80286?usp=email ) Change subject: soc/amd: commonize PCI root IOAPIC initialization ...................................................................... soc/amd: commonize PCI root IOAPIC initialization Make the initialization of the IOAPIC(s) in the PCI root(s) common across all AMD family 17h+ SoCs. For this the more general implementation from the Genoa code that supports multiple PC roots is moved to the common AMD code. All other family 17h+ SoCs are then adapted to use the common code. For those non-Gena SoCs, the initialization of this second IOAPIC is moved from the northbridge device to the domain device above to match Genoa. Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized on Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16 --- M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/include/amdblocks/root_complex.h M src/soc/amd/common/block/root_complex/Makefile.mk A src/soc/amd/common/block/root_complex/ioapic.c M src/soc/amd/genoa_poc/domain.c M src/soc/amd/glinda/chip.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/chip.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/root_complex.c 14 files changed, 36 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/80286/1 diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index ffbd94a..7d315cb 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -3,6 +3,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> +#include <amdblocks/root_complex.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,6 +30,7 @@ .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 0fb086f..72a2419 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -42,11 +42,6 @@ }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_cezanne_config *config = config_of_soc(); @@ -76,7 +71,6 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/common/block/include/amdblocks/root_complex.h b/src/soc/amd/common/block/include/amdblocks/root_complex.h index cac659e..767221e 100644 --- a/src/soc/amd/common/block/include/amdblocks/root_complex.h +++ b/src/soc/amd/common/block/include/amdblocks/root_complex.h @@ -31,4 +31,6 @@ void read_fsp_resources(struct device *dev, unsigned long *idx); +void amd_pci_domain_init(struct device *domain); + #endif /* AMD_BLOCK_ROOT_COMPLEX_H */ diff --git a/src/soc/amd/common/block/root_complex/Makefile.mk b/src/soc/amd/common/block/root_complex/Makefile.mk index ba550bd..07f3ab1 100644 --- a/src/soc/amd/common/block/root_complex/Makefile.mk +++ b/src/soc/amd/common/block/root_complex/Makefile.mk @@ -1,2 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX) += non_pci_resources.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX),y) + +ramstage-y += ioapic.c +ramstage-y += non_pci_resources.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX diff --git a/src/soc/amd/common/block/root_complex/ioapic.c b/src/soc/amd/common/block/root_complex/ioapic.c new file mode 100644 index 0000000..cdeb532 --- /dev/null +++ b/src/soc/amd/common/block/root_complex/ioapic.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/ioapic.h> +#include <amdblocks/root_complex.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <device/resource.h> +#include <types.h> + +void amd_pci_domain_init(struct device *domain) +{ + struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX); + if (!res) + return; + + register_new_ioapic((void *)(uintptr_t)res->base); +} diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 711dfc3..14248cd 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -42,15 +42,6 @@ } } -static void genoa_domain_init(struct device *domain) -{ - struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX); - if (!res) - return; - - register_new_ioapic((void *)(uintptr_t)res->base); -} - static const char *genoa_domain_acpi_name(const struct device *domain) { const char *domain_acpi_names[4] = { @@ -70,7 +61,7 @@ .read_resources = amd_pci_domain_read_resources, .set_resources = genoa_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, - .init = genoa_domain_init, + .init = amd_pci_domain_init, .acpi_name = genoa_domain_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index 13933c7..c8b4d08 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -5,6 +5,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> +#include <amdblocks/root_complex.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -31,6 +32,7 @@ .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 36942bf..d51fef2 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -57,11 +57,6 @@ }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_glinda_config *config = config_of_soc(); @@ -106,7 +101,6 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 0bb9637..99f57aa 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -3,6 +3,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> +#include <amdblocks/root_complex.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,6 +30,7 @@ .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 3247eb4..2179833 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -85,11 +85,6 @@ }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_mendocino_config *config = config_of_soc(); @@ -267,7 +262,6 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index 2291945..7fc89ad 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -5,6 +5,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> +#include <amdblocks/root_complex.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -31,6 +32,7 @@ .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 4ce5f2a..918b7bd 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -57,11 +57,6 @@ }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_phoenix_config *config = config_of_soc(); @@ -106,7 +101,6 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index d896a83..d2070c1 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -3,6 +3,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> +#include <amdblocks/root_complex.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -30,6 +31,7 @@ .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index d4e8401..dd39cb2 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -42,11 +42,6 @@ }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_picasso_config *config = config_of_soc(); @@ -85,7 +80,6 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/80286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16 Gerrit-Change-Number: 80286 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit February 2024